Semiconductor component

Abstract

A semiconductor component (10, 10', 10'') having the following features: a first circuit layer (12) having at least one integrated circuit; and a second circuit layer (14, 14', 14'') having at least one power supply (14s) designed to supply the integrated circuit (12i) with electrical energy; a second main surface (12h2) of the first circuit layer (12) being connected to a first or second main surface (14h2) of the second circuit layer (14, 14', 14'').

Description

[0001] semiconductor component

[0002] Description

[0003] Embodiments of the present invention relate to a semiconductor component, in particular to one with 3D integration face-to-face power supply. Further embodiments relate to a corresponding manufacturing method.

[0004] Until now, the power supply of an integrated circuit, or more generally a circuit or a 3D stack of circuits, has been realized by external power supplies, such as DC-DC converters or on-chip DC-DC converters. On-chip DC-DC converters can then, for example, be located in the same circuit layer or the same 3D stack of circuit layers. With the latest circuit technologies, such as 3 nm technology, on-chip DC-DC converters are no longer (technically) feasible. The reason for this is that the corresponding transistors no longer have sufficient dielectric strength and / or current-carrying capacity. Even external DC-DC converters can no longer guarantee the necessary supply voltage stability.Background: The supply voltage has been repeatedly reduced in recent years, although the permissible deviation from the nominal supply voltage has remained roughly the same, resulting in significantly higher demands on the overall solution. However, this is generally no longer feasible with an external power supply, as the supply lines would otherwise be too long.

[0005] Therefore, there is a need for an improved approach. The object of the present invention is to create a power supply for the latest circuit technologies, such as 3 nm technology, that eliminates or minimizes the disadvantages in terms of manufacturability and supply voltage stability.

[0006] The problem is solved by the subject matter of the independent patent claims.

[0007] Embodiments of the present invention provide a semiconductor component having a first circuit layer and a second circuit layer. The first circuit layer comprises at least one integrated circuit, such as a memory and / or logic circuit. The second circuit layer comprises at least one power supply configured to supply the integrated circuit with electrical energy. A second main surface of the first circuit layer (e.g., a front side / face) is connected to a first or second main surface (front or back side, depending on the embodiment) of the second circuit layer.

[0008] Embodiments of the present invention are based on the realization that, through a novel package technology such as 3D integration, it is possible to produce very compact implementations of various components in a chip stack. For this purpose, the circuits are stacked on top of one another in 3D integration. Within the first circuit layer, the one or more circuits that are provided with the actual logic or memory function are arranged or constructed as a 3D stack. A novel manufacturing technology such as 3 nm technology can be used for this circuit layer or these circuit layers. The associated power supply is then arranged in a second circuit layer. Because the two circuit layers are directly adjacent to one another, e.g.By connecting the two circuit layers, e.g., by bonding or using copper pillars, the line lengths are extremely short, allowing voltage stability to be achieved according to the application. By using a separate circuit layer, a different manufacturing technology can be used than for the first circuit layer, which then also facilitates the manufacturability of high-performance power supplies. Furthermore, embodiments of the present invention advantageously provide a power supply that is implemented directly at the load.

[0009] According to embodiments, the integrated circuit of the first circuit layer (or generally the first circuit layer) is manufactured using a first semiconductor manufacturing technology (e.g., 3 nm technology), wherein the at least one power supply of the second circuit layer or generally the second circuit layer is manufactured using a second semiconductor manufacturing technology. The first semiconductor manufacturing technology differs from the second semiconductor manufacturing technology. According to embodiments, the first semiconductor manufacturing technology may, for example, comprise 3 nm technology or a better or further miniaturized semiconductor manufacturing technology.

[0010] Three exemplary embodiments of 3D integration are explained below. According to a first variant, the second circuit layer can be coupled to the first circuit layer using a face-to-back connection. In this case, the first main surface of the second circuit layer is connected to the second main surface of the first circuit layer.

[0011] According to a second variant, the first and second circuit layers can be connected face-to-face. In this case, the second main surface of the first circuit layer is connected to the second main surface of the second circuit layer. In these two circuit layers, the materials, in particular semiconductor materials, of the two circuit layers can, for example, be approximately the same width, resulting in a 3D structure.

[0012] According to a third variant, it would also be conceivable for the second circuit layer to contain a mold material. In this case, for example, the two circuit layers are connected face-to-face with a mold. This means that the second main surfaces of the first and second circuit layers are connected to each other.

[0013] According to embodiments, the connection of the second main surface of the first circuit layer to the first or second main surface of the second circuit layer is a direct connection, a direct-bonded connection, a bonded connection, a connection with a contact pad, or a connection with a copper contact pad (copper pillar). According to embodiments, the second circuit layer covers the (entire) area of ​​the first circuit layer. In other words, this means that these two circuit layers are the same size. According to embodiments, the second circuit layer has a semiconductor material across the entire width of the first circuit layer. According to other embodiments, the second circuit layer has a first region with a semiconductor material and at least one second region with a mold material. There can also be a plurality of second regions, e.g.be provided laterally next to the semiconductor region. For example, the first and second regions can extend across the (entire) width of the first circuit layer. Alternatively, each of the two regions can also have subregions, so that the entire width is defined by the first and second regions, each with one or more subregions, whereby the subregions can also be designed differently.

[0014] According to a further embodiment, the first main surface of the second circuit layer has contacts or a contacting layer if the second main surface serves for connection to the first circuit layer. Alternatively, the second main surface of the second circuit layer has contacts or a contacting layer if the first main surface serves for contacting to the first circuit layer. According to embodiments, the contacts are designed to be connected to an unregulated voltage source. According to embodiments, the power supply is designed to generate a regulated voltage on the side of the second main surface of the first circuit layer, ie, based on an applied unregulated voltage of an unregulated voltage source.Depending on the structure, it must be provided via its first or second main surface in order to supply the integrated circuit with electrical energy (power supply).

[0015] According to embodiments, the second circuit layer has one or more vias that extend across the thickness of the second circuit layer and are configured to create a signal contact for the integrated circuit. According to embodiments, the one or more vias can extend through the semiconductor material of the second circuit layer or through a mold material of the second circuit layer. In this respect, these two embodiments advantageously enable signal contacting of the integrated circuit of the first circuit layer to be achieved via the main surface of the second circuit layer facing away from the first circuit layer.

[0016] As already indicated above, each circuit layer can have one or more planes, so that a 3D integrated circuit is formed for each circuit layer. According to embodiments, the second main surface of the first circuit layer and / or the second main surface of the second circuit layer can have a rewiring layer and / or a component layer. This rewiring layer is then used, for example, to establish contact with the other circuit layer.

[0017] According to further embodiments, the semiconductor component has a further circuit layer. This further circuit layer is arranged on a first main surface of the first circuit layer. For example, this further circuit layer can comprise an integrated circuit, a logic circuit, and / or a memory.

[0018] A further embodiment provides a manufacturing method for the semiconductor component explained above. The manufacturing method includes the step of connecting the first circuit layer to the second circuit layer. According to embodiments, the connection can be made by bonding, direct bonding, or by establishing a contact pad connection or a copper contact pad connection. According to embodiments, the connection is made using face-to-back technology or face-to-face technology.

[0019] Embodiments of the present invention are explained with reference to the accompanying drawings. They show:

[0020] Fig. 1 is a schematic diagram of a semiconductor device in cross-sectional view having a face-to-back arrangement according to embodiments;

[0021] Fig. 2 is a schematic representation of a semiconductor device in a sectional view having a face-to-face arrangement according to a further embodiment; and

[0022] Fig. 3 is a schematic representation of a semiconductor component with a mold in sectional view, which has a face-to-face arrangement, according to a further embodiment.

[0023] Before exemplary embodiments of the present invention are explained below with reference to the accompanying drawings, it should be noted that the same elements and structures are provided with the same reference numerals, so that the description of them is applicable or interchangeable.

[0024] Fig. 1 shows a semiconductor component 10 with at least two circuit layers 12 and 14. These two circuit layers are provided one on top of the other, i.e. directly adjacent to one another or even directly connected to one another. For example, the two circuit layers 12 and 14 can have an identical, similar or at least comparable width and together form a chip or a semiconductor component 10. Optionally, a third circuit layer 16 can also be provided, which will not be discussed in connection with the basic embodiment. The first circuit layer 12 is, for example, the upper circuit layer, while the circuit layer 14 is the lower circuit layer. The upper circuit layer 12 is connected to the second circuit layer 14 by a second main surface 12h2, i.e. by its underside.Here, the second main surface 12h2 of the first circuit layer is connected to the first main surface 14h1 of the second circuit layer 14. The main surface 12h2 is the front side of the first circuit layer 12, while the circuit layer 14h1 can be referred to as the back side of the second circuit layer 14. The front side of the second circuit layer 14 is designated by the reference symbol 14h2. The described arrangement results in a so-called face-to-back (front-to-back) arrangement of the two circuit layers 12 and 14, forming a 3D stack of circuits.

[0025] The two circuit layers 12 and 14 can of course also comprise multiple layers of regions, such as semiconductor regions, doped regions, insulating regions, or conductive regions (metallization layer), in order to produce the electrical components intended for the respective circuit layer 12 and 14. The component or circuit layer 12 comprises, for example, one or more integrated circuits 12i, which form, for example, a logic or a memory. According to embodiments, the entire circuit layer 12 is manufactured using a manufacturing technology, such as 3 nm semiconductor manufacturing technology, so that the circuit layer 12, which, for example, has a common semiconductor material (in different layers), can be referred to as a component or even as a chip.

[0026] Circuit layer 14 comprises a power supply 14s, e.g., a DC-DC converter. Power supply 14 serves to supply integrated circuit 12i with a correspondingly stabilized voltage. For example, power supply 14s is electrically coupled to an optional rewiring layer 12u of circuit layer 12 via contacts 14sk on surface 14h1. This results in very short line lengths, which is advantageous for the stabilized voltage. By fabricating power supply 14s in a separate component or separate circuit layer 14, a different manufacturing technology can be used here compared to circuit layer 12, e.g., an older circuit technology or, generally, one that is advantageous for manufacturing components for power supplies.

[0027] The exemplary embodiment can therefore be described in such a way that two circuit layers 12 and 14 are connected to one another by means of a face-to-back arrangement. For example, direct bond technology (direct bonding or generally bonding) or the use of copper pillars (=copper connection pads or generally connection pads, alternatively: copper pillow) can be used for the connection. It should be noted at this point that, according to exemplary embodiments, the power supply 14s can have one or more DC-DC converters. Since it is assumed, for example, that the power supply 14s is supplied with unregulated voltage from the underside 14h2 (second main surface), the DC-DC converter 14s can perform voltage regulation such that a highly adjusted voltage is provided without major fluctuations with sufficient electrical energy. The unregulated voltage can be applied, for example, via the contact terminals 14sk2.

[0028] Furthermore, according to further embodiments, the circuit layer 14 may have one or more vias (tsv), which are marked, for example, with the reference symbol 14tsv. These serve, for example, to establish a direct connection (electrical connection) from the second main surface 14h2 to the first main surface 14h1. This allows a signal to be applied from the outside to the integrated circuit 12i. Signal vias are marked with the reference symbol 14tsvs.

[0029] According to a further exemplary embodiment, a further circuit layer 16 can be arranged, for example, on the first main surface 12h1 (top side). This, in turn, is arranged with its underside 16h2 (second main surface) and, according to exemplary embodiments, can comprise an integrated circuit, such as a logic or a memory (not shown). In the exemplary embodiments present here, the underside 16h2, 14h2 and 12h2 can be characterized in that it has a rewiring layer 12u, 16u or 14u. The rewiring layer serves to electrically contact the individual components in the semiconductor region and can, for example, be embodied as metallization. Instead of the rewiring layer, a type of transistor layer can of course also be provided, wherein, for example, parts of the transistors can also be formed in the semiconductor region.The rewiring layer also serves, for example, for external contacting, as is particularly evident from the rewiring layer 14u.

[0030] A further embodiment is explained below with reference to Fig. 2.

[0031] Fig. 2 shows a semiconductor component 10', again with two circuit layers 12 and 14', as well as an optional circuit layer 16. The circuit layer 12 essentially corresponds to the circuit layer 12 from Fig. 1 and comprises, for example, the integrated circuit 12i. The circuit layer 12 is connected to the circuit layer 14' via its second main surface 12h2. The circuit layer 14' is fundamentally comparable to the circuit layer 14 from Fig. 1 and, for example, likewise has the DC converter 14s as a power supply. In this exemplary embodiment, however, the circuit layer 14' is not connected to the main surface 14h1, but to the main surface 14h2 with the circuit layer 12. As mentioned at the beginning, this second main surface 14h2 can, for example, have the rewiring layer 14u.

[0032] This arrangement is called a face-to-face arrangement. With this arrangement, the path from the DC-DC converter 14s to the actual circuit 12i is extremely short. The DC-DC converter 14s can also be manufactured using an older circuit technology. This supplies the system with an unregulated voltage from the underside (side of circuit layer 14), see connections 14sk2, with the voltage regulation in the circuit being carried out by the DC-DC converter 14h2. The "normal" signals of the circuit with the logic and memory 12i are routed to the outside via the vias 14tsvs through the circuit 14' with the DC-DC converter 14s.

[0033] Referring to Fig. 3, a so-called face-to-face arrangement with a mold is explained. Fig. 3 shows the semiconductor arrangement 10" with the circuit layers 12, 14" and the optional circuit layer 16.

[0034] Circuit layer 14" is a further development of circuit layer 14' and, in addition to the semiconductor material or the first material in the area of ​​the voltage supply 14s, comprises another material. This additional material is designated here by reference numerals 14m1 and 14m2 and can, for example, comprise a molding material. Layer 14" is in turn coupled by its second main surface 14h2 to the second main surface 12h2 of the first circuit layer 12.

[0035] In this respect, the exemplary embodiment presented here creates a so-called face-to-face arrangement with a mold arrangement. The line length from the DC-DC converter to the "normal" circuit 12i remains extremely short. Furthermore, it is also ensured that the DC-DC converter 14 or the general power supply 14s can be manufactured using older circuit technology or an adapted circuit technology. At this point, it should be noted that both the semiconductor component 10' from Fig. 2 and the semiconductor component 10" from Fig. 3 can also have the additional features "vias 14tsv or 14tsvs" and "voltage contacts 14sk2". As can be seen from the exemplary embodiment in Fig. 3, the vias 14tsv can extend in the mold material 14m1 and 14m2, although an extension through the semiconductor material 14h would of course also be conceivable. For example, the power supply vias extend here, seeContact 14sk2 through the semiconductor material 14h to the rewiring layer 14u, so that the unregulated voltage of the power supply 14s is provided via this rewiring layer 14u, wherein the power supply 14s then regulates the voltage accordingly.

[0036] It is worth mentioning that, for the vias 14tsv and 14tsvs, which extend from the mold material 14m1 and 14m2, the vias 14tsv and 14tsvs, respectively, extend to the rewiring layer 12u, while the vias 12sk2, which extend through the semiconductor material 14h, extend to the rewiring layer 14u. In the embodiment of Fig. 2, all vias extend, for example, to the rewiring layer 14u (cf. 14tsv, 14tsvs, 14sk2).

[0037] According to a preferred embodiment, vias 14tsv and 14tsvs in the mold area 14m1 and 14m2 are used for signal conduction (control signal for the logic / memory), while vias 14sk2 are used to conduct a current / voltage signal. An external current or voltage signal for the power supply 14s can thus be provided via these vias 14sk2. According to embodiments, contacts are provided on the main surface 14h1 (facing away from the circuit layer 12), namely in the area 14m1 and 14m2 and in the area 14h. The contacts in the area 14h are used for the current / voltage supply. The contacts in the area 14m1 and 14m2 are used to couple a signal. It is advantageous that the signal is passed through the mold material and is thus largely separated from disturbing influences from the chip that houses the power supply.The insulating properties of the mold material also have a positive technical effect.

[0038] In all of the above embodiments from Figs. 1 to 3, the two circuit layers 12 and 14 can be connected by means of direct bonding or copper pillars. A copper pillar is designated by reference numeral 13k. However, it should also be noted at this point that other connection options are conceivable. All embodiments have in common that the novel 3D integration package technology enables very compact implementations for various components in a chip stack. For this purpose, circuits are stacked on top of one another in 3D integration. In this case, this is one or more of the circuits that are provided with the actual (logic or memory) function and are constructed as a 3D stack. External components that have different requirements, such as the power supply 14s, can be outsourced to another circuit layer.

[0039] At this point, it should be noted that the above embodiment always assumed two or three circuit layers, although several circuit layers (i.e., more than three) would of course also be conceivable. The optional circuit layers 16 in particular can also be arranged rotated relative to the other circuit layers 12 and 14 (or 14' or 14"). In the above embodiment, it was always assumed that the second circuit layer 14 is connected either to layer 14h1 or to layer 14h2 (cf. circuit structure 10' or 10"). On the side of the first circuit layer 12, the main surface 12h2 is always used.According to further embodiments, a coupling via the main surface 12h1 to the second circuit layer 14 would also be conceivable, wherein the connection via the main surface 12h2 has the advantage that the rewiring layer 12u is provided here, via which the supply voltage can be easily supplied to the integrated circuits 12i.

[0040] Applications for the 3D integration discussed above include semiconductor components that may contain a semiconductor material, such as silicon or gallium arsenide, at least in certain regions. Applications are not limited by functional focus, meaning that any component, be it memory devices or processors (logic), is a potential application area for 3D integration.

[0041] Further exemplary embodiments relate to a manufacturing method of the exemplary embodiments 10, 10', 10" explained above. The manufacturing method comprises the central step of connecting the first and second circuit layers 12 and 14 or 12 and 14' or 12 and 14", i.e. using face-to-back technology, face-to-face technology or face-to-face technology with a mold. As already explained above, the connection can be made using contact pads or copper contact pads, but also using bonding or direct bonding. Even if exemplary embodiments were explained in particular in connection with a device (semiconductor component, 3D layer stack or chip), it should be noted that the explanations of the individual product features can simultaneously represent the explanations of the corresponding method step. Conversely, the explanation of the method step can also be interpreted as an explanation of a product step.The scope of protection is defined by the following patent claims.

Claims

Patent claims 1. Semiconductor device (10, 10', 10") with the following features: a first circuit layer (12) with at least one integrated circuit; and a second circuit layer (14, 14', 14") with at least one power supply (14s) configured to supply the integrated circuit (12i) with electrical energy; wherein the second circuit layer (14, 14', 14") has a first region with a semiconductor material and at least a second region with a mold material (14m1, 14m2), wherein the first and second regions extend over the width of the first circuit layer (12) and wherein a second main surface (12h2) of the first circuit layer (12) is connected to a first or second main surface (14h2) of the second circuit layer (14, 14', 14").wherein the second circuit layer (14, 14', 14") has one or more vias (14tsv, 14tsvs) extending over the thickness of the second circuit layer (14, 14', 14") and configured to provide a signal contact for the integrated circuit; and wherein the one or more vias (14tsv, 14tsvs) extend through a mold material (14m1, 14m2) of the second circuit layer (14, 14', 14").

2. Semiconductor device (10, 10', 10") according to claim 1, wherein the connection of the second main surface (12h2) of the first circuit layer (12) to the first or second main surface (14h2) of the second circuit layer (14, 14', 14") comprises a direct connection, a direct-bonded connection, a bonded connection, a connection with a contact pad (13k) or a connection with a copper contact pad.

3. Semiconductor device (10, 10', 10") according to any one of the preceding claims, wherein the integrated circuit (12i) comprises logic / or memory.

4. Semiconductor device (10, 10', 10") according to one of the preceding claims, wherein the power supply (14s) comprises a DC-DC converter. Semiconductor device (10, 10', 10") according to any one of the preceding claims, wherein the second circuit layer (14, 14', 14") covers the area of ​​the first circuit layer (12); and / or wherein the second circuit layer (14, 14', 14") comprises a semiconductor material over the width of the first circuit layer (12). Semiconductor device (10, 10', 10") according to any one of claims 1 to 4, wherein the first main surface (14h1) of the second circuit layer (14, 14', 14") has contacts if the second main surface serves for connection with the first circuit layer (12), or wherein the second main surface (14h2) of the second circuit layer (14, 14', 14") has contacts if the first main surface serves for contacting the first circuit layer (12).Semiconductor device (10, 10', 10") according to one of the preceding claims, wherein the semiconductor device has contacts on a main surface of the second circuit layer facing away from the second circuit layer, wherein the contacts are arranged and configured in the first region to conduct a current / voltage signal, and / or wherein the contacts are arranged and configured in the second region to conduct a control signal.Semiconductor device (10, 10', 10") according to claim 7, wherein the power supply (14s) is configured to provide a regulated voltage on the side of the second main surface (12h2) of the first circuit layer (12) for the power supply (14s) for the integrated circuit (12i) starting from an applied unregulated voltage of an unregulated voltage source; and / or in combination with an unregulated voltage source wherein the contacts (14sk2) are configured to be connected to an unregulated voltage source.

9. Semiconductor device (10, 10', 10") according to one of the preceding claims, wherein the one or more vias (14tsv, 14tsvs) are formed by a semiconductor material of the second circuit layer (14, 14', 14").

10. Semiconductor device (10, 10', 10") according to any one of the preceding claims, wherein the one or more vias of the second circuit layer are configured to carry a control signal; and / or wherein the second circuit layer has one or more further vias extending through the first region and configured to carry a current / voltage signal to the power supply. 1 1 . Semiconductor device (10, 10', 10") according to one of the preceding claims, wherein the second main surface (12h2) of the first circuit layer (12) and / or the second main surface (14h2) of the second circuit layer (14, 14', 14") comprises a rewiring layer and / or a component layer.

12. Semiconductor device (10, 10', 10") according to one of the preceding claims, wherein a further circuit layer with an integrated circuit, logic and / or memory is arranged on a first main surface (12h 1 ) of the first circuit layer (12).

13. Semiconductor device (10, 10', 10") according to any one of the preceding claims, wherein the integrated circuit (12i) of the first circuit layer (12) is manufactured using a first semiconductor fabrication technology and wherein the at least one power supply (14s) of the second circuit layer (14, 14', 14") is manufactured using a second semiconductor fabrication technology; and wherein the first fabrication technology differs from the second fabrication technology and / or wherein the first semiconductor fabrication technology comprises a 3 nm technology or better.

14. Manufacturing method for producing a semiconductor device (10, 10', 10") according to any one of the preceding claims, wherein the manufacturing method is The step comprises connecting the first circuit layer (12) to the second circuit layer (14, 14', 14"). The manufacturing method according to claim 14, wherein the connecting is performed by bonding, direct bonding, or creating a contact pad connection or copper- A contact pad connection is made. A manufacturing method according to claim 15 or 16, wherein the connection is made using face-to-back or face-to-face technology.

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