Piezoelectric-on-insulator (POI) substrate and method for producing a piezoelectric-on-insulator (POI) substrate

Abstract

The invention relates to a piezoelectric-on-insulator (POI) substrate (100) comprising a support substrate (102), in particular a silicon-based substrate, a piezoelectric layer (108), in particular a layer of lithium tantalate (LTO) or lithium niobate (LNO), a dielectric layer (106), in particular a layer of silicon oxide, sandwiched between the piezoelectric layer (108) and the support substrate (102), and a trapping structure (104) sandwiched between the dielectric layer (106) and the support substrate (102). The trapping structure (104) comprises at least two trapping layers (104a, 104b) which are based on different materials. The invention also relates to a method for producing a piezoelectric-on-insulator (POI) substrate.

Description

Description Title of the invention: Piezoelectric substrate on insulator (POI) and method for manufacturing a piezoelectric substrate on insulator (POI)

[0001] The invention relates to a piezoelectric substrate on insulator (POI) comprising in this order a support substrate, a trapping structure, a dielectric layer and a piezoelectric layer, as well as a method for manufacturing such a POI substrate.

[0002] Such substrates are known in the state of the art, for example, a POI substrate comprising a monocrystalline silicon substrate, a polycrystalline silicon trapping structure, a silicon oxide layer, and a piezoelectric layer, in particular a lithium tantalate (LTO) or lithium niobate (LNO) layer. The trapping structure reduces losses due to parasitic conduction effects at the interface between the substrate and the dielectric layer. Indeed, the trapping layer, which is inserted between the substrate and the dielectric layer, serves to reduce the lifetime of charges in this region.

[0003] However, it has been observed that during heat treatments during or after the fabrication of POI substrates, metallic elements from the piezoelectric layer, such as lithium, can diffuse through the dielectric layer and the trapping structure to the interface with the substrate. The accumulation of these metallic elements reduces the performance of the trapping structure, and the suppression of parasitic currents is thus negatively affected.

[0004] It is possible to increase the thickness of the trapping layer to increase the number of available traps. However, in this case, spurious modes appear in devices using the POI substrate, such as filters, sensors, etc.

[0005] The object of the invention is therefore to increase the number of traps with less risk of the appearance of parasitic effects.

[0006] The object of the invention is realized by a piezoelectric substrate on an insulator (POI) comprising: a support substrate, in particular a silicon-based substrate; a piezoelectric layer, in particular a lithium tantalate (LTO) or lithium niobate (LNO) layer; a dielectric layer, in particular a silicon oxide layer, sandwiched between the piezoelectric layer and the support substrate; and a trapping structure sandwiched between the dielectric layer and the support substrate, comprising a first trapping layer based on polycrystalline, amorphous, or porous silicon, preferably based on polycrystalline silicon. This POI substrate is characterized in that the trapping structure comprises a second trapping layer based on a different material.

[0007] Adding a second trapping layer with a different material in the trapping structure makes it possible to increase the number of traps, without having to increase the total thickness of the trapping structure to the same extent as would be necessary in the case of a single-material trapping structure.

[0008] In one embodiment, the second trapping layer can be silicon carbide-based. A second silicon carbide-based layer effectively reduces parasitic currents.

[0009] In one embodiment, the second silicon carbide-based trapping layer can be thinner than the first layer. Thus, the addition of a thinner silicon carbide layer increases the number of traps while limiting the occurrence of parasitic modes due to the presence of the trapping structure, particularly compared to a single-material silicon-based trapping layer with the same number of traps.

[0010] According to one embodiment, the second silicon carbide-based trapping layer can have a thickness less than or equal to 500 nm, in particular a thickness less than or equal to 200 nm, and more particularly less than or equal to 50 nm. Even for such small thicknesses, a sufficient increase in the number of traps is observed.

[0011] In one embodiment, the first silicon-based trapping layer can have a thickness less than or equal to 2 µm, in particular a thickness less than or equal to 1 µm. By using a second trapping layer, it becomes possible to keep the thickness of the first trapping layer sufficiently small. Thus, parasitic modes due to this layer cannot develop, or at least their contribution remains negligible.

[0012] In one embodiment, the second trapping layer can be formed directly on top of the first trapping layer. This allows for the maintenance of a compact structure.

[0013] In one embodiment, the first trapping layer is positioned between the support substrate and the second trapping layer. This facilitates the formation of the trapping structure, as a silicon carbide layer is deposited at a lower temperature than a silicon layer.

[0014] According to one embodiment, the trapping structure comprises only the first trapping layer and the second trapping layer.

[0015] According to one embodiment, the trapping structure is arranged directly on the substrate and the dielectric layer is arranged directly on the trapping structure.

[0016] The object of the invention is also realized by a method for manufacturing a piezoelectric substrate on an insulator (POI) as described above and comprising the steps of: providing a support substrate, in particular a silicon-based substrate; providing a substrate comprising a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO); forming a trapping structure over the support substrate; forming a dielectric layer, in particular a silicon oxide layer, over the substrate comprising a piezoelectric layer and / or over the trapping structure; and assembling the piezoelectric substrate with the support substrate such that the dielectric layer and the trapping structure are sandwiched between the piezoelectric layer and the support substrate, characterized in that the formation of the trapping structure comprises the formation of a first layer. based on polycrystalline or amorphous or porous silicon, preferably based on polycrystalline silicon, and the formation of a second trapping layer based on a different material.

[0017] According to one embodiment, the manufacturing process for a piezoelectric substrate may further include a step of: forming a weakened zone within the piezoelectric layer, particularly before the assembly step, and creating a fracture along the weakened zone to separate a portion of the piezoelectric layer from the remainder of the substrate, including the piezoelectric layer, after the assembly step, in order to transfer the portion of the piezoelectric layer onto the support substrate. This process allows for the industrial production of the POI substrates according to the invention.

[0018] The invention and its advantages are described in more detail below by means of exemplary advantageous embodiments and by reference in particular to the following accompanying figures, in which the reference numbers identify features of the invention.

[0019] . [Figure 1] schematically represents a piezoelectric substrate on insulator (POI) according to a first embodiment of the invention.

[0020] . [Figure 2] schematically represents a method for manufacturing a piezoelectric substrate on insulator (POI) according to a second embodiment of the invention.

[0021] The embodiments described are simply possible configurations and it should be borne in mind that the individual features as described above can be provided independently of each other, or can be omitted entirely when implementing the present invention.

[0022] . [Figure 1] schematically represents a piezoelectric substrate on insulator (POI) 100 according to the first embodiment of the invention.

[0023] The piezoelectric substrate on insulator 100 comprises a support substrate 102. In this first embodiment, the support substrate 102 is a silicon-based substrate, in particular a single-crystal silicon wafer.

[0024] A trapping structure 104 is arranged on top of the support substrate 102. The trapping structure 104 can be in direct contact with the support substrate 102. The trapping structure 104 has a thickness equal to or less than 2 pm, preferably equal to or less than 1 pm, even more preferably equal to or less than 600 nm.

[0025] According to the first embodiment, the trapping structure 104 comprises two layers: a first trapping layer 104a and a second trapping layer 104b having a different material from the material of the first trapping layer 104a.

[0026] According to one variant, the trapping structure 104 comprises only the first trapping layer 104a and the second trapping layer 104b.

[0027] The first trapping layer 104a is based on polycrystalline silicon, amorphous silicon, or porous silicon. The second trapping layer 104b is based on silicon carbide (SiC). Preferably, these layers are deposited by low-pressure chemical vapor deposition (LPCVD) or by activated chemical vapor deposition. plasma (PECVD) or high-density plasma-activated chemical vapor deposition (HDP-CVD).

[0028] In this embodiment, the two trapping layers 104a and 104b have different thicknesses. The silicon-based trapping layer 104a preferably has a thickness of 2 µm or less, in particular 1 µm or less. The silicon carbide-based trapping layer 104b preferably has a thickness of 500 nm or less, in particular 200 nm or less, and more particularly 50 nm or less. According to one example of the invention, the first trapping layer 104a has a thickness of 500 nm and the second trapping layer 104b has a thickness of 50 nm.

[0029] A dielectric layer 106 is arranged on top, in particular directly on the trapping structure 104. The dielectric layer 106 is preferably a silicon oxide-based layer. The dielectric layer 106 preferably has a thickness between 100 nm and 1 pm, in particular between 200 nm and 700 nm. The dielectric layer 106 can be formed by CVD deposition or any other suitable deposition process.

[0030] A piezoelectric layer 108 is arranged on top, in particular directly on the dielectric layer 106. This is preferably a lithium tantalate (LTO) or lithium niobate (LNO) layer. The piezoelectric layer 108 typically has a thickness between 200 nm and 1 pm.

[0031] The use of a trapping structure 104 with two trapping layers 104a, 104b of different materials makes it possible to increase the number of traps without excessively increasing the thickness of the trapping structure 104.

[0032] By adding a second trapping layer 104b of a different, and in particular thinner, material, it becomes possible to increase the number of traps while keeping the trapping structure sufficiently thin to limit the appearance of spurious modes in end devices such as sensors, filters, etc.

[0033] According to one variant, the order of the first trapping layer 104a and the second trapping layer 104b can be reversed. In this case, the second trapping layer, based on silicon carbide, is located between the support substrate 102 and the first trapping layer 104a, which is based on polycrystalline silicon, amorphous silicon, or porous silicon.

[0034] . [Figure 2] schematically represents a method for manufacturing a piezoelectric substrate on insulator (POI) according to the second embodiment of the invention to obtain a POI 100 substrate according to the first embodiment as described above in relation to Figure 1. The reference numbers already used with reference to Figure 1 in the context of the description of the POI 100 substrate are reused to describe the method of the second embodiment.

[0035] The manufacturing process of a piezoelectric substrate on insulator (POI) 100 begins with step I) of providing a support substrate 102, in particular a silicon-based substrate, in particular a single-crystal silicon wafer.

[0036] According to this second embodiment of the invention, step II) provides for the formation of the trapping structure 104 on a free surface 120 of the support substrate 102.

[0037] The formation of the trapping structure 104 begins with the formation of a first trapping layer 104a produced by low-pressure chemical vapor deposition (LPCVD). Depending on the variant, the formation of the first trapping layer 104a in step II) can be carried out by a thermal growth technique or by physical vapor deposition (PVD).

[0038] The trapping layer 104a formed on the support substrate 102 is a layer based on polycrystalline silicon, amorphous silicon or porous silicon.

[0039] The thickness of the trapping layer 104a is equal to or less than 2 pm, in particular equal to or less than 1 pm.

[0040] Next, a second 104b trapping layer is formed on top of the first 104b trapping layer. This second 104b trapping layer is silicon carbide-based. The second 104b trapping layer is formed with a thickness less than the first trapping layer, preferably with a thickness equal to or less than 500 nm, in particular a thickness less than or equal to 200 nm, and more particularly a thickness equal to or less than 50 nm.

[0041] The second trapping layer 104b is produced by low-pressure chemical vapor deposition (LPCVD), plasma-activated chemical vapor deposition (PECVD), or high-density plasma-activated chemical vapor deposition (HDP-CVD). Depending on the variant, the formation of the second trapping layer 104b in step II) can be achieved by a thermal growth technique or by physical vapor deposition (PVD). Typically, the formation of the second trapping layer 104b is carried out at a lower temperature than the first trapping layer 104a.

[0042] . Before the formation of the second trapping layer, one or more surface treatments of the first trapping layer 104a may take place, such as polishing, in particular CMP type polishing, or surface activation by plasma or ozone treatment.

[0043] . During step III) a dielectric layer 106a is formed on the free surface 122 of the second trapping layer 104b. The dielectric layer 106a is preferably a silicon oxide layer formed by chemical vapor deposition (CVD) or by physical vapor deposition (PVD).

[0044] The dielectric layer 106a preferably has a thickness equal to or less than 1 pm, in particular equal to or less than 700nm.

[0045] . A heat treatment can be carried out after the deposition of the 106a dielectric layer to densify it.

[0046] In step IV), a substrate 124 comprising a piezoelectric layer 126, in particular a substrate 124 comprising lithium tantalate (LTO) or lithium niobate (LNO), is provided. In this embodiment, the piezoelectric layer 124 is arranged on top of a base substrate 126. Alternatively, the piezoelectric layer 126 is a massive layer and forms the entire substrate 124.

[0047] In step V) a second dielectric layer 106b, in particular a silicon oxide layer, is made on the free surface 130 of the piezoelectric layer 126. This layer is made in the same way as the dielectric layer 106a formed in step III). The thickness is chosen such that the sum of the thicknesses of the two dielectric layers 106a and 106b is between 10 µm and 1 µm, in particular between 200 nm and 700 nm.

[0048] According to one variant, one or more surface treatment steps of the free surface 130 of the substrate 124 comprising a piezoelectric layer can be carried out before the formation of the dielectric layer 106b. For example, a surface activation treatment, such as a plasma treatment and / or an ozone-based treatment, can be carried out.

[0049] . During step VI), the substrate 124 obtained after step V) is assembled with the support substrate 102 obtained in step III) to form a support substrate-substrate assembly 132 comprising a piezoelectric layer.

[0050] The assembly is carried out so that the dielectric layers 106a and 106b are in direct contact. The assembly is preferably carried out by molecular adhesion.

[0051] . Once the two substrates are assembled, a thinning step VII) of the assembly 132 is carried out to obtain the POI substrate 100 with a thinner piezoelectric layer 108, as illustrated in Figure 1.

[0052] . For example, the thinning step can be carried out by grinding, or by a step of forming a weakening zone in the piezoelectric layer 126 before the assembly step VI), so as to delimit the piezoelectric layer 108 to be transferred onto the support substrate 102, followed by fracturing. This step of forming a weakening zone is carried out by implanting atomic or ionic species in the piezoelectric layer 126. The atomic or ionic implantation can be carried out in such a way that the weakening zone is located inside the piezoelectric layer 126 and delimits a piezoelectric layer 108 to be transferred from the rest of the piezoelectric layer 126. Then, a fracturing step of the assembly 132 by supplying thermal and / or mechanical energy to the weakening zone of the piezoelectric layer 126 is then carried out, in order to obtain the piezoelectric substrate on insulation (POI) 100.

[0053] . According to variants, the bonding between the support substrate 102 and the substrate 124 can also be done between the trapping structure 104 and the dielectric layer 106b, i.e. without carrying out step III), or between the dielectric layer 106a and the piezoelectric layer 126.

[0054] Before applying one or more of the layers mentioned above, one or more cleaning, brushing or polishing steps of the surface directly below may be carried out to remove the presence of particles and dust.

Claims

Demands

1. . Piezoelectric substrate on insulation (POI) comprising: - a support substrate (102), in particular a silicon-based substrate, - a piezoelectric layer (108), in particular a layer of lithium tantalate (LTO) or lithium niobate (LNO), - a dielectric layer (106), in particular a silicon oxide layer, sandwiched between the piezoelectric layer (108) and the supporting substrate (102), - a trapping structure (104) sandwiched between the dielectric layer (106) and the support substrate (102) comprising a first trapping layer (104a) based on polycrystalline or amorphous or porous silicon, preferably based on polycrystalline silicon, and, the trapping structure (104) comprises a second trapping layer (104b) based on silicon carbide characterized in that the first trapping layer (104a) is positioned between the support substrate (102) and the second trapping layer (104b).

2. , Piezoelectric substrate on insulator (POI) according to claim 1, wherein the second trapping layer (104b) is thinner than the first trapping layer (104a).

3. . Piezoelectric substrate on insulator (POI) according to claim 1 or 2, wherein the second trapping layer (104b) has a thickness less than or equal to 500nm, in particular a thickness less than or equal to 200nm, in particular a thickness less than or equal to 50nm.

4. . Piezoelectric substrate on insulator (POI) according to any one of claims 1 to 3, wherein the first trapping layer has a thickness less than or equal to 2pm, in particular a thickness less than or equal to 1pm.

5. . Piezoelectric substrate on insulator (POI) according to any one of claims 1 to 4, wherein the second trapping layer (104b) is directly formed on the first trapping layer (104a).

6. . Piezoelectric substrate on insulator (POI) according to any one of claims 1 to 5, wherein the trapping structure (104) comprises only the first trapping layer (104a) and the second trapping layer (104b).

7. . A method for manufacturing a piezoelectric substrate on an insulator (POI) according to any one of claims 1 to 5, comprising the steps of: - provide a supporting substrate, in particular a silicon-based substrate, - provide a substrate comprising a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO), - to form a trapping structure on top of the supporting substrate, - to form a dielectric layer, in particular a silicon oxide layer, over the piezoelectric substrate and / or on top of the trapping structure, - assemble the substrate comprising a piezoelectric layer with the support substrate such that the dielectric layer and the trapping structure are sandwiched between the piezoelectric layer and the support substrate the formation of the trapping structure includes the formation of a first layer based on polycrystalline or amorphous or porous silicon on the support substrate, preferably based on polycrystalline silicon, and, then the formation of a second trapping layer based on silicon carbide.

8. . A method for manufacturing a piezoelectric substrate according to claim 6, further comprising a step of: - to form a zone of weakening within the piezoelectric layer, and - to create a fracture along the area of ​​weakening to separate part of the piezoelectric layer from the rest of the substrate including the piezoelectric layer after the assembly step to transfer part of the piezoelectric layer onto the supporting substrate.

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