Piezoelectric-on-insulator (POI) substrate and method for producing a piezoelectric-on-insulator (POI) substrate

Abstract

The invention discloses a piezoelectric-on-insulator (POI) substrate comprising: a carrier substrate (102), in particular a substrate based on silicon; a piezoelectric layer (108), in particular a layer of lithium tantalate (LTO) or of lithium niobate (LNO); a dielectric layer (106), in particular a layer of silicon oxide, sandwiched between the piezoelectric layer (108) and the substrate (102); a trapping structure (104) sandwiched between the dielectric layer (106) and the carrier substrate (102). The POI substrate is characterised in that the trapping structure (104) comprises at least two trapping layers (104a, 104c), which layers are separated each time by a dielectric intermediate layer (104b). The invention also discloses a method for producing a piezoelectric-on-insulator (POI) substrate.

Description

Description Title of the invention: Piezoelectric substrate on insulator (POI) and method for manufacturing a piezoelectric substrate on insulator (POI)

[0001] The invention relates to a piezoelectric substrate on insulator (POI) comprising in this order a support substrate, a trapping structure, a dielectric layer and a piezoelectric layer, as well as a method for manufacturing such a POI substrate.

[0002] Such substrates are known in the state of the art. Devices such as sensors or filters are made in and / or on the piezoelectric layer.

[0003] The trapping structure reduces losses due to parasitic effects at the interface between the substrate and the dielectric layer. This trapping layer, inserted between the substrate and the dielectric layer, decreases the free carrier density and prevents variations in the Fermi level. This results in a higher and more consistent resistivity in the substrate, which reduces parasitic effects such as signal attenuation, harmonic generation, and conductive coupling.

[0004] However, it has been observed that during heat treatments, either during or after the fabrication of POI substrates, metallic elements from the piezoelectric layer, such as lithium, can diffuse through the dielectric layer and the trapping structure to the interface with the substrate. The accumulation of these metallic elements reduces the performance of the trapping structure, and the suppression of parasitic effects is thus negatively affected.

[0005] The object of the invention is therefore to reduce the harmful effect of the diffusion of metallic elements through the structure of the POI substrate.

[0006] The object of the invention is realized by a piezoelectric substrate on insulator (POI) comprising: a support substrate, in particular a silicon-based substrate, a piezoelectric layer, in particular a lithium tantalate (LTO) or lithium niobate (LNO) layer, a dielectric layer, in particular a silicon oxide layer, sandwiched between the piezoelectric layer and the support substrate, a trapping structure sandwiched between the dielectric layer and the support substrate, characterized in that the trapping structure comprises at least two trapping layers, the trapping layers being separated from each other by an intermediate dielectric layer.Separating the trapping structure into at least two trapping layers with a dielectric layer between them allows for the segregation of some of the contamination by metallic elements at the interfaces between the trapping layers. This intermediate layer reduces the level of metallic element accumulation at the interface between the trapping structure and the supporting substrate. Thus, the parasitic effect can be effectively reduced. The supporting substrate should preferably have a resistivity greater than or equal to 500 Ω·cm.

[0007] According to one embodiment, the trapping layers of the POI substrate can be based on polycrystalline, amorphous, or porous silicon, or on silicon carbide (SiC). Such layers effectively reduce parasitic effects.

[0008] In one embodiment, the dielectric intermediate layer of the POI substrate can be a silicon oxide layer, in particular a native silicon oxide layer, a layer deposited by chemical vapor deposition (CVD), or a layer obtained by thermal oxidation. Silicon oxides are easy to produce, and at the same time, an accumulation of diffuse metallic elements can be observed at the interfaces of the intermediate layers of the trapping structure.

[0009] According to one embodiment, the intermediate dielectric layer(s) of the POI substrate may have a thickness equal to or less than 5 nm, in particular equal to or less than 1 nm. Even layers of such small thicknesses show an effect on reducing parasitic effects.

[0010] According to one embodiment, at least two of the trapping layers may have one or more physical properties, in particular a different grain size. This makes it possible to further improve the suppression of parasitic effects.

[0011] In one embodiment, each trapping layer of the POI substrate can have the same thickness. In an alternative, at least one trapping layer of the POI substrate can have a different thickness than the other trapping layer(s). This allows for optimization of the properties of the POI substrate.

[0012] According to one embodiment, the POI substrate trapping structure can have a thickness equal to or less than 5 µm, preferably equal to or less than 2 µm. Thus, even with trapping structures thinner than those used in the prior art, a satisfactory reduction of the parasitic effect can be achieved.

[0013] The object of the invention is also realized by the process of manufacturing a piezoelectric substrate on an insulator (POI) as described above and comprising the steps of: providing a support substrate, in particular a silicon-based substrate, providing a substrate comprising a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO), forming a trapping structure on top of the support substrate, forming a dielectric layer, in particular a silicon oxide layer, on top of the substrate comprising a piezoelectric layer and / or on top of the trapping structure, assembling the substrate comprising a piezoelectric layer with the support substrate such that the dielectric layer and the trapping structure are sandwiched between the piezoelectric layer and the support substrate, characterized in that the step of forming the trapping structure comprises forming a first trapping layer,form an intermediate dielectric layer on the first trapping layer and form a second trapping layer on the intermediate dielectric layer. With this process, a substrate can be obtained that effectively reduces the negative effect of the diffusion of metallic elements towards the supporting substrate.

[0014] According to one embodiment, the manufacturing process for a piezoelectric substrate may further include a step of: forming a weakened zone within the piezoelectric layer, and creating a fracture along the weakened zone to separate a portion of the piezoelectric layer from the remainder of the substrate, including the piezoelectric layer after the assembly step, in order to transfer the portion of the piezoelectric layer onto the support substrate. This process allows for the industrial production of the POI substrates according to the invention.

[0015] The invention and its advantages will be explained in more detail hereafter by means of advantageous embodiments, given by way of example and with reference to the following figures, in which the reference numbers identify features of the invention.

[0016] [Figure 1] schematically represents a piezoelectric substrate on insulator (POI) according to a first embodiment of the invention.

[0017] [Figure 2] schematically represents a piezoelectric substrate on insulator (POI) according to a second embodiment of the invention.

[0018] [Figure 3] schematically represents a piezoelectric substrate on insulator (POI) according to a third embodiment of the invention.

[0019] [Figure 4] schematically represents a method for manufacturing a piezoelectric substrate on insulator (POI) according to a fourth embodiment of the invention.

[0020] The embodiments described are only possible configurations and it is recalled that the individual characteristics as described above can be provided independently of each other or can be omitted altogether when implementing the present invention.

[0021] [Figure 1] schematically represents a piezoelectric substrate on insulator (POI) 100 according to the first embodiment of the invention.

[0022] The piezoelectric substrate on insulator 100 comprises a support substrate 102. In this first embodiment, the support substrate 102 is a silicon-based substrate, in particular a single-crystal silicon wafer. The support substrate preferably has a resistivity greater than or equal to 500 Ω·cm.

[0023] A trapping structure 104 is arranged above the support substrate 102. The trapping structure 104 may be in direct contact with the support substrate 102. The trapping structure 104 has a thickness equal to or less than 5 µm, preferably equal to or less than 2 µm.

[0024] According to the first embodiment, the trapping structure 104 comprises three layers: a first trapping layer 104a, an intermediate dielectric layer 104b and a second trapping layer 104c.

[0025] The trapping layers 104a and 104c are based on polycrystalline, amorphous, or porous silicon, or on silicon carbide (SiC). Preferably, they are layers deposited by low-pressure chemical vapor deposition (LPCVD). In this embodiment, the two trapping layers 104a and 104c have the same thickness.

[0026] The dielectric intermediate layer 104b can be a silicon oxide layer, preferably a native silicon oxide layer. In some variations, the dielectric intermediate layer can also be formed by chemical vapor deposition (CVD) or by thermal oxidation. The dielectric intermediate layer 104b preferably has a thinner profile than the trapping layers 104a and 104b, in particular a profile equal to or less than 5 nm, and in particular equal to or less than 1 nm.

[0027] A dielectric layer 106 is arranged above, in particular directly on, the trapping structure 104. The dielectric layer 106 is preferably a silicon oxide-based layer. The dielectric layer 106 preferably has a thickness between 100 nm and 1 pm, in particular between 200 nm and 700 nm. The dielectric layer 106 can be formed by CVD deposition or any other suitable deposition process.

[0028] A piezoelectric layer 108 is arranged above, specifically directly on the dielectric layer 106. This is preferably a lithium tantalate (LTO) or lithium niobate (LNO) layer. The piezoelectric layer 108 typically has a thickness between 200 nm and 1 pm.

[0029] According to one variant, the two trapping layers 104a and 104c may have one or more different physical properties, such as grain size.

[0030] Separating the trapping structure 104 into at least two trapping layers 104a, 104c with an intermediate dielectric layer 104b between the two trapping layers 104a, 104c allows for the segregation of some of the contamination by metallic elements at the interfaces between the trapping layers 104a, 104c and the intermediate layer 104b, thus reducing the concentration of metallic elements at the interface between the trapping structure 104 and the support substrate 102. Thus, the reduction in suppression of parasitic effects is mitigated.

[0031] [Figure 2] schematically represents a piezoelectric substrate on insulator (POI) 200 according to a second embodiment of the invention.

[0032] The piezoelectric substrate on insulator 200 comprises the support substrate 102, the dielectric layer 106, and the piezoelectric layer 108 of the first embodiment. A new description of these layers and their properties is omitted, and reference is made to their description above in relation to the first embodiment.

[0033] The only difference between the first and second embodiments lies in the use of a different trapping structure 204.

[0034] In the second embodiment, the trapping structure 204 comprises a total of five trapping layers 204a, 204c, 204e, 204g and 204i. An intermediate dielectric layer 204b, 204d, 204f and 204h is intercalated between two trapping layers each time.

[0035] The trapping layers 204a, 204c, 204e, 204g and 204i are made in the same way as the trapping layers 104a and 104c of the first embodiment and they have the same physical properties that the latter. In particular, they all have the same thicknesses, specifically all a thickness of 0.2pm or less.

[0036] Similarly, the intermediate dielectric layers 204b, 204d, 204f and 204h are made in the same way as the intermediate dielectric layer 104b of the first embodiment and have the same physical properties. In particular, they all have the same thicknesses, specifically a thickness of a few tenths of a nanometer (a few Angstroms), in particular one or less nanometer (10 or less Angstroms).

[0037] By increasing the number of interfaces in the trapping structure 204, the concentration of metallic elements, particularly lithium, at the interface between the first trapping layer 204a and the support substrate 102 can be further reduced, as metallic elements are trapped at each interface. Thus, the amount of metallic elements reaching the interface with the support substrate 102 is lower than in a structure with fewer interfaces.

[0038] Depending on the variants, more or fewer trapping layers and intermediate dielectric layers may be provided in the trapping structure, depending on the level of concentration of metallic elements considered acceptable for a given application.

[0039] [Figure 3] schematically represents a piezoelectric substrate on insulator (POI) 300 according to a third embodiment of the invention.

[0040] The piezoelectric substrate on insulator 300 comprises the support substrate 102, the dielectric layer 106, and the piezoelectric layer 108 of the first embodiment. These layers and their properties will not be described again, but reference is made to their description in the first embodiment.

[0041] The only difference between the first and third embodiments lies in the use of a different trapping structure 304.

[0042] In this embodiment, the trapping structure 304 comprises several trapping layers 304a, 304c, 304e, 304g, 304i and 304k, which, as in the second embodiment, are separated by intermediate dielectric layers 304b, 304d, 304f, 304h, 304j.

[0043] The intermediate dielectric layers 304b, 304d, 304f, 304h, 304j are made as in the first or second embodiment and have the same thicknesses, for example a few tenths of a nanometer (a few Angstroms), in particular one or less nanometer (10 Angstroms or less).

[0044] However, while the various thin trapping layers 304c, 304e, 304g, 304i, and 304k all have the same thickness, for example, 0.1 µm or less, the trapping layer 304a is thicker, specifically 0.5 µm or more.

[0045] By increasing the number of interfaces in the trapping structure 304, the concentration of metallic elements, particularly lithium, at the interface between the first trapping layer 304a and the supporting substrate 102 can be reduced, as in the second embodiment. The layer 304a at interface with the support substrate 102 is thicker and thus retains its trapping properties.

[0046] Depending on the variants, more or fewer trapping layers and intermediate dielectric layers can be provided in the trapping structure depending on the level of accumulation of metallic elements considered acceptable for a given application.

[0047] [Figure 4] schematically represents a process for manufacturing a piezoelectric substrate on insulator (POI) according to the fourth embodiment of the invention to obtain a POI 100 substrate according to the first embodiment as described above in relation to Figure 1. The reference numbers already used in the description of the POI 100 substrate of Figure 1 are reused for the description of the process.

[0048] The manufacturing process of a piezoelectric substrate on insulator (POI) 100 begins with step I) of providing a support substrate 102, in particular a silicon-based substrate, in particular a single-crystal silicon wafer.

[0049] According to this fourth embodiment of the invention, step II) provides for the formation of the trapping structure 104 on a free surface 120 of the support substrate 102.

[0050] The formation of the trapping structure 104 begins with the formation of a first trapping layer 104a produced by low-pressure chemical vapor deposition (LPCVD). Depending on the variant, the formation can be carried out by a thermal growth technique or by physical vapor deposition (PVD).

[0051] The trapping layer 104a formed on the support substrate 102 is a polycrystalline silicon-based layer, amorphous or porous, or a silicon carbide-based layer. The thickness of the trapping layer 104a is equal to or less than 2.5 µm, in particular equal to or less than 1 µm.

[0052] Next, an intermediate dielectric layer 104b is formed on the first trapping layer 104a. The intermediate dielectric layer 104b can be a silicon oxide layer, preferably a native silicon oxide layer. According to one variant, the intermediate dielectric layer is formed by chemical vapor deposition (CVD) or by thermal oxidation. The intermediate dielectric layer 104b preferably has a thinner thickness than the first trapping layer 104a, in particular a thickness that is less than 5 nm, and especially less than 1 nm.

[0053] To complete the formation of the trapping structure 104, a second trapping layer 104c is formed on the intermediate dielectric layer 104b in the same way as the first trapping layer 104a and in particular with the same thickness.

[0054] According to one variant, the two trapping layers 104a and 104c can be formed with one or more different physical properties, such as grain size. According to another variant, the two trapping layers 104a and 104c can be based on different materials from those mentioned above. For example, layer 104a could be made of porous silicon and layer 104c of polycrystalline silicon.

[0055] In step III), a dielectric layer 106a is formed on the free surface 122 of the second trapping layer 104c. The dielectric layer 106a is preferably a silicon oxide layer formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). According to one variant, the layer 106a is formed by oxidation of polycrystalline silicon.

[0056] The dielectric layer 106a preferably has a thickness equal to or less than 1 pm, in particular equal to or less than 700nm.

[0057] Heat treatment can be carried out after the deposition of the 106a dielectric layer to densify it.

[0058] In step IV), a substrate 124 comprising a piezoelectric layer 126, in particular a substrate 124 comprising lithium tantalate (LTO) or lithium niobate (LNO), is provided. In this embodiment, the piezoelectric layer 124 is arranged above a base substrate 126. Alternatively, the piezoelectric layer 126 is a bulk layer and forms the entire substrate 124.

[0059] In step V) a second dielectric layer 106b, in particular a silicon oxide layer, is made on the free surface 130 of the piezoelectric layer 126. This layer is made in the same way as the dielectric layer 106a formed in step III). The thickness is chosen such that the sum of the thicknesses of the two dielectric layers 106a and 106b is between 100 nm and 1 pm, in particular between 200 nm and 700 nm.

[0060] According to one variant, one or more surface treatment steps of the free surface 130 of the substrate 124 comprising a piezoelectric layer can be carried out before the formation of the dielectric layer 106b. For example, a surface activation treatment, such as a plasma treatment and / or an ozone-based treatment, can be carried out.

[0061] During step VI), the substrate 124 obtained after step V) is assembled with the support substrate 102 obtained in step III) of assembly to form a support substrate - substrate assembly 132 comprising a piezoelectric layer.

[0062] The assembly is carried out so that the dielectric layers 106a and 106b are in direct contact. The assembly is preferably carried out by molecular adhesion.

[0063] Once the two substrates are assembled, a thinning step VII) of the assembly 132 is carried out to obtain the POI substrate 100 with a thinner piezoelectric layer 108, as illustrated in Figure 1.

[0064] For example, the thinning step can be carried out by grinding or by a step of forming a weakened zone in the piezoelectric layer 126 before the assembly step VI, so as to delimit the piezoelectric layer 108 to be transferred onto the support substrate 102 and fractured. This weakened zone formation step is carried out by implanting atomic or ionic species into the piezoelectric layer 126. The atomic or ionic implantation can be carried out in such a way that the weakened zone is located inside the piezoelectric layer 126 and delimits a piezoelectric layer 108 to be transferred from the rest of the piezoelectric layer 126. Then, a fracturing step of the assembly 132 by supplying thermal and / or mechanical energy at the level of the weakening zone of the piezoelectric layer 126 is then carried out to obtain the piezoelectric substrate on insulator (POI) 100.

[0065] According to variants, the bonding between the support substrate 102 and the substrate 124 can also be done between the trapping structure 104 and the dielectric layer 106b, i.e. without carrying out step III), or between the dielectric layer 106a and the piezoelectric layer 126.

[0066] Before applying one or more of the layers mentioned above, one or more steps of cleaning, brushing or polishing the surface directly below may be carried out to remove the presence of particles and dust.

[0067] The process can also be applied to obtain the POI 200 and 300 substrates of the second and third embodiment of the invention described in relation to Figure 2 and Figure 3 respectively.

Claims

Demands

1. . Piezoelectric substrate on insulation (POI) comprising: - a support substrate (102), in particular a silicon-based substrate - a piezoelectric layer (108), in particular a layer of lithium tantalate (LTO) or lithium niobate (LNO), - a dielectric layer (106), in particular a silicon oxide layer, sandwiched between the piezoelectric layer (108) and the supporting substrate (102), - a trapping structure (104) sandwiched between the dielectric layer (106) and the supporting substrate (102) characterized in that the trapping structure (104) comprises at least two trapping layers (104a, 104c), the trapping layers (104a, 104c) being separated from each other by an intermediate dielectric layer (104b), and at least two of the at least two trapping layers (104a, 104c) have different physical properties, in particular grain size.

2. . Piezoelectric substrate on insulator (POI) according to claim 1, wherein the trapping layers (104a, 104c) are based on polycrystalline silicon and / or amorphous silicon and / or porous silicon and / or silicon carbide (SiC).

3. . Piezoelectric substrate on insulator (POI) according to claim 1 or 2, wherein the intermediate dielectric layer (104b) is a silicon oxide layer, in particular a native silicon oxide layer or a layer deposited by chemical vapor deposition (CVD) or a layer obtained by thermal oxidation.

4. . Piezoelectric substrate on insulator (POI) according to any one of claims 1 to 3, wherein the intermediate dielectric layer(s) (104b) have a thickness equal to or less than 5nm, in particular equal to or less than 1 nm.

5. . Piezoelectric substrate on insulator (POI) according to any one of claims 1 to 4, wherein each trapping layer (104a, 104c) has the same thickness.

6. . Piezoelectric substrate on insulator (POI) according to any one of claims 1 to 5, wherein at least one trapping layer (304a) has a different thickness from the other trapping layer(s) (304c, 304e), in particular the trapping layer (304a) directly provided on the supporting substrate is thicker than the other trapping layer(s).

7. . Piezoelectric substrate on insulator (POI) according to at least one of claims 1 to 6, wherein the trapping structure (104) has a thickness equal to or less than 5pm, preferably equal to or less than 2pm.

8. . A method for manufacturing a piezoelectric substrate on an insulator (POI) according to any one of claims 1 to 7 comprising the steps of: - provide a supporting substrate, in particular a silicon-based substrate, - provide a substrate comprising a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO), - to form a trapping structure above the supporting substrate, - form a dielectric layer, in particular a silicon oxide layer, over the substrate comprising a piezoelectric layer and / or over the trapping structure; assemble the substrate comprising a piezoelectric layer with the support substrate such that the dielectric layer and the trapping structure are sandwiched between the piezoelectric layer and the support substrate, characterized in that the step of forming the trapping structure comprises forming a first trapping layer, forming an intermediate dielectric layer on the first trapping layer and forming a second trapping layer on the intermediate dielectric layer, the two trapping layers having different physical properties, in particular grain size.

9. . A method for manufacturing a piezoelectric substrate according to claim 8, further comprising a step of: - to form a zone of weakening within the piezoelectric layer, and - to create a fracture along the area of ​​weakening to separate part of the piezoelectric layer from the rest of the substrate including the piezoelectric layer after the assembly step to transfer part of the piezoelectric layer onto the supporting substrate.

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