SEMICONDUCTOR WAFER HAVING GaN INTERMEDIATE LAYERS FOR FORMING SEMICONDUCTOR COMPONENTS

Abstract

The invention relates to a semiconductor wafer for forming GaN semiconductor components having a diameter of at least 100 mm, comprising a substrate having an upper face and a lower face, wherein: the substrate consists on the upper face of silicon; a transition layer is integrally bonded to the upper face of the substrate; a first GaN layer which is integrally formed on the transition layer is provided; the first GaN layer comprises a first GaN partial layer and a second GaN partial layer; the second GaN partial layer is formed on the first GaN partial layer; the second GaN partial layer comprises, on average, a lower number of threading dislocations than the first GaN partial layer; and the first GaN partial layer has a first layer thickness and the second GaN partial layer has a second layer thickness, the second layer thickness being greater than or equal to the first layer thickness.

Description

[0001] Semiconductor wafer with GAN interlayers for the formation of GAN semiconductor components

[0002] The invention relates to a semiconductor wafer for forming GaN semiconductor components.

[0003] Such semiconductor wafers primarily comprise a silicon substrate with an overlying buffer layer system, with the topmost layer of the buffer layer system comprising a GaN layer. GaN semiconductor components, particularly power transistors or LEDs, are fabricated on the GaN layer by growing and structuring additional layers.

[0004] The goal here is to achieve the epitaxial growth of the GaN layer or GaN sublayers, in particular, as dislocation-free and single-crystal as possible. In other words, to reduce the number of defects, e.g., the number of thread-like dislocations, as much as possible and to deposit a defect-free single-crystal GaN layer in order to achieve the highest possible yield in the production of semiconductor components containing or consisting of GaN.

[0005] The production of the layers of the buffer layer system, including the GaN layer, is typically carried out using vapor-phase epitaxy (MOVPE) processes. In this process, the respective semiconductor layers are created by deposition from the vapor phase.

[0006] To produce the GaN layer from the gas phase, organic carrier gases such as trimethylgallium ((CH3)3Ga) and ammonia (NH3) are used with the addition of hydrogen as a carrier gas during the growth of gallium nitride, whereby the reaction proceeds by means of the reaction formula Due to the presence of large amounts of carbon and hydrogen, small amounts of hydrogen and carbon are also unintentionally and inevitably incorporated into the semiconductor crystal, ie into the GaN

[0007] CONFIRMATION COPY layer installed.

[0008] While hydrogen can be removed by annealing in an inert gas atmosphere or in vacuum, for example to avoid passivating the acceptors necessary for p-type conduction, the unavoidable and unintentional incorporation of carbon caused by the process leads to p-doping or an increase in the residual conductivity.

[0009] Despite complex procedures to avoid all impurities resulting from the use of devices and raw materials such as organometallics required to produce the GaN layer, unintentional and unavoidable impurities such as oxygen are found in the GaN layer.

[0010] Methods for producing GaN layers are known from DE 10 2006 008 929 Al, EP 2 767 620 Al, DE 102 56 911 Al, US 2006 / 0281284 Al and US 2013 / 0087762 Al.

[0011] Against this background, the object of the invention is to provide a device that further develops the state of the art.

[0012] The object is achieved by a semiconductor wafer for forming GaN semiconductor components having the features of patent claim 1. Advantageous embodiments of the invention are the subject of subclaims.

[0013] According to the subject matter of the invention, a semiconductor wafer for forming GaN semiconductor components is provided, wherein the semiconductor wafer has a diameter of at least 100 mm. It is understood that the semiconductor wafer may also have a diameter of 150 mm, 200 mm, 300 mm, or 450 mm.

[0014] Furthermore, the semiconductor wafer comprises a substrate with a top side and a bottom side, with the top side of the substrate being made of silicon. Furthermore, a transition layer is bonded to the top side of the substrate. A first GaN layer is bonded to the transition layer.

[0015] The first GaN layer comprises a first GaN sublayer and a second GaN sublayer, wherein the second GaN sublayer is formed on the first GaN sublayer.

[0016] The second GaN sublayer has, on average, a smaller number of thread-like dislocations than the first GaN sublayer.

[0017] Furthermore, the first GaN sublayer has a first layer thickness and the second GaN sublayer has a second layer thickness, wherein the second layer thickness is greater than or equal to the first layer thickness.

[0018] It is understood that the semiconductor wafer comprises a substrate, wherein the substrate comprises or consists of a single layer or, in another embodiment, the substrate comprises or consists of a plurality of layers arranged in a stack.

[0019] It should be noted that a monocrystalline silicon layer is formed on the upper side of the substrate. In one embodiment, only the upper side consists of a monocrystalline layer. In a further development, the thickness of the uppermost monocrystalline layer ranges from 10 nm to 100 pm. Preferably, the entire surface comprises or consists of a monocrystalline layer.

[0020] In one embodiment, the entire substrate consists of silicon, i.e. a single single-crystalline silicon layer.

[0021] Preferably, the crystal orientation of the single-crystalline layer is either <100> or <111> . It is understood, however, that the single-crystalline layer may also have other crystal directions, in particular a <110> or <011> or <001> Direction. It should be noted that the term "on average" refers to the total number of filamentary dislocations relative to the entire area of ​​the first or the entire area of ​​the second GaN sublayer. With the above definition, the area density of filamentary dislocations of the second GaN sublayer determined in this way is lower than the area density of filamentary dislocations of the first GaN sublayer.

[0022] In other words, if the number of filamentary dislocations on small selected areas of the second GaN sublayer is compared with small selected areas of the first GaN sublayer, it is possible that the number of filamentary dislocations on the second GaN sublayer is equal to or even larger than the number of filamentary dislocations on the first GaN sublayer.

[0023] It should also be noted that the term GaN layer or GaN sublayer refers to a layer that contains at least the elements Ga and N. Furthermore, it should be noted that all layers always contain unintentional and unavoidable impurities and intentionally introduced dopants.

[0024] In a further development, the GaN layer or GaN sub-layer comprises, in addition to the elements Ga and N, other elements such as In and / or Al and / or other elements of the III or V main group.

[0025] In another further development, the proportion of the other elements of the III main group and / or the number of elements relative to the V main group is less than 10%, preferably less than 5%, most preferably less than 1%.

[0026] In another embodiment, the GaN layer or the respective GaN sublayer consists exclusively of the elements Ga and N, although unintentional and unavoidable impurities and intentionally introduced dopants are still included. It should be noted that the aforementioned layers, including at least the transition layer and the first GaN layer, are part of a semiconductor buffer layer sequence. As already mentioned at the beginning, the purpose of the semiconductor buffer layer sequence is to provide a GaN layer that is as defect-free as possible in order to be able to manufacture GaN semiconductor components.

[0027] An advantage of constructing a GaN layer from several, ie at least two, GaN sublayers is that the quality of the uppermost GaN sublayer is improved compared to a GaN layer comprising or consisting of a single GaN sublayer.

[0028] One reason for the improvement in the layer quality of the GaN layer is, among other things, a reduction in the number of thread-like dislocations.

[0029] Another advantage is that the surface area of ​​the majority of the crystallites in the second GaN sublayer is larger than in the first GaN sublayer. This, in particular, reduces the number of thread-like dislocations. The observed surface of the crystallites is always parallel to the respective layer surface and is also referred to below as the lateral surface.

[0030] In other words, the average crystallite size in the second GaN sublayer is increased compared to the average crystallite size in the first GaN sublayer. The "average crystallite size" here refers to the arithmetic mean, i.e., the total lateral area divided by the number of crystallites.

[0031] Studies have shown that the differences between the two GaN sublayers can be created by changing the growth conditions. Between the two GaN sublayers, i.e., at the point where an interface forms between the two GaN sublayers, at least one deposition parameter is changed on the MOVPE system. It is understood that the change in the changed deposition parameter is greater than the inaccuracy of the respective deposition parameter caused by the system conditions.

[0032] In a further development, the magnitude of the parameter change or the lower limit for the parameter change is at least 2 times, at least 10 times, or at least 50 times the inaccuracy specified for the parameter by the control system on the MOVPE. It is understood that if multiple separation parameters are changed, the above statements apply to each of the changed separation parameters.

[0033] In a further development, the first GaN sublayer and the second GaN sublayer have the same stoichiometry.

[0034] In another embodiment, the difference in stoichiometry between the two GaN sublayers with respect to the elements of the III main group is less than 2% and the difference in stoichiometry with respect to the elements of the V main group is less than 2%.

[0035] In one embodiment, the difference in the curvature of the semiconductor wafer when depositing the first GaN sublayer and the second GaN sublayer is less than 5 km 1 In other words, both layers, the first GaN sublayer and the second GaN sublayer, exert the same or approximately the same stress on the substrate.

[0036] In a further development, the first GaN sublayer is almost or completely stress-free during deposition and / or immediately after deposition, i.e. neither compressively nor tensilely strained.

[0037] In a further development, the second GaN sublayer is almost or completely stress-free during deposition and / or immediately after deposition, i.e. neither compressively nor tensilely strained.

[0038] In one refinement, the magnitude of the wafer curvature is, to a first approximation, independent of the diameter of the semiconductor wafer. In one embodiment, the first GaN sublayer has a first lattice constant and the second GaN sublayer has a second lattice constant. Preferably, the first lattice constant is equal to the second lattice constant. In another refinement, the difference between the two lattice constants is less than 1%, less than 0.5%, or less than 0.3%.

[0039] In another embodiment, the second GaN sublayer is formed integrally on the first GaN sublayer.

[0040] In one embodiment, a bonding layer is formed between the first GaN sublayer and the second GaN sublayer. Preferably, the lattice constant of the bonding layer is equal to the lattice constant of the first GaN sublayer and / or equal to the lattice constant of the second GaN sublayer, or, in another alternative, the lattice constant of the bonding layer is different from the lattice constant of the first GaN sublayer and / or the lattice constant of the second GaN sublayer.

[0041] In one embodiment, the thickness of the connecting layer is in a range between 0.5 nm and 100 nm, preferably between 0.5 nm and 30 nm.

[0042] In another embodiment, the difference in the lattice constant between the connection layer and the first and / or the second GaN sublayer is each or in total less than 1% or less than 0.5% or less than 0.3%.

[0043] In one embodiment, the ratio of the sum of the thread-like dislocations of the second GaN sublayer to the sum of the thread-like dislocations of the first GaN sublayer is between 2 and 1000 or between 5 and 40. The sum is determined from the total number of thread-like dislocations of the entire layer. Preferably, the sum of the thread-like dislocations is determined at the surface of the respective GaN sublayer. In another embodiment, the difference in the sum of the thread-like dislocations at the interface between the second GaN sublayer and the first GaN sublayer is between 2 and 1000 or between 5 and 40. The interface comprises the underside of the second GaN sublayer and the top side of the first GaN sublayer.

[0044] In a further development, the surface density of the thread-like dislocations in the first GaN sublayer is in a range between 2*10 9 cm'2 and l*10 10 cm' 2 and the surface density of the thread-like dislocations in the second GaN sublayer in a range between l*10 7 cm' 2 and l*10 9 cm' 2 .

[0045] In a further development, the surface density of the thread-like dislocations at the bottom in the first GaN sublayer is greater than 5*1O 10 cm' 2 . Furthermore, the surface density of the thread-like dislocations on the top side of the first GaN sublayer is in a range between 2*10 9 cm' 2 and l*10 10 cm' 2 and the surface density of the thread-like dislocations at the top of the second GaN sublayer in a range between l*10 7 cm' 2 and l*10 9 cm' 2 .

[0046] In another embodiment, the first GaN sublayer, in contrast to the second GaN sublayer, has a larger total number of thread-like dislocations with an oblique orientation. It should be noted that the term "oblique orientation" refers to the orientation of the thread-like dislocations within the respective GaN sublayer deviating from a perpendicular direction, i.e., deviating from the direction of the normal on the upper side of the respective GaN sublayer.

[0047] It is understood that the course of the thread-like dislocations within the respective GaN sublayer has both vertical or, to a first approximation, vertical sections, and that the course only assumes an oblique course with increasing length of the thread-like dislocation. It is desirable that the oblique course of the thread-like dislocations runs as horizontally as possible, i.e., parallel to the top side of the respective GaN sublayer.

[0048] In one embodiment, at least 50% or at least 80% of the thread-like dislocations in the first GaN sublayer have an oblique course. In a further development, the dislocation angle is greater than 10°, 30°, or 50°.

[0049] In a further development, the step angle of the obliquely running thread-like dislocations in the first GaN sublayer is greater than 50° or greater than 30°.

[0050] In another embodiment, the ratio of the thickness of the second GaN sublayer to the thickness of the first GaN sublayer is in a range between 1 and 100, or in a range between 1 and 10, or in a range between 1 and 3.

[0051] In another embodiment, the thickness of the first GaN sublayer is in a range between 50 nm and 300 nm and / or the thickness of the second GaN sublayer is in a range between 300 nm and 5000 nm.

[0052] In another embodiment, the first GaN layer has a total layer thickness of at least 0.35 pm and a maximum thickness of 5 pm.

[0053] As mentioned at the beginning, during vapor deposition to produce the GaN layer, carbon and oxygen are inevitably incorporated during the growth of the GaN layer due to the equipment and precursors required for the production of the GaN layer using MOVPE. This type of incorporation is also referred to as unintentional incorporation. It should be noted that MOVPE is a possible and common method for producing GaN layers. In particular, GaN layers can also be produced using processes such as MBE, LPE, or HVPE.

[0054] Investigations have shown that by changing the growth conditions from the deposition of the first GaN sublayer to the second GaN sublayer, the level of unintentional incorporation of carbon and oxygen changes.

[0055] In one embodiment, both the first GaN sublayer and the second GaN sublayer have a carbon concentration that is unintentionally and inevitably generated, ie, as explained above, necessarily generated by the deposition process. The carbon concentration is higher in the first GaN sublayer than in the second GaN sublayer.

[0056] In other words, at least one deposition process parameter in the formation of the first GaN sublayer differs from one of the deposition process parameters for the formation of the second GaN sublayer, as a result of which the second GaN sublayer has a higher unintentional and unavoidable carbon concentration than the first GaN sublayer.

[0057] In a further development, at the interface, the ratio of the unintentional and unavoidable carbon concentration between the second GaN sublayer and that of the first GaN sublayer is in a range between 2 and 1000 or in a range between 4 and 200 or in a range between 10 and 100.

[0058] In another embodiment, the unintentional and unavoidable carbon concentration in the first GaN sublayer is constant or decreases towards the second GaN sublayer.

[0059] In one embodiment, in the first GaN sublayer, the unintentional and unavoidable carbon concentration is constant or decreases along the distance from the interface between the transition layer and the first GaN sublayer to the interface between the first GaN sublayer and the second GaN sublayer.

[0060] In one embodiment, the unintentional and unavoidable carbon concentration in the first GaN sublayer is in a range between l*10 17 cm' 3 and 5*10 18 cm' 3 and in the second GaN sublayer, the unintentional and unavoidable carbon concentration is in a range of 5*10 15 cm' 3 and 5*10 16 cm' 3 In one embodiment, both the first GaN sublayer and the second GaN sublayer have an oxygen concentration that is unintentionally and inevitably generated, ie, as explained above, necessarily generated by the deposition process. The oxygen concentration is higher in the first GaN sublayer than in the second GaN sublayer.

[0061] In other words, at least one deposition process parameter in the formation of the first GaN sublayer differs from one of the deposition process parameters for the formation of the second GaN sublayer, as a result of which the second GaN sublayer has a higher unintentional and unavoidable oxygen concentration than the first GaN sublayer.

[0062] In a further development, the ratio of unintentional and unavoidable oxygen concentration between the second GaN sublayer and the first GaN sublayer at the interface is in a range between 2 and 5000 or in a range between 4 and 200 or in a range between 10 and 100.

[0063] In another embodiment, the unintentional and unavoidable oxygen concentration in the first GaN sublayer is constant or decreases towards the second GaN sublayer.

[0064] In one embodiment, in the first GaN sublayer, the unintentional and unavoidable oxygen concentration is constant or decreases along the distance from the interface between the transition layer and the first GaN sublayer to the interface between the first GaN sublayer and the second GaN sublayer.

[0065] In a further development, the unintentional and unavoidable oxygen concentration in the first GaN sub-layer is in a range between 2*10 17 cm' 3 and 5*10 18 cm' 3 and in the second GaN sublayer, the unintentional and unavoidable oxygen concentration is in a range of l*10 15 cm' 3 and l*10 17 cm' 3. In one embodiment, the density of the filamentary dislocations in the first GaN sublayer is at least 2 times and at most 1000 times greater than the density of the filamentary dislocations in the second GaN sublayer.

[0066] In another embodiment, a plurality of patches containing oxygen are formed on the upper surface of the silicon layer of the substrate. This forms the oxide patches on the upper surface of the silicon layer and below the transition layer.

[0067] In a further development, the oxygen-containing spots cover at least 0.005% and at most 35% of the upper surface of the substrate. Alternatively, the oxygen-containing spots cover at least 5% and at most 50% of the upper surface of the substrate.

[0068] It is understood that the layers are each formed over the entire surface. The term "over the entire surface" refers to the entire surface of the semiconductor wafer. Furthermore, it should be noted that the spots consist predominantly of silicon oxide, i.e., they consist of oxide or at least comprise oxide. In other words, the oxide spots remain and are covered by the subsequent layers. However, the oxide spots do not form a continuous layer on top of the silicon layer.

[0069] One advantage is that, surprisingly, the spots can be used to improve the quality of the semiconductor buffer layer sequence, i.e., the GaN layers on the respective top surface. In particular, coalescence during the growth of the semiconductor buffer layer sequence can be improved.

[0070] In one embodiment, the oxygen-containing spots preferably cover a minimum of 0.2% to a maximum of 20%, or a minimum of 0.01% to a maximum of 30%, or a minimum of 0.1% to a maximum of 25% of the upper side of the substrate and are integrally bonded to the upper side of the substrate. In another embodiment, the oxygen-containing spots each have a size of at least 10 nm, or at least 50 nm, or at least 100 nm. The spots can have a wide variety of shapes.

[0071] In a further development, the oxygen-containing spots each have an extension of a maximum of 5 m or a maximum of 1 pm or a maximum of 0.5 pm.

[0072] In a further development, the oxygen-containing spots have a thickness in a range between one monolayer and 4 nm, wherein the thickness of the monolayer is approximately 0.4 nm.

[0073] In one embodiment, the oxygen-containing spots comprise or consist of a silicon dioxide and / or a silicon monoxide, collectively referred to below as silicon oxide.

[0074] In another embodiment, the silicon oxide is formed as a naturally grown oxide. Natural oxide, i.e., silicon oxide, grows in an oxygen-containing environment.

[0075] It should be noted, however, that the formation of the natural oxide accelerates in a humid environment. The density of natural oxide is lower than that of a thermally grown oxide. Naturally grown oxide, as defined herein, refers to a silicon oxide that is preferably formed at room temperature, but most preferably at a temperature below 100°C or below 200°C. The thickness of the natural oxide is between one monolayer, i.e., approximately 0.4 nm and 4 nm. In one embodiment, the thickness of the natural oxide is between 1 nm and 2 nm.

[0076] A thermally grown oxide is understood here to be a silicon oxide that is preferably grown at a temperature above 500°C. Preferably, the density of the thermal oxide is more than 30% higher than that of the natural oxide.

[0077] In another embodiment, the oxygen-containing spots comprise silicon oxide and oxynitride or consist of silicon oxide or consist of oxynitride.

[0078] In one embodiment, the oxygen-containing spots are distributed almost evenly on the upper side. The term "evenly distributed" is understood here to mean that the spots are evenly distributed over the entire surface of the semiconductor wafer. In one embodiment, the number of spots in a region of the wafer comprising at least 20% of the total area does not deviate by more than 50% from the number of spots in a second, equally sized region on the semiconductor wafer.

[0079] In a further development, the semiconductor buffer layer sequence has a thickness of at least 1 pm or at least 4 pm and a maximum thickness of 30 pm. In one embodiment, the semiconductor buffer layer sequence has a thickness of between 0.5 pm and 10 pm or between 1.0 pm and 5 pm on the top side.

[0080] In another embodiment, the transition layer comprises or consists of a layer sequence of at least two different layers.

[0081] In a further development, the transition layer comprises a nucleation layer consisting of AlN that completely or partially covers the upper side of the substrate. The nucleation layer has a layer thickness of at least 5 nm and at most 50 nm. It is understood that if oxide spots are present on the upper side of the substrate, the nucleation layer at least partially covers the oxide spots.

[0082] In another embodiment, the nucleation layer has a plurality of holes. Preferably, the proportion of the surface area of ​​the holes on the upper side of the nucleation layer, i.e., the total hole area, is between 1% and 30% of the total surface area of ​​the nucleation layer.

[0083] The proportion of the total hole area is calculated as the total area of ​​the holes on the entire layer surface divided by the total area of ​​the nucleation layer. If the transition layer on a top side consists exclusively of the top side of the nucleation layer, it is understood that the transition layer has the same distribution and number of holes as the nucleation layer.

[0084] In a further development, the holes are, in a first approximation, evenly distributed over the entire surface of the nucleation layer.

[0085] In another development, the hole area relative to the total surface of the nucleation layer is in a range between 5% and 20%.

[0086] In one embodiment, a masking layer comprising (Al)GaN or consisting of (Al)GaN and at least partially covering the nucleation layer is formed on the nucleation layer.

[0087] In one embodiment, the masking layer has a surface area and an aluminum content between 0% and 10% based on all elements of main group III of the periodic table. The thickness of the masking layer is at least 100 nm or at least 300 nm and a maximum of 900 nm. In another embodiment, the masking layer has a thickness between 400 nm and 600 nm.

[0088] In a further development, the first GaN layer is formed on the masking layer. Preferably, the first GaN layer is formed directly on the surface of the masking layer.

[0089] In one embodiment, a sequence of an intermediate layer and a second layer comprising GaN is formed on the first GaN layer. It is understood that the second GaN layer comprises a first GaN sublayer or consists of a first GaN sublayer. In a further development, the second GaN layer comprises a first GaN sublayer and a second GaN sublayer, or the second GaN layer consists of a first GaN sublayer and a second GaN sublayer.

[0090] In one embodiment, multiple sequences are formed on the first GaN layer. At least one sequence and a maximum of 10 sequences are formed on the first GaN layer.

[0091] In one embodiment, the sequence has a thickness between 0.5 pm and 10 pm or between 1.0 pm and 5 pm. In a further development, the sequence has a thickness of at least 1 pm or at least 4 pm and a maximum thickness of 30 pm.

[0092] In one development, the intermediate layer includes AI. In another development, the intermediate layer includes AIGaN or consists of AIGaN.

[0093] The invention will be explained in more detail below with reference to the drawings. Similar parts are labeled with identical designations. The illustrated embodiments are highly schematic, ie the distances and the lateral and vertical extensions are not to scale and, unless otherwise stated, do not have any deducible geometric relationships to one another.

[0094] Figure 1 shows a cross-section of a semiconductor wafer with a GaN layer, wherein the GaN layer is divided into a first GaN sub-layer and a second GaN sub-layer,

[0095] Figure 2 shows a profile of the lattice constant of the semiconductor wafer, shown in connection with the figure in Fig.l,

[0096] Figure 3 shows a cross section on a semiconductor wafer with a further embodiment of the layer arrangement, Figure 4 shows a cross section on a semiconductor wafer with a detailed view of the differences in the thread-like dislocations between the first GaN sub-layer and the second GaN sub-layer.

[0097] The layer arrangements shown below above the substrate are part of a semiconductor buffer layer sequence, wherein a so-called active layer for producing GaN semiconductor components is formed above the semiconductor buffer layer sequence, which is generally not considered to be part of the semiconductor buffer layer sequence.

[0098] Figure 1 shows a cross-sectional view of a semiconductor wafer consisting of a substrate 10, preferably a silicon substrate, with a top surface OS and a bottom surface US. The substrate 10 consists of monocrystalline silicon at least on the top surface and has a diameter of at least 100 mm.

[0099] A transition layer UES with a top side OF is formed on the top side OS of the substrate 10, wherein the transition layer UES is integrally connected to the substrate 10. A first GaN layer GS is integrally arranged on the top side OF of the transition layer UES.

[0100] The first GaN layer GS comprises or consists of a first GaN sublayer GN1 with a thickness D1 and a second GaN sublayer GN2 with a thickness D2, wherein the thickness of the first GaN sublayer GN1 is less than or equal to the thickness D2 of the second GaN sublayer. An interface GRZ is formed between the first GaN sublayer GN1 and the second GaN sublayer GN2.

[0101] An intermediate layer ZW is formed above the first GaN layer. In this case, the intermediate layer ZW is firmly bonded to the top surface of the first GaN layer GS. A further GaN layer GAU is formed on top of the intermediate layer ZW. The intermediate layer ZW and the further GaN layer together form a sequence AF.

[0102] In an embodiment not shown, several sequences AF are arranged one above the other. It is understood that in each of the sequences AF, the further GaN layer GAU comprises or consists of a first GaN sublayer and / or a second GaN sublayer.

[0103] The figure in Figure 2 shows the course of the lattice constant of the semiconductor wafer, shown in connection with the figure in Figure 1. In the following, only the differences to the figure in Figure 1 are explained.

[0104] The first GaN sublayer GN1 has a first lattice constant Gl. The second GaN sublayer GN2 has a second lattice constant G2. In this case, the first lattice constant GN1 and the second lattice constant GN2 are almost equal or exactly equal.

[0105] An optional sequence of the intermediate layer ZW and the further GaN layer is shown in dashed lines, whereby the lattice constant remains the same.

[0106] Figure 3 shows a cross-section of a semiconductor wafer with another embodiment of the layer arrangement. Only the differences from the previous figures are explained below.

[0107] On the top side OS of the silicon substrate 10, spots OXF are shown in dashed lines, i.e., optionally containing oxygen. It should be noted that the spots OXF, referred to below as oxide spots, are distributed as evenly as possible on the top side OS. However, the spots OXF have irregular outlines and sizes (not shown) and cover at least 0.005% and a maximum of 50% of the top side OS of the substrate 10. The optional spots OXF are shown as part of the transition layer UES. The transition layer UES comprises a nucleation layer NUS and a masking layer MASK formed on the nucleation layer NUS. The masking layer MASK forms the top side OF of the transition layer UES.

[0108] A thin connection layer VS is optionally arranged at the interface GRZ between the first GaN sublayer GN1 and the second GaN sublayer GN2.

[0109] The connection layer VS has the same lattice constant as the underlying first GaN sublayer GN1.

[0110] The illustration in Figure 4 shows a cross-section on a semiconductor wafer with a detailed view of the first GaN layer GS with differences in thread-like dislocations FV between the first GaN sublayer GN1 and the second GaN sublayer GN2.

[0111] The second GaN sublayer GN2 has, on average, a smaller number of filamentary dislocations FV than the first GaN sublayer GN1. Furthermore, the filamentary dislocations FV in the first GaN sublayer GN1 generally have a more oblique orientation than the filamentary dislocations FV in the second GaN sublayer GN2. In other words, the first GaN sublayer has a lower quality than the second GaN sublayer GN2.

[0112] The number of filamentary dislocations (FV) in the second GaN sublayer GN2 is also lower than in the first GaN sublayer GN1. As a result, the size of the crystallites in the second GaN sublayer GN2 is also significantly larger than in the first GaN sublayer GN1.

Claims

Patent claims 1. Semiconductor wafer for forming GaN semiconductor components having a diameter of at least 100 mm - a substrate (10) having a top side (OS) and a bottom side (US), wherein the substrate (10) consists of silicon on the top side (OS), a transition layer (UES) is integrally connected to the top side (OS) of the substrate, a first GaN layer (GS) integrally formed on the transition layer (UES), characterized in that the first GaN layer (GS) comprises a first GaN sub-layer (GN1) and a second GaN sub-layer (GN2), and the second GaN sub-layer (GN2) is formed on the first GaN sub-layer (GN1), wherein the second GaN sub-layer (GN2) has on average a smaller number of thread-like dislocations (FV) than the first GaN sub-layer (GN1), and the first GaN sub-layer (GN1) has a first layer thickness (D1) and the second GaN sub-layer (GN2) has a second layer thickness (D2), wherein the second layer thickness (D2) is greater than or equal to the first layer thickness (Dl).

2. Semiconductor wafer according to claim 1, characterized in that the difference in the curvature of the semiconductor wafer during the deposition of the first GaN sub-layer (GN1) and the second GaN sub-layer (GN2) is less than 5 km' 1 is.

3. Semiconductor wafer according to claim 1 or claim 2, characterized in that the first GaN sub-layer (GN1) has a first lattice constant (Gl) and the second GaN sub-layer (GN2) has a second lattice constant (G2), wherein the first lattice constant (Gl) is equal to the second lattice constant (G2) or the difference between the two lattice constants (Gl, G2) is less than 1%. Semiconductor wafer according to one of the preceding claims, characterized in that the second GaN sublayer (GN2) is formed integrally on the first GaN sublayer (GN1) or a connecting layer (VS) is formed between the first GaN sublayer (GN1) and the second GaN sublayer (GN2), wherein the lattice constant of the connecting layer (VS) is equal to the lattice constant of the first sublayer (GN1) or the lattice constant of the connecting layer (VS) is different from the lattice constant of the first GaN sublayer (GN1) or the second GaN sublayer (GN2). Semiconductor wafer according to one of the preceding claims, characterized in that the ratio of the sum of the thread-like dislocations (FV) of the second GaN sublayer (GN2) to the sum of the thread-like dislocations (FV) of the first GaN sublayer (GN1) is between 2 and 1000 or between 5 and 40.Semiconductor wafer according to one of the preceding claims, characterized in that the surface density of the thread-like dislocations of the first GaN sub-layer (GN1) is in a range between 2*10. 9 cm' 2 and l*10 10 cm' 2 and the surface density of the thread-like dislocations (FV) in the second GaN sublayer (GN2) in a range between l*10 7 cm' 2 and l*10 9 cm' 2 The semiconductor wafer according to one of the preceding claims, characterized in that the first GaN sublayer (GN1), in contrast to the second GaN sublayer (GN2), has a larger total number of thread-like dislocations (FV) with an oblique course. The semiconductor wafer according to one of the preceding claims, characterized in that at least 50% or at least 80% of the thread-like dislocations (FV) in the first GaN sublayer (GN1) have an oblique course. Semiconductor wafer according to one of the preceding claims, characterized in that the ratio of the thickness (D2) of the second GaN sublayer (GN2) to the thickness (D1) of the first GaN sublayer (GN1) is in a range between 1 and 100 or in a range between 1 and 10 or in a range between 1 and 3. Semiconductor wafer according to one of the preceding claims, characterized in that the first GaN sublayer (GN1) and the second GaN sublayer (GN2) each have unintentionally incorporated oxygen and / or unintentionally incorporated carbon, wherein the concentration of oxygen and / or carbon in the first GaN sublayer (GN1) is greater than in the second GaN sublayer (GN2).Semiconductor wafer according to one of the preceding claims, characterized in that at the boundary layer (GRZ) the ratio of the concentration of unintentionally incorporated carbon between the second GaN sub-layer (GN2) and that of the first GaN sub-layer (GN1) is in a range between 2 and 1000 or in a range between 4 and 200 or in a range between 10 and 100. Semiconductor wafer according to one of the preceding claims, characterized in that at the boundary layer (GRZ) the ratio of the concentration of unintentionally incorporated oxygen between the second GaN sub-layer (GN2) and that of the first GaN sub-layer (GN1) is in a range between 2 and 5000 or in a range between 4 and 200 or in a range between 10 and 100. Semiconductor wafer according to one of the preceding claims, characterized in that in the first GaN sub-layer (GN1) the unintentional oxygen concentration is in a range between. 2*10 17 cm' 3 and 5*10 18 cm' 3 and in the second GaN sublayer (GN2) of l*10 15 cm' 3 and l*10 17 cm' 3 lies.

14. Semiconductor wafer according to one of the preceding claims, characterized in that in the first GaN sub-layer (GN1) the unintentional carbon concentration is in a range between l*10 17 cm' 3 and 5*10 18 cm' 3 and in the second GaN sublayer (GN2) of 5*10 15 cm' 3 and 5*10 16 cm' 3 15. Semiconductor wafer according to one of the preceding claims, characterized in that the first GaN layer (GS) has a total layer thickness of at least 0.35 pm and a maximum of 5 pm.

Images