Neuroimplant with data rate-reduction section

Abstract

The invention relates to a neuroimplant for the brain region, having: at least one detection section for detecting signals from the brain region; an electrode section comprising at least one electrode which can be coupled to the detection section and which can be arranged in the brain region and is designed to electrically contact the brain region; at least one digitization section for generating at least one digital data stream from the signals detected by the at least one detection section, wherein the at least one data stream comprises a respective sequence of data points; and a data reduction section which is designed to reject data points in the sequence of data points from the at least one data stream according to a specified formula.

Description

[0001] Neuroimplant with data rate reduction section

[0002] The present invention relates to a neuroimplant with a data rate reduction section.

[0003] Neuroimplants are used in human-machine interfaces. These are based on implantable microelectronics that enable low-noise reading of neural signals in parallel across multiple channels and flexible stimulation of brain activity.

[0004] Medical applications include the diagnosis and treatment of neurodegenerative diseases such as Parkinson's, Alzheimer's, and epilepsy. Applications in basic neurophysiological research and in the field of novel, directly thought-controlled prostheses are also conceivable.

[0005] The multitude of applications also results in fundamentally different requirements for the underlying hardware. For example, in implantable systems, the permissible power consumption is severely limited, as the surrounding tissue could be damaged by excessive heat generation. The neurosignals of interest are generally divided into two categories. In the low frequency range between approximately 0.2 and 200 Hertz, local field potentials can be measured; these consist of the superimposed potentials of hundreds or even thousands of neurons in the area around the recording electrode. The second category comprises action potentials (spikes), which occur in the frequency range from approximately 200 to 8000 Hertz and demonstrate the activation process of a single neuron. Depending on the application, different signal bands and different numbers of channels are required as a data source.At the same time, however, it is desirable to provide a common hardware platform for all applications so that research in this area is not hampered by the limited availability of precisely tailored microelectronics. The object of the present invention is therefore to provide a data rate module for a neuroimplant that at least partially alleviates the aforementioned technical problems.

[0006] This object is achieved by the data rate module according to claim 1. Advantageous further developments are defined in the dependent claims.

[0007] Accordingly, a neuroimplant for the brain region is provided, comprising: at least one detection section for detecting signals from the brain region, an electrode section with at least one electrode, which can be coupled to the detection section and can be arranged in the brain region and is designed to make electrical contact with the brain region, at least one digitization section for generating at least one digital data stream from the signals detected by the at least one detection section, wherein the at least one data stream each comprises a sequence of data points, and a data reduction section which is designed to discard data points in the sequence of data points from the at least one data stream according to a predetermined scheme.

[0008] Thus, the data rate of at least one data stream can be reduced according to the predetermined scheme.

[0009] The adjustment of the data rate at which neural signals are output can be specifically controlled using two schemes that allow for flexible selection of the channels of interest and the number of data points to be discarded between two transmitted data points per channel. This enables adaptation (= optimization) of a common hardware platform to a wide variety of application areas. The innovation that is the subject of this invention therefore comprises a digital section that allows the chip's data rate to be modified using very simple means. This has a direct impact on both the utilization of the readout instance (e.g., microcontroller) and the system's power consumption. Both can be reduced. Power reductions are of utmost importance, especially in implantable microelectronics.

[0010] Furthermore, optimizations for specific application scenarios are possible while using an identical hardware platform.

[0011] The scheme may include discarding all data points from a data stream.

[0012] Alternatively or additionally, the scheme may comprise regularly discarding a predetermined number of data points from at least one data stream.

[0013] In general, the scheme may involve discarding n data points from each sequence of m data points in a data stream, where m and n are natural numbers.

[0014] A first register may be provided which contains a value for each of the at least one data stream which is representative of whether all data points of the respective data stream are discarded or not.

[0015] A second register may be provided which contains a value representative of discarding n data points from each sequence of m data points of at least one data stream.

[0016] The first and / or second register can be programmable.

[0017] In the neuroimplant according to a variant, it is provided that the at least one detection section, the at least one digitization section and the data reduction section are arranged on a common semiconductor substrate and are designed in particular as an ASIC component.

[0018] The section according to the invention for reducing the output data rate offers two specific schemes in one variant: • Channel selection: By setting a 32-bit register, for example, it is determined individually for each channel whether the measured data is to be discarded (“0”) or not (“1”), i.e. output.

[0019] • Discard data points: By setting a 5-bit register, for example, a number is defined that determines how many available data points per channel are discarded between two actually sent data points. For example, a "1" (binary "00001") means that one data point is discarded between two output data points – thus, only every second data point leaves the chip, and the data rate is halved accordingly.

[0020] Both schemes can be combined without the system becoming untestable and thus unverifiable due to the large number of configuration options. This is an important feature, as very strict approval requirements must be met for human-implantable electronics.

[0021] Discarding unnecessary data points allows for a significant increase in efficiency, particularly in systems that only require local field potentials and thus can forgo the higher data rate required to measure spike potentials. Averaging to utilize the discarded data points was deliberately omitted, as a significant improvement in input-related noise is generally not expected. This is because flicker noise (1 / f noise) is the dominant noise process, particularly in the low frequency range, which is particularly affected by discarding many data points. This exhibits significant temporal correlations, and thus no improvement can be achieved through temporal averaging.

[0022] According to one variant, the section is located on the neuromodulation ASIC (application-specific integrated circuit) with 32 bidirectional channels. This is very flexible and can therefore be used in many different application scenarios.

[0023] Furthermore, the detection section can be configured to perform signal filtering, in particular high-pass filtering, which can be adjusted according to the predetermined scheme. Thus, the signal filtering can be adapted to the data rate of the data stream (data points per unit of time) after the data rate reduction by the data rate reduction section.

[0024] The invention and embodiments are described in more detail with reference to the drawing.

[0025] Fig. 1 shows an embodiment of the invention; and

[0026] Fig. 2 shows the arrangement and function of the data reduction section.

[0027] Fig. 1 illustrates a neuroimplant according to an embodiment of the invention in which the data rate reduction section is realized.

[0028] The neuroimplant comprises at least one detection section 230 for detecting signals from the brain region and is divided into a plurality of similarly designed channels 10; a typical number is 32 channels. Only one channel 10 is illustrated in Fig. 1. This neuroimplant is therefore a neuromodulator or closed-loop neuroimplant.

[0029] The electrode section 600 comprises a number of electrodes and is connected to the at least one detection section 230. The number of electrodes is typically at least as large as the number of channels 10.

[0030] The neuroimplant according to one variant additionally has at least one stimulation section 220 for generating stimulation voltages for the brain region, as well as an electrode section 600 connected to the stimulation section 220 for contacting the brain region. The electrode section 600, with at least one electrode, is coupled to the stimulation section 220 via a connection 700 for transmitting the stimulation signals.

[0031] Each channel 10 is assigned or assignable to exactly one electrode of the electrode section 600, a stimulation section 220 and a detection section 230.

[0032] Each channel 10 (according to the variant) is bidirectional, meaning it can conduct electrical signals and other electrical quantities in two directions. In one direction, stimulation signals generated by at least one stimulation section 220 are conducted to the respective electrode; in the opposite direction, neural signals from the brain region, which are detected via the electrode of electrode section 600, are conducted to at least one detection section 230.

[0033] The stimulation section 220 of each channel 10 includes a digital-to-analog converter (DAC) 221 for generating analog stimulation signals from externally supplied digital control signals. The DAC 221 may be a 5-bit current DAC with a high-voltage push-pull output stage. The high voltage is, for example, 18 V.

[0034] The stimulation section 220 can be configured in different modes. In a first mode, it generates current-controlled stimulation (CCS) signals, and in a second mode, it generates voltage-controlled stimulation (CVS) signals. In the second mode, the DAC 221 and the high-voltage output are embedded in a DSM-based feedback loop.

[0035] In the exemplary embodiment, the stimulation section 220 has an increased dynamic range by scaling the current mirror gain options. In the exemplary embodiment, the dynamic range is 66 dB, with stimulation currents from 5 pA to 10 mA.

[0036] The stimulation section 220 features flexible waveform generation based on a state machine with sequential execution of stimulation commands. This is enhanced with programmable loops within the command panel, enabling extended repeated execution of waveforms and commands.

[0037] The entire neuroimplant can be controlled by a microcontroller unit (MCU, not illustrated).

[0038] The neuroimplant further comprises a switch matrix section 240, which is arranged between the electrode section 600 and the at least one detection section 230. The switch matrix section 240 comprises switching devices 241, 242 for each channel 10 to couple or decouple the electrode of each channel 10 to the detection section 230 of the channel 10. In addition, the switch matrix section 240 comprises switching devices 243, with which each electrode can be connected to ground GND. In this way, the respective electrode can be discharged, for example. Furthermore, the switch matrix section 240 comprises switching devices 244, with which an electrode (or several electrodes) can be switched as a reference electrode REF. If the electrode is connected as a reference electrode REF, it can be coupled to the reference input, e.g. the inverting input (-) of each detection section 230, while it is separated from the measuring input, e.g.the non-inverting input (+) of the respective detection section 230. In this way, each detection section 230 can have the potential REF of the reference electrode applied as the common reference potential.

[0039] This feature is often required in practical applications because the characteristics of implanted electrodes are unknown before implantation and can also vary over time, making it disadvantageous to define a specific electrode as a reference electrode a priori.

[0040] Thus, the switch matrix section 240 is adjustable so that the reference electrode REF is not simultaneously used as a charge sink for the passive discharge of electrodes after stimulation, as this could lead to artifacts and charging of the reference electrode REF. Instead, an electrode different from the reference electrode serves as the ground electrode GND for discharging. This also provides a better reference when detecting and recording neurosignals.

[0041] Each channel 10 is digitally controlled by a state machine that is programmable via SPI communication (SPI = Serial Peripheral Interface).

[0042] Furthermore, the at least one detection section 230 is designed to be programmable, which makes it possible to record either local field potentials (LPFs), action potentials (APs) or both bands with selectable gain and bandwidth settings.

[0043] At least one digitization section 800, specifically an analog-to-digital converter (ADC, I-DSM 1, I-DSM 2), is provided to digitize the detected analog neural signals and generate at least one data stream (via SPI 850) therefrom. In one embodiment, two 16-bit ADCs are provided; each ADC can be coupled to 16 channels. Each ADC can be periodically connected in time-multiplex mode to the individual channels, which digitize the detected signals via them.

[0044] Typically, the ADC's sampling frequency is constant, e.g., 20 kHz. However, this exceeds the required data rate if only LFP signals are to be recorded, resulting in an unnecessarily high workload on the MCU that is supposed to process the data streams. This would require the MCU to downsample the data streams to avoid excessive power consumption in the SPI Bluetooth connection outside the body.

[0045] Therefore, a section 900 for reducing the data rate of the digitized data streams is provided, which is designed to adapt the digital data streams according to the bandwidth of the SPI interface. For this purpose, the data reduction section 900 is programmable such that it discards n data points from each sequence of m data points of the data stream of a channel and allows only the remaining data points to pass unchanged; where m and n are natural numbers.

[0046] Additionally or alternatively, individual channels can be completely deactivated, i.e. the data points of the respective data stream can be completely discarded.

[0047] Fig. 2 illustrates the arrangement and function of the data reduction section.

[0048] In the top right corner of the figure, a data stream with full data rate, i.e. without data reduction by discarding data points, is shown, below with reduction.

[0049] According to the invention, data points (or samples) are suppressed according to the respective reduction scheme, while the non-suppressed data points are forwarded unchanged. In the example, the data streams of half of the channels 10 are discarded, while only every third point of the remaining data streams is transmitted; thus, two out of every three data points are discarded (m=3, n=2).

[0050] A first register 950 can be provided for selecting the data stream or streams (channel / channels 10) that are to be completely suppressed. By setting this 32-bit register, for example, it is individually determined for each channel whether the detected data stream is to be output ("1") or discarded ("0"). To define whether individual data points of a data stream are to be discarded, a second register 955 can be provided. By setting the 5-bit register, for example, a number is defined that determines how many available data points per channel are discarded between two actually sent data points. For example, a 1 (binary "00001") means that one data point is discarded between two output data points - thus only every second data point leaves the chip, and the data rate is halved accordingly.

[0051] While transmitting only a portion of the samples seems like a primitive measure, since averaging over multiple samples could suppress noise through downsampling, this only applies to white noise, not to the correlated flicker noise prevalent in LPF signals. Because downsampling is not feasible in the AP region dominated by white noise due to bandwidth requirements, there is no significant benefit there either. Thus, downsampling can be omitted entirely.

[0052] The data rate reduction is achieved by a section 900 located on the ASIC together with the other sections of the neuroimplant. The data rate can therefore be reduced even before the data stream leaves the neuroimplant. The (external) MPU is thus relieved of this task, and the communication connection is protected in terms of the required bandwidth.

[0053] Furthermore, the detection section 230 can be configured to perform signal filtering, in particular high-pass filtering, which can be adjusted according to the predetermined scheme. Thus, the signal filtering can be adapted to the data rate of the data stream (data points per unit of time) after the data rate reduction by the data rate reduction section.

Claims

September 13, 2023 CorTec GmbH C55949PC GS Claims 1. A neuroimplant for the brain region, comprising: at least one detection section (230) for detecting signals from the brain region, an electrode section (600) with at least one electrode, which can be coupled to the detection section (230) and can be arranged in the brain region and is designed to make electrical contact with the brain region, at least one digitization section (800) for generating at least one digital data stream from the signals detected by the at least one detection section (230), wherein the at least one data stream each comprises a sequence of data points, and a data reduction section (900) which is designed to discard data points in the sequence of data points from the at least one data stream according to a predetermined scheme.

2. A neuroimplant according to the preceding claim, wherein the scheme comprises discarding all data points of a data stream.

3. A neuroimplant according to any one of the preceding claims, wherein the scheme comprises regularly discarding a predetermined number of data points from the at least one data stream. Neuroimplant according to one of the preceding claims, wherein the scheme comprises discarding n data points from each sequence of m data points of a data stream, where m and n are natural numbers. Neuroimplant according to one of the preceding claims, wherein a first register (950) is provided which contains, for each of the at least one data stream, a value representative of whether or not all data points of the respective data stream are discarded. Neuroimplant according to one of the preceding claims, wherein a second register (955) is provided which contains a value representative of discarding n data points from each sequence of m data points of at least one data stream. Neuroimplant according to one of the preceding claims, wherein the first and / or the second register is programmable.Neuroimplant according to one of the preceding claims, wherein the at least one detection section, the at least one digitization section (800), and the data reduction section (900) are arranged on a common semiconductor substrate and are in particular designed as an ASIC component. Neuroimplant according to one of the preceding claims, further comprising a switch matrix section (240) arranged between the electrode section (600) and the at least one detection section (230), wherein the switch matrix section (240) comprises switching devices (241, 242) for coupling or decoupleing the electrode of each channel (10) to the detection section (230) of the channel (10). Neuroimplant according to one of the preceding claims, further comprising:. at least one stimulation section (220) for generating stimulation signals for the brain area. Neuroimplant according to the preceding claim, wherein the switch matrix section (240) comprises switching devices (243) with which an electrode can be connected to a ground point (GND). Neuroimplant according to the preceding claim, wherein the switch matrix section (240) comprises switching devices (243) with which a predetermined electrode can be switched as a reference electrode (REF) for the at least one detection section (230). Neuroimplant (1) according to one of the preceding claims, wherein the neuroimplant is divided into a number of channels (10), each channel (10) of which has a stimulation section (220), a detection section (230), and an electrode of the electrode section (60).The neuroimplant according to one of the preceding claims, further comprising a switch matrix section (240) arranged between the electrode section (600) and the at least one detection section (230), wherein the switch matrix section (240) comprises switching devices (241, 242) for coupling or decoupleing the electrode of each channel (10) to the detection section (230) of the channel (10). The neuroimplant according to one of the preceding claims, wherein the detection section (230) is configured to perform signal filtering, in particular high-pass filtering, which is adjustable according to the predetermined scheme.

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