Ferroelectric device with integrated heater for poling

EP4609262A1Pending Publication Date: 2025-09-03LUMIPHASE AG
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Patent Information

Application Number
EP2023805166
Authority / Receiving Office
EP · EP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2022-12-09
Filing Date
2023-11-03
Publication Date
2025-09-03

AI Technical Summary

Technical Problem

Silicon-based electro-optic modulators face limitations in fast modulation due to charge-carrier lifetimes and high power consumption, while integrating Pockels materials like lithium niobate and barium titanate is challenging due to alignment issues and high chip costs, especially with ferroelectric domain alignment requiring high voltages and precise temperature control.

Method used

An electro-optic device structure with a Pockels material layer, such as barium titanate, integrated with a waveguide and heater electrodes allows for efficient alignment of ferroelectric and crystallographic domains by applying a controlled electric field and heat, optimizing heat transfer and reducing the need for high voltages and large-scale temperature changes.

Benefits of technology

This approach enables efficient domain alignment at lower voltages, maintaining in-plane electric fields localized to the active device region, reducing chip-wide heating, and improving the effective Pockels response, thus enhancing the performance of silicon photonic modulators.

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Abstract

An electro-optic method and device that allows efficient poling of a ferroelectric device. The electro-optic device comprises a waveguide, barium titanate (BTO) layer adjacent to the waveguide, a heater electrode for heating the BTO layer in a vicinity of the waveguide, and at least one poling electrode near the waveguide for establishing an electric field in the BTO layer heated by the heater electrode.
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Description

FERROELECTRIC DEVICE WITH INTEGRATED HEATER FOR POLINGRELATED APPLICATIONS

[0001] This application claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 63 / 431,448, filed on December 9, 2022, which is incorporated herein by reference in its entirety.BACKGROUND OF THE INVENTION

[0002] Silicon photonics have become a platform for dense and low-cost photonic integrated circuits (PIC) for a wide range of applications that in many cases require fast and energyefficient electro-optical (EO) switches.

[0003] Silicon modulators have major constraints, however. Fast modulation of only the optical phase is not possible, as changes in real and imaginary parts of the refractive index are linked. In addition, operating speed is limited by charge-carrier lifetimes in forward-biased or reverse-biased devices. The silicon based state-of-the-art modulators are often based on differently doped regions in the waveguides. Higher doping is required for higher speed operation, but higher doping increases absorption. Another option is heater-based devices. Here, a heater (often metal wire) changes the temperature via Joule heating (an electrical current), and consequently changes the temperature in a waveguide in close proximity but far enough that the optical mode does not see the strongly optically absorbing heater conductor. Such heater-based devices tend to be slow, have high power consumption, and can suffer from crosstalk.

[0004] Pockels materials avoid these problems. In such materials, a change of the refractive index is induced by an electric field. But no Pockels effect exists in a centrosymmetric crystal such as silicon. Thus, materials with sizeable Pockels coefficients must be integrated onto silicon photonic structures to combine the benefits of bulk Pockels modulators with the low fabrication costs of integrated silicon photonics. Thus, the photonic integrated circuits based on Pockels materials are often multi domain and often need to be aligned to realize a large effective Pockels effect.

[0005] Several approaches exist for integrating a material with a large effective Pockels effect in silicon based modulators. For example, the Pockels effect is present in lithium niobate (EiNbCh, EN) single crystals. And, lithium niobate has been integrated with silicon waveguides, e.g. via wafer bonding techniques. However, the size mismatch between EN wafers and silicon wafers renders the integration process difficult to scale to large substrate sizes, which results in rather high chip costs.

[0006] Barium titanate (BaTiCh, BTO), for several reasons, has emerged to enable Pockels- effect-based devices on silicon. First, BTO has one of the largest Pockels coefficients. Second, it has previously been used in thin-film EO modulators on small-size oxide substrates. Third, BTO may be grown on silicon substrates with large wafer sizes, and with excellent crystal quality, and so forth. BTO-based photonic electro-optic components on silicon wafers have been demonstrated. However, two issues strongly impact EO response. First is alignment of crystallographic domains and second is alignment of ferroelectric domains.

[0007] In crystallographic alignment, domains are typically determined by epitaxial processes and are fixed after chip fabrication. The effective Pockels effect in a waveguide (WG) based device depends on the orientation of the crystallographic domains relative to the direction of the propagation of light and the orientation / direction of the applied electric field.

[0008] In ferroelectric alignment, as-grown films typically have ferroelectric domains with spontaneous polarization. The polarization is randomly oriented along specific crystallographic directions. Thus, a zero net-polarization results in most films, which yields a zero effective Pockels coefficient. Application of an external electric field aligns the ferroelectric domains. This process is referred to as “ferroelectric poling”. But some domains might not be poled despite the electric field, e.g. due to defect pinning or domain size effects. The lower the temperatures of the film, the more pronounced is the defect pinning.SUMMARY OF THE INVENTION

[0009] Modifying material properties of an electro-optic device are complex and expensive and often do not result in an enhancement of material properties of substrates or chips. If the temperature needed for efficient poling / domain alignment is applied to the whole chip, other components can be damaged.

[0010] The present invention allows for aligning ferroelectric and / or crystallographic domains at achievable voltages and may be supported by control electronics in a more efficient manner.

[0011] One aspect of the invention relates to an electro-optic device structure including a waveguide, a Pockels material structure such as a barium titanate (BTO) layer with the waveguide, heater electrodes and electrodes formed in conjunction with the waveguide. According to one configuration, the Pockels material layer is disposed within and / or adjacent to the waveguide, and a heater is provided for heating the Pockels material layer in a vicinity of the waveguide. Electrodes are further provided near the waveguide for establishing an electric fieldin the Pockets material layer heated by the heater electrode. This arrangement allows for the aligning of the ferroelectric and / or crystallographic domains of the Pockets material layer after fabrication of the Pockets material structure.

[0012] The approaches can provide a number of advantages. The material properties, crystallographic and ferroelectric effect in the electro-optic device may be modified by temporarily heating (to change the crystallographic and / or ferroelectric phase, coercive field) of the electro-optic device while applying an electric field to pole.

[0013] The one or more heater electrodes are disposed above the waveguide or below the waveguide and / or next to the waveguide in different configurations. The heat transfer from the heater electrode(s) to the waveguide may be optimized by thermal insulation using etched air grooves, suspended waveguides, and / or materials with low thermal conduction to isolate the heat flow to the vicinity of the waveguide, and / or by using highly thermally conductive materials to efficiently transfer heat from the heater electrode to the Pockels layer.

[0014] A second aspect of the invention relates to a method of fabricating an electro-optic device. The method includes steps as: deposit and pattern or otherwise form a Pockels material structure such as barium titanate (BTO) layer; deposit and pattern or otherwise form a waveguide in association with the Pockels material layer; form one or more heater electrodes adjacent, such as above, next and / or below, the Pockels material layer; form one or more poling electrodes and / or device drive electrodes on either side of the waveguide, although the same electrodes can be used as both poling electrodes during the process of aligning ferroelectric and / or crystallographic domains and drive electrodes during operation of electro-optic modulation or switching; and deposit a cladding layer around the waveguide.

[0015] These fabrication steps can generally be performed in different sequences depending on the device’s configuration and fabrication efficiencies.

[0016] Then, a poling voltage is applied, such as step or a ramp, or any other modulation function, to the poling electrodes, the heater electrode is energized such as by driving a current to heat the Pockels material layer adjacent to the waveguide, e.g. to an elevated temperature, its Curie or next crystalline phase transition temperature, or above / below. This can occur in any order. The heater electrode is then deenergized allowing the BTO layer to cool while maintaining the poling voltage.

[0017] In this implementation, the poling effect can also be revived at periodic intervals or based on feedback loops, when effective Pockels response drops below a threshold limit, orduring initialization of the device before operation. The poling voltage and temperature are applied in periodic intervals of seconds, minutes, hours or days or months in deployed devices. In same implementations, even shorter or longer poling intervals may be applied. The poling events may also be applied on unperiodic intervals, e.g. based on an open or closed control loop.

[0018] The approaches can provide a number of advantages, such as lower voltages may be used compared to poling at ambient temperature. With the presented approaches, poling may be done efficiently without heating up the whole chip or wafer and maintaining an in-plane electric field, localized to the active device region, during cool down. It should also be noted that sufficiently large in-plane fields are difficult to obtain on wafer scale because the gaps of the electrodes are typically large, on the order of wafer diameter. The present approaches can have a field of a few micrometers in spacing. In-plane fields are needed for in-plane domains, or convert crystallographic domains into such in -plane domains. Out-of-plane fields and poling is in principle possible.

[0019] Further, crystallographic alignment may happen on the electro-optic device level, which results in a single, or one preferred, crystallographic orientation of the Pockels material, to maximize the Pockels response or optimize other film parameters such as propagation losses, permittivites, etc., compared to the multi-domain crystallographic structure imposed by the thermodynamic s / kinetics properties during the film fabrication.

[0020] In some example embodiments, the electro-optic device is heated slowly from seconds to minutes and kept at high temperature for specific period. The electro-optic device is heated and cooled at a rate between microseconds to milliseconds to seconds. The voltage is applied constantly such as between 3 Volts (V) or less to 100 V or more.

[0021] Alternative approaches to align ferroelectric domains suffer from various challenges, such as requiring very large voltages when such alignment is done on a full wafer level, in particular for aligning domains within the plane of the wafer. When aligning the ferroelectric domains in devices without increasing the temperature results typically in a relatively low degree of domain alignment due to domain pinning and other effects that prevent switching of individual domains.

[0022] Approaches to align crystallographic domains require dedicated engineering and matching of crystallographic lattice, as well as engineering of thermal expansion coefficients. It is in particular difficult to align a tetragonal crystal on a cubic crystal in a dedicated way, such as orienting the c-axis of that tetragonal crystal parallel to the surface of the substrate, due to asymmetry mismatch. To align crystallographic domains, it is beneficial to undergo a crystalline phase transition, e.g. from a cubic symmetry to a tetragonal symmetry, while applying an electric field. The electric field may break the symmetry when passing that phase transition, e.g. it may distort the crystal lattice via the piezo-electric effect in same cases. However, similarly as mentioned above, applying an electric field e.g. on a wafer level while changing the temperature requires very large voltages. The approaches disclosed in this invention can provide a number of advantages such as lower voltages may be used.

[0023] The above and other features of the invention including various novel details of construction and combinations of parts, and other advantages, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular method and device embodying the invention are shown by way of illustration and not as a limitation of the invention. The principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In the accompanying drawings, reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale; emphasis has instead been placed upon illustrating the principles of the invention. Of the drawings:

[0025] FIGS. 1A, IB and 1C are cross-sectional views of implementations of electro-optic devices, in accordance with different embodiments of the present invention;

[0026] FIGS. 2A and 2B are top views of electro-optic device(s);

[0027] FIG. 3 is a hysteresis loop showing changes in coercive behavior of a ferroelectric material at different temperatures;

[0028] FIGS. 4A-4D shows a process of annealing the substrate at elevated temperature and in an electric field, in order to polarize the BTO and align its crystallographic domains;

[0029] FIG. 5 shows a crystallographic domain alignment procedure of the substrate, in accordance with an embodiment of the present invention;

[0030] FIGS. 6A-6D are plots of poling voltage and heater current as a function of time graphs for phase change of the substrate during the crystallographic and / or ferroelectric domain alignment, in accordance with embodiments of the present invention; and

[0031] FIG. 7A is a flowchart of a method fabricating the electro-optic device, in accordance with an embodiment of the present invention;

[0032] FIG. 7B is a flowchart of a method of modifying material properties of the electrooptic device, in accordance with an embodiment of the present invention.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which illustrative embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0034] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Also, all conjunctions used are to be understood in the most inclusive sense possible. Thus, the word "or" should be understood as having the definition of a logical "or" rather than that of a logical "exclusive or" unless the context clearly necessitates otherwise. Further, the singular forms and the articles "a", "an" and "the" are intended to include the plural forms as well, unless expressly stated otherwise. It will be further understood that the terms: includes, comprises, including and / or comprising, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Further, it will be understood that when an element, including component or subsystem, is referred to and / or shown as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

[0035] It will be understood that although terms such as “first” and “second” are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, an element discussed below could be termed a second element, and similarly, a second element may be termed a first element without departing from the teachings of the present invention.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined incommonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0037] FIGs. 1A, IB, and 1C are cross-sectional views of three implementations of electrooptic devices, according to the present invention.

[0038] The electro-optic devices 100 comprise a Pockels material structure such as a barium titanate (BaTiO3, BTO) layer 102 adjacent to a waveguide 104.

[0039] In other examples, the Pockels material can be at least one of lithium niobate, bariumstrontium titanate ((Ba,Sr)TiO3), lead zirconate titanate (Pb(Zr,Ti)O3 and / or polymers.

[0040] The waveguide 104 is positioned in proximity to the Pockels material structure 102 such that the optical mode in the waveguide extends into the BTO or other material. Note that in other embodiments, other materials are used as the Pockels material structure in place of BTO. In addition, the Pockels material structure may be a combination of different layers, where some are Pockels and some are not Pockels materials, e.g. BTO and strontium titanate (STO) or any other combinations, e.g. with oxide materials.

[0041] Note that Fig. 1C shows a rib waveguide configuration in which the waveguide 104 is part of the Pockels material structure 102.

[0042] In other examples, the waveguide 104 is disposed on one side of the Pockels material layer 102.

[0043] Further, the electro-optic device 100 has a heater electrode 106 for heating the Pockels material layer 102 in a vicinity of the waveguide 104. Further, the electro-optic device 100 has at least one poling electrode or combined poling and drive electrode 108 near the waveguide 104 for establishing an electric field in the Pockels material layer 102 heated by the heater electrode 106. Separate poling electrodes 108 and drive electrodes 112 are used in some examples (Fig. 1A). Typically, these electrodes are fabricated from aluminum, tungsten, TiN, gold, titanium, platinum, conductive oxides, or copper, or any other conductive layers, or any combinations of such materials.

[0044] The Pockels material structures 102 is typically transferred via wafer bonding to or deposited on a semiconductor substrate W, such as a silicon wafer, a germanium wafer, a germanium-on-silicon wafer, a silicon-on-insulator (SOI) wafer, or the like. There are typically several layers and devices C located between the actual silicon wafer material W and the Pockelsmaterial layer 102. The heater 106 can often be fabricated in these layers C between the wafer substrate W and the BTO layer 102.

[0045] The semiconductor wafer W may come in various sizes, such as 100mm, 150mm, 200mm, 300mm, or larger. In one embodiment, a large 300mm silicon wafer or larger is used to improve the productivity.

[0046] The waveguide 104 may be a SiN, a SiON, a Ge, or a Si waveguide fabricated on the Pockels material layer 102. Other materials with a higher refractive index than the cladding layer 110 may also be used. It may also be primarily constructed from the Pockels material 102, patterned by partial etching (see Fig. 1C). It can be noted that the waveguide 104 such as the SiN waveguide may be tuned to have a high non-linear refractive index. The electro-optic device 100 also includes a cladding layer 110 of silicon dioxide (SiO2), SisN4, SiO2, AI2O3, MgO, SiCN, SiON, SiCO, SiOCN, and HfO surrounding the waveguide 104 and the Pockels material structure 102. In one example embodiment, the thickness of the cladding layer 110 will usually have a uniform thickness of about 1 to 5 micrometers (um) or more.

[0047] Further, the cladding layer 110 is often disposed on top of the Pockels material structure 102, the waveguide 104, the heater electrode 106 and the poling electrodes 108 and drive electrodes 112, encapsulating them. The cladding layer 110 may be provided for enhancement of temperature into the Pockels material layer 102 and improving stability of the heater electrode 106. Further, the heater electrode 106 is driven by a current, and is located close to the waveguide 104 for good thermal coupling. Nevertheless, the heater electrode 106 should be far enough away from the waveguide to avoid significantly attenuating a waveguide optical mode.

[0048] The at least one pair of poling electrodes 108 is provided to establish the electric field in the BTO layer 102 applying a voltage across the electrodes, after supplying the current to the heater electrode 106. The pair of poling electrode 108 is used to establish alignment of the Pockels material structure 102. Then, the drive electrodes 112 or combined drive and poling electrodes 108 (as show in FIGs. IB and 1C) are used during device operation modulate the effective refractive index of the waveguide 104 and thus modulate the phase of the optical signal propagating in the waveguide 104 via the Pockels effect in the Pockels material structure 102.

[0049] Also, it is important to mention that if there are multiple sets of electrodes, i.e., drive and poling electrodes, they may share one physical electrode (e.g. the common ground electrode), resulting in only three conductors rather than four.

[0050] Careful fabrication of the Pockels material structure 102 is important. To align crystallographic domains, the device may be heated and cooled while applying an electric field, similar to poling the ferroelectric domains mentioned above. The annealing temperature may be above a temperature of a crystalline phase transition, e.g. from tetragonal to cubic in case of BTO, e.g. with a range of 120° C to 750° C or higher. In particular annealing at a higher temperature may help to release stress at the interface of the Pockels material structure 102. It should be noted that the anneal to high temperatures may reduce the mechanical coupling between the Pockels material layer 102 and the substrate / interface. Stress might be relieved in the Pockels material layer. If the Pockels material is patterned in a mesa structure (as shown in Fig. 1C), the strain relaxation may be uniaxial, resulting in a reduction of symmetry and hence an alignment of the extraordinary crystallographic direction and reduction of differently oriented domains. Mesa structure means that the Pockels layer is at least partially removed next to the waveguide, e.g. at the location of the electrodes 108 and / or next to the electrodes, typically at or near the sides of the electrodes that are further away from the waveguide.

[0051] After fabrication of the Pockels structure 102, it may be biaxial strained. If the film gets patterned in a mesa structure, uniaxial strain relief can occur, particularly at elevated temperatures. This can lead to a preferential alignment of crystallographic domains, when the material is heated and subsequently cooled through a phase transition temperature, reducing the density of domain boundaries and potentially improve electro-optical device performance. The heaters / electrodes can be completely (a) or partly (b) on the BTO mesa.

[0052] It can be noted that there may be a large difference in coefficient of thermal expansion (CTE) between the substrate W and the Pockels material structure 102 and / or any adjacent layers in the vicinity of the waveguide. For example, the CTE of the BTO is temperature dependent and about (10-15) E-6 / °C and the CTE of the Silicon is about 2.6E-6 / °C.

[0053] The large CTE difference between silicon and BTO may cause the stress in the Pockels material structure 102 to undergo from relaxed at the deposition of the film (which may be in the range of 300 to 1200 C) to tensile stressed at ambient temperatures. As such, at room temperature, the net or dominant stress in the Pockels material structure 102 may be tensile, which may energetically favor in-plane orientation. Therefore, the annealing temperature may be selected such that the Pockels material layer 102 may be under tensile stress at the ferroelectric phase transition temperature and may stabilize the polarization after cooling in the plane of the film. Applying an electric field during that cool down is an additional option that breaks thesymmetry between both orthogonal directions (parallel and perpendicular to the waveguide) and may favor the formation of a particular type of crystallographic domains.

[0054] With reference to Fig. 1A, the Pockels layer thickness T is typically 100-500 nanometers (nm), but may also be lOnm to 2000nm (but not limited to it). The electrode gap G between the poling electrodes is typically 4-20 micrometers, may also 1 micrometer to 100 micrometers, or in cases e.g. of plasmonic devices even as small as 20 nm. The cladding thickness may be in the range of 200nm to 10 micrometers, but in some cases even thicker. In some other cases, when the heater is for example placed below the Pockels material, there may be no cladding layer above and close the waveguide 104.

[0055] The heater separation H is typically in the range of 500 nm to 4 micrometers from the waveguide 104, but it may also be in the range of lOOnm to 10 micrometers.

[0056] In some cases, the heating may be performed via the poling electrodes 108 or drive electrodes 112 instead of a dedicated heater electrode 106. In that case, the poling or drive electrodes are used to both apply an electric field to the Pockels layer 102 and to heat the layer 102 via Joule heating.

[0057] FIG. 2A is a top view 200 of the electro-optic device 100. FIG. 2B is a top view showing several devices 200A-200C.

[0058] As discussed, the poling electrodes 108 are connected to a poling voltage source 222 via contacts 202. The at least one heater electrode 106 are connected to a heater current source 220 via contacts 204. The sources are typically controlled by a control circuit. In one example, multiple poling electrodes may be provided to align ferroelectric and / or crystallographic domains in the Pockels material layer 102. A second metal or conductive connection 205 is provided with vias to cross the waveguide 104, through the cladding layer 110 or other layers. The second metal connection 205 is connected at one end to the left poling electrode 108 and at other end to the contacts 202 for the driver or control circuit. In some other implementations, the contacts 202 or 204 may also be on different sides of the waveguide without the need for a metal connection 205.

[0059] As shown in Fig. 2B, multiple poling electrodes are implemented to allow different direction of the electric field and hence the poling direction and poling magnitude along the waveguide direction. This figure shows several devices 200A, 200B, 200C along a common waveguide 104. This implementation would be used for periodic poling, which enables a completely different set of applications in nonlinear optics. In some other implementation, theheating electrode may be shared across several devices, that is for example only one heater source may be used for several devices.

[0060] In some cases, the poling electrodes 108 or drive electrodes 112 may be used as heaters instead of a dedicated heater electrode 110. In that case, one or several poling electrodes are contacted at least at two locations, preferably at the end of the electrodes, to allow applying an electrical current along one or both of those electrodes to create heat via Joule heating.

[0061] FIG. 3 is a plot of polarization (pC / cm2) as a function of electric field (kV / mm) showing a hysteresis loop 300 illustrating the change in coercive behavior of a ferro-electric material at different temperatures. This shows just two specific examples: Process 1, Process 2.

[0062] The hysteresis loop 300 changes with the change in temperature induced by the heater electrode 106. In a poling strategy 1 “Process 1”, the poling field is typically higher as the field applied during the operation of the device (operating voltage). At the poling field E_po, a certain fraction of the ferroelectric domains will be poled, e.g. 90%. When reducing the field to the operating field, E_op, this fraction of poled domains may decrease. As a poling strategy 2 “Process 2”, heating the device at higher temperature (Temp_2), changes the shape of the hysteresis curve. At the same poling field E_po, a higher fraction of poled domains may be reached, e.g. -100%. Reducing the voltage to the operating field E_op may decay this fraction slightly. After cooling from Temp_2 to the initial temperature Temp_l, the fraction of aligned ferroelectric domains may be higher (e.g. -100%) compared to poling Strategy 1.

[0063] FIG. 4 A shows the domain structure of a ferroelectric film for different poling strategies. This is a process of annealing the substrate above the Curie temperature and in an electric field, in order to pole the ferroelectric domains in the Pockels material layer and to align its crystallographic domains.

[0064] Initially, at room temperature (RT), the polarization of crystals of the Pockels material layer 102 is random on the tetragonal crystal axes. When heating the sample above a phase transition, the film changes the crystallographic structure. E.g. for BTO, the spontaneous polarization vanishes in the crystals and the film becomes non-ferroelectric when heating above the Curie temperature. The transition temperature may be not a specific temperature but rather a temperature range, such as 120 to 250C for BTO thin films. The energy barrier between two polarization states is lowered with temperature. The Pockels material layer 102 can then be cooled under the application of the constant electric field (i.e. voltage of between 3 V to 100V) in order to invoke a net polarization.

[0065] Fig. 4B, Fig. 4C and Fig. 4D show different alignments between the electrodes and different domain patterns.

[0066] In Fig. 4B, the domains are simplified by squares. In reality, the domains have irregular shapes. The arrows represent the direction of the ferroelectric polarization. This can be flipped by 180 degrees in specific examples like BTO. Above the phase transition temperature, domains have different structure, e.g., cubic for BTO, which allows a new crystallographic domain pattern when cooling down effectively allowing 90 degrees rotations. The orientation of the waveguide in the electrodes relative to the ferroelectric domain orientations may vary and can be used to optimize the performance, such as the effective Pockels effect and refractive index are dependent on the geometry of the device. It should be noted that the electrodes do not need to be aligned to the major axes of the crystal as long as one of the two crystalline directions is preferred. The alignment of the electric field is not 45 degrees with respect to the crystalline major axes. The yield of the alignment might change since the energy difference of the two alignments is reduced.

[0067] In some materials such as BTO, such application of the electric field lifts the two-fold degeneracy of the tetragonally distorted crystal, but the anti-parallel aligned polarization state is meta stable up to a critical (i.e. coercive) field. The coercive field is dependent on the height of the energy barrier between different polarization states and on the temperature.

[0068] Further, the rotation of crystallographic domains requires more energy and is typically not feasible under electric field below the Curie temperature. For example, if BTO is annealed above the Curie temperature and an electric field is applied, the crystal stabilizes with the polarization axis (which is parallel to the crystallographic c-axis) aligned to the electric field. It can be noted that the electric field needs to lift the 2-fold degeneracy in some materials such as BTO. All or some of the domains will align along the electric field. It is possible, that layers exist e.g. at either interface, where the domain orientation is different from the bulk of the film, e.g. the majority being 90 degrees off.

[0069] Atomic displacement below the Curie temperature leads to a ferroelectric polarization and a tetragonal crystal structure. The energy barrier between different polarization states is lowering with increase in temperature from RT and vanishes above Tc, the required electric field for poling is reduced.

[0070] The energy barrier is lowered with the increase in temperature, as above, and one polarization state is preferred when the external electric filed is increased (E>0) and the crystal ispoled. A field (E>0) is applied while cooling down and the crystal stays in poled state, which is stable at lower temperature.

[0071] FIG. 5 shows a plot 500 of applied poling voltage generated by the poling voltage source 222 and heater current from the heater source 220 as a function of time in order to achieve crystallographic and / or ferroelectric domain alignment for the Pockels structure 102. Specifically, the heater current is initially off (a) and then ramped (b) raising the temperature of the Pockels structure. The temperature is increased to a higher temperature and even above the Curie temperature in the case of crystallographic alignment (c). Once at the target temperature, the electric field is applied by raising the voltage 612. With the electric field held constant, the temperature is ramped down (d).

[0072] The same procedure shown in FIG. 5 may be used for only ferroelectric domain alignment. In that case, temperatures below the Curie temperature can be employed.

[0073] FIGS. 6A-6B are plots 600 and 602 of voltage 612 and heater current 610 as a function of time graphs for phase change of the substrate during the crystallographic and ferroelectric domain alignment, in accordance with other embodiments of the poling process.

[0074] The ferroelectric poling occurs at an elevated temperature and at voltage (Vpole) with crystallographic domain alignment typically above the Curie temperature (T > Tc). The poling is performed as part of an initial fabrication process, e.g. as an inline alignment procedure e.g. on wafer level, after finishing fabrication, e.g. during testing of the final devices, or later in the field during operation / initialization. The concept can also be used repeatedly or periodically as a refresh operation to compensate for any unwanted domain flipping processes during operation or storage. In the refresh poling, for example, heating and poling is performed at periodic intervals, such as e.g. minutes, hours, days, months, etc., or based on feedback loops, such as, when effective Pockels response drops below threshold.

[0075] In operation, the heater electrode 106 supplies heat slowly to the Pockels material structure 102. The heating can be done by heating slowly, such as, seconds to minutes, and keeping high temperature for specific period, such as, seconds, minutes and then cooling down slowly. The heating operation may also be done quickly, e.g. between microseconds to milliseconds of heating and cooling. Such quick operation may reduce impact of leakage / ion migration, e.g. in the Pockels layer.

[0076] A voltage 612 is applied constantly for example between 3V-100V, generating an electric field between the poling electrodes on the order of 3kV / cm to IMV / cm. Depending onthe coercive field, device geometry and dimensions, and other material properties such as piezoelectric coefficients, the magnitude of the applied voltage may also be smaller or larger. See poling voltage plot 612. In other examples, a pulsing electric field is applied between subnanoseconds to milliseconds which may reduce ion migration and other non-poling effects or effects not-related to crystallographic domain alignment, as shown in FIG. 6B. In another example, a pulsing heater current 610 is applied between milliseconds to seconds with a largely steady state voltage 612, as shown in FIGs. 6C and 6D. In other examples, the electric field may be non-constant, such as oscillating with constant or varying amplitude, and with an increasing and decreasing magnitude. The time constants of such variations of the electric field may be in range such as nanoseconds to milliseconds. Also longer time constants may be used in some cases. The application of the electric field, or ramp enhances poling effect during the heating and cooling process. In other examples, the heating operation and / or the application of the electric field is cycled with constant or varying amplitude. For example, a constant electric field is applied and the heater current and thus the temperature of the Pockels material is cycled between a low temperature (e.g. room temperature) and a varying higher temperature (e.g. above the Curie temperature). The heater current may also by cycled around the Curie temperature or any phase transition temperature to enhance the alignment of ferroelectric and / or crystallographic domains.

[0077] After the poling procedure, the voltage may be reduced from Vpole to 0, or from Vpole to Voperating, as shown in FIG. 6A. Voperating refers to the voltage used during operation, and may be larger than 0 and equal to or smaller than Vpole. In same cases, it may be larger than Vpole. Typically, there is no interruption of the voltage supply between poling and operating the device, i.e. the voltage is not reduced any value lower than Voperate at any time during or after poling.

[0078] The plots show how the Pockels material layer 102 may be annealed above the Curie temperature and in the electric field. The crystal may stabilize with the polarization axis (parallel to the crystallographic c-axis in case of BTO) aligned to the electric field, as discussed above.

[0079] FIG. 7A shows a method 800 fabricating the electro-optic device 100, in accordance with an embodiment of the present invention.

[0080] In a first step, the Pockels material layer 102 is formed. It can be deposited and patterned or a layer transfer can be made, at step 802. The substrate may contain structures suchas heaters. Further, the waveguide 104 is deposited and patterned on the Pockels material structure 102, at step 804. Patterning of waveguide on or as part of the Pockels material structure 102 can be done by patterning BTO, or by integration of other layers that will be patterned, such as SiO2, SiN.

[0081] The one or more one poling electrodes 108 and device drive electrodes 112 are fabricated on either side of the waveguide 104, at step 806.

[0082] In step 808, a first cladding layer 110 is deposited over the waveguide 104.

[0083] In step 810, the heater electrodes above the waveguide are formed.

[0084] Then a second cladding layer is deposited over the heater electrodes, in step 811.

[0085] FIG. 7B is a flowchart of a method 801 of modifying material properties of the electro -optic device 100, in accordance with an embodiment of the present invention.

[0086] The poling voltage is applied to the at least one poling electrode 108, at step 812. At the same time, the heater electrode 106 is energized in order to heat the Pockels material structures such as BTO layer 102 adjacent to the waveguide 104 to an elevated temperature, e.g. the Curie temperature or higher or lower temperatures, at step 814. However, in some examples, the BTO layer is heated or possibly preheated first. The heater electrode 106 is typically subsequently deenergized allowing the BTO layer 102 to cool while maintaining the poling voltage, at step 816. The poling voltage during cooldown may be different than the poling voltage at peak temperature. After the poling step 816, the voltage at the poling or drive electrodes is typically set to operating or storage voltages at step 818.

[0087] It should be noted that there may be already a voltage applied to the poling electrodes prior to the process, in particular when it is implemented as a “refresh” procedure during operation. Also note that the poling and drive electrodes may be the identical pair of electrodes.

[0088] For example, a standard BTO phase shifter is taken, and an integrated heater is disposed close to the BTO phase shifter, such as, above or at the side of the BTO phase shifter drive electrodes, or even use drive electrodes as heaters and / or poling electrodes, as mentioned above.

[0089] Then the BTO phase shifter is heated to temperatures closer to the Curie temperature or a phase transition temperature or even above. Coercive voltage is reduced, or even vanishes, and / or crystallographic structure changes. The electric field is applied with voltages and theheater is ramped down. Poling will happen at lower voltage and / or crystallographic alignment will change within the region of the electric field.

[0090] In one aspect, lower voltages may be used. When operating the chip at lower temperatures, e.g. below room temperature or close to OK, the material properties of the Pockels or any other layer may vary. E.g. the coercive field and / or the crystal structure may vary compared to operation at higher temperatures, e.g. room temperature. In same cases, the coercive field may become very large to make ferroelectric poling difficult and may require to heat up the whole chip / system. Poling at such lower temperatures may be done efficiently by using the integrated heater as discussed previously, and without heating up the whole chip and thus the whole BTO layer 102 and maintaining the electric field during cool down.

[0091] Crystallographic alignment may happen on a device level, which allows other crystallographic orientations (to maximize the Pockels response) compared to the crystallographic orientation imposed by the thermodynamic s / kinetics properties during the BTO layer 102 fabrication.

[0092] While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

Claims

CLAIMSWhat is claimed is:

1. An electro-optic device comprising: a waveguide; a Pockels material structure adjacent to and / or including the waveguide; a heater electrode for heating the Pockels material structure; and at least one poling electrode near the waveguide for establishing an electric field in the Pockels material structure heated by the heater electrode.

2. The electro-optic device of claim 1, wherein materials of the Pockels material structure include at least one of lithium niobate, Barium Titanate (BaTiCh), bariumstrontium titanate ((Ba,Sr)TiO3), Lead zirconate titanate (Pb(Zr,Ti)O3 and / or polymers.

3. The electro-optic device of any of claims 1 or 2, wherein the Pockels material structure can be one or more layers.

4. The electro-optic device of any of claims 1 to 3, further comprising a cladding layer.

5. The electro-optic device of any of claims 1 to 4, wherein the heater electrode is disposed above the waveguide or below the waveguide or next to the waveguide.

6. The electro-optic device of any of claims 1 to 5, wherein at least one poling electrode is configured to be used as heater electrode.

7. The electro-optic device of any of claims 1 to 6, wherein the heater electrode is shared between multiple devices.

8. The electro-optic device of any of claims 1 to 7, wherein heat transfer from the heater electrode to the waveguide is optimized by thermal insulation using etch air grooves, suspended waveguide, or thermally little-conducting materials.

9. A method of modifying material properties of an electro-optic device, the method comprising: apply a poling voltage to poling electrodes and energizing a heater electrode to heat a Pockels material structure associated with a waveguide; anddeenergizing the heater electrode allowing the Pockels material structure to cool while maintaining poling voltage.

10. The method of claim 9, wherein the poling effect is performed in periodic intervals or based on feedback loops, when effective Pockels response drops below a threshold limit.

11. The method of any of claims 9 or 10, wherein the poling voltage and temperature are applied in periodic intervals of seconds, minutes, hours or days or months.

12. The method of any of claims 9 to 11, wherein the electro-optic device is heated slowly from seconds to minutes and kept at high temperature for a specific period.

13. The method of any of claims 9 to 12, wherein the electro-optic device is heated and cooled at a rate between microseconds to milliseconds.

14. The method of any of claims 9 to 13, wherein the electric field is applied constantly or modulated between 3 volts to lOOvolts.

15. The method of any of claims 9 to 14, wherein the heater is operated to modulate the temperature of the Pockels material during the poling procedure.