Persistent memory devices and methods

Abstract

A data processing apparatus (100) is disclosed. The data processing apparatus (100)comprises a persistent memory (110) configured to store data in a plurality of non-volatile memory, NVM, pools (111) addressable by one or more reusable pointers (113). Moreover, the data processing apparatus (100) comprises a CPU (120), wherein the CPU (120) comprises an instruction set architecture, ISA, and wherein the ISA includes one or more instructions for executing one or more operations on the one or more reusable pointers (113).

Description

[0001] Persistent memory devices and methods

[0002] TECHNICAL FIELD

[0003] The present disclosure relates to devices and methods for information processing technology. More specifically, the present disclosure relates to devices and methods for implementing pointers for a persistent memory.

[0004] BACKGROUND

[0005] Persistent memory (PMEM) relates to storing data structures such that they can continue to be accessed using memory instructions or memory application programming interfaces (APIs) even after the end of the process that created or last modified them. PMEMs enable new usages, such as persistent data structures. These allow for example instant recovery. However, as an operating system (OS) usually enforces address randomization, the pointers may have to be offset based or reconstructed. Reconstruction of massive data-structures, i.e. static rebasing is typically relatively slow, complicated and eliminates PMEM fast recovery. Offset based pointers, i.e. dynamic rebasing supports instant recovery but adds high overhead and may be not compatible with standard libraries.

[0006] SUMMARY

[0007] It is an objective of the present disclosure to provide improved persistent memory devices and methods implementing pointers.

[0008] The foregoing and other objectives are achieved by the subject matter of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

[0009] According to a first aspect a data processing apparatus is provided. The data processing apparatus comprises a persistent memory configured to store data in a plurality of non-volatile memory, NVM, pools addressable by one or more reusable pointers. The plurality of NVM pools may be provided as part of a file-backed memory. The one or more reusable pointers may be stored in one or more of the plurality of NVM pools. Moreover, the data processing apparatus comprises a central processing unit, CPU, wherein the CPU comprises an instruction set architecture, ISA, and wherein the ISA includes one or more instructions for executing one or more operations on the one or more reusable pointers. As used herein, the one or more instructions of the ISA for executing one or more operations on the one or more reusable pointers are instructions exclusively for operating on reusable pointers. Providing the ISA of the CPU of the data processing apparatus with one or more instructions for executing one or more operations exclusively on the one or more reusable pointers allows substantially accelerating the usage of reusable pointers, which, in turn, allows using reusable pointers in a mapped memory either in recovery or from a concurrent process. The one or more instructions of the ISA may include a single hardware instruction for dereferencing and validation of a reusable pointer. The one or more instructions of the ISA may include an instruction for hardware-assisted dynamic rebasing of pointers, which allows to almost completely eliminate the overheads of dynamic rebasing by using a dedicated hardware. Multiple processes may use the same reusable pointer simultaneously.

[0010] In a further possible implementation form, each of the one or more reusable pointers comprises a first portion storing an NVM pool identifier for identifying one of the plurality of NVM pools and a second portion storing an offset from the identified NWM pool. Thus, as used herein, a reusable pointer comprises a memory segment identifier and an offset, which upon reference, extracts the memory segment base, adds the offset and loads the referenced value.

[0011] In a further possible implementation form, each of the one or more reusable pointers has a size of 64 bits, wherein the first portion has a size of 16 bits and the second portion has a size of 48 bits.

[0012] In a further possible implementation form, the data processing apparatus further comprises an array of base addresses configured to store base addresses of the plurality of NVM pools and the CPU is configured to determine an access pointer for accessing one of the plurality of NVM pools by adding the offset of the respective reusable pointer from the respective NVM pool to the base address of an NVM heap.

[0013] In a further possible implementation form, the CPU is configured to check whether the access pointer falls within address limits of the respective NVM pool.

[0014] In a further possible implementation form, the one or more instructions for executing the one or more operations on the one or more reusable pointers comprise an instruction for loading data from one of the plurality of NVM pools using the one or more reusable pointers. In a further possible implementation form, the one or more instructions for executing the one or more operations on the one or more reusable pointers comprise an instruction for storing data in one of the plurality of NVM pools using the one or more reusable pointers.

[0015] In a further possible implementation form, the one or more instructions for executing the one or more operations on the one or more reusable pointers comprise an instruction for resolving the address of the one or more reusable pointers.

[0016] According to a second aspect a method is provided for operating a data processing apparatus, in particular a data processing apparatus according to the first aspect. The method comprises the following steps: storing data in a plurality of non-volatile memory, NVM, pools of a persistent memory of the data processing apparatus addressable by one or more reusable pointers; and executing one or more operations on the one or more reusable pointers, wherein the one or more operations on the one or more reusable pointers are defined by one or more instructions of an instruction set architecture, ISA, of the central processing unit, CPU, of the data processing apparatus.

[0017] The method according to the second aspect of the present disclosure can be performed by the data processing apparatus according to the first aspect of the present disclosure. Thus, further features of the method according to the second aspect of the present disclosure result directly from the functionality of the data processing apparatus according to the first aspect of the present disclosure as well as its different implementation forms described above and below.

[0018] According to a third aspect a computer program product is provided, comprising a computer- readable storage medium for storing program code which causes a computer or a processor to perform the computer-implemented data processing method according to the second aspect when the program code is executed by the computer or the processor.

[0019] Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description, drawings, and claims.

[0020] BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In the following, embodiments of the present disclosure are described in more detail with reference to the attached figures and drawings, in which: Fig. 1 shows a schematic diagram illustrating a data processing apparatus according to an embodiment;

[0022] Fig. 2 is a schematic diagram illustrating an exemplary application scenario of a data processing apparatus according to an embodiment;

[0023] Fig. 3 is a schematic diagram illustrating an exemplarily architecture for implementing a reusable pointer;

[0024] Fig. 4a and 4b are schematic diagrams illustrating an exemplarily microarchitecture for implementing a reusable pointer; and

[0025] Fig. 5 is a flow diagram illustrating a method for operating a data processing apparatus according to an embodiment.

[0026] In the following, identical reference signs refer to identical or at least functionally equivalent features.

[0027] DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] In the following description, reference is made to the accompanying figures, which form part of the disclosure, and which show, by way of illustration, specific aspects of embodiments of the present disclosure or specific aspects in which embodiments of the present disclosure may be used. It is understood that embodiments of the present disclosure may be used in other aspects and comprise structural or logical changes not depicted in the figures. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0029] For instance, it is to be understood that a disclosure in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if one or a plurality of specific method steps are described, a corresponding device may include one or a plurality of units, e.g. functional units, to perform the described one or plurality of method steps (e.g. one unit performing the one or plurality of steps, or a plurality of units each performing one or more of the plurality of steps), even if such one or more units are not explicitly described or illustrated in the figures. On the other hand, for example, if a specific apparatus is described based on one or a plurality of units, e.g. functional units, a corresponding method may include one step to perform the functionality of the one or plurality of units (e.g. one step performing the functionality of the one or plurality of units, or a plurality of steps each performing the functionality of one or more of the plurality of units), even if such one or plurality of steps are not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary embodiments and / or aspects described herein may be combined with each other, unless specifically noted otherwise.

[0030] Figure 1 shows a schematic diagram illustrating a data processing apparatus 100 according to an embodiment. In an embodiment, the data processing apparatus 100 may be implemented as a cloud server, mobile device, tablet computer, laptop computer or other type of data processing apparatus. As illustrated in Figure 1 , the data processing apparatus 100 comprises a central processing unit, CPU, 120, and a memory with a persistent memory portion 110 (possibly including further types of memory as well). The CPU 120 may be implemented in hardware and / or software and may comprise digital circuitry, or both analogue and digital circuitry. Digital circuitry may comprise components such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or general-purpose processors. The memory of the data processing apparatus 100 may be configured to store executable program code which, when executed by the CPU 120, causes the data processing apparatus 100 to perform the functions and methods described herein.

[0031] As will be described in more detail below, the persistent memory 110 of the data processing apparatus 100 is configured to store data in a plurality of non-volatile memory, NVM, pools 111 addressable by one or more reusable pointers 113. In an embodiment, the plurality of NVM pools 113 may be provided as part of a file-backed portion of the persistent memory 110. In an embodiment, the one or more reusable pointers 113 may be stored in one or more of the plurality of NVM pools 111. In an embodiment, multiple processes being executed by the CPU 120 may use the same reusable pointer simultaneously.

[0032] The CPU 120 of the data processing apparatus 100 comprises an instruction set architecture, ISA. The ISA includes one or more instructions for executing one or more operations exclusively on the one or more reusable pointers 113. As used herein, a reusable pointer may comprise a memory segment identifier and an offset, which upon reference, extracts the memory segment base, adds the offset and loads the referenced value. Further details about reusable pointers as used herein may be found, for instance, in Kim, Wook-Hee, et al. "PACTree: A High Performance Persistent Range Index Using PAC Guidelines." Proceedings of the ACM SIGOPS 28th Symposium on Operating Systems Principles. 2021 , which is fully incorporated herein by reference.

[0033] Figure 2 is a schematic diagram illustrating an exemplary application scenario of the data processing apparatus 100 according to an embodiment. As illustrated in figure 2, each of the one or more reusable pointers 113 may comprise a first portion 113a storing an NVM pool identifier for identifying one of the plurality of NVM pools 111 and a second portion 113b storing an offset from the identified NWM pool.

[0034] Each of the one or more reusable pointers 113 may have a size of 64 bits. The first portion 113a may have a size of 16 bits and the second portion 113b may have a size of 48 bits. Alternatively, the first portion 113a may have a size of K bits and the second portion 113b may have a size of 64-K bits, where 0<K<64.

[0035] The data processing apparatus 100 may further comprises an array 230 of base addresses configured to store base addresses of the plurality of NVM pools 111 . As illustrated by operator 209 in figure 2, the CPU 120 may be configured to determine an access pointer for accessing one of the plurality of NVM pools 111 by adding the offset of the respective reusable pointer 113 from the respective NVM pool to the base address of an NVM heap.

[0036] The one or more instructions for executing one or more operations on the one or more reusable pointers 113 may comprise an instruction for loading data from one of the plurality of NVM pools 111 using the one or more reusable pointers 113, an instruction for storing data in one of the plurality of NVM pools 111 using the one or more reusable pointers 113 and / or an instruction for resolving the address of the one or more reusable pointers 113.

[0037] The data processing apparatus 100 may be used for storage, on premises or in the cloud, and / or for databases that need to be recoverable in PMEM or concurrently used from different processes that map the same multiple PMEM segments. Furthermore, the data processing apparatus 100 may be implemented for mobile applications that for example need immediate restart and distributed systems that map for example pools through PCI I UBus I XSL interconnects. The data processing apparatus 100 may be implemented in operating systems and file systems.

[0038] In the example of PACTree, the first program code 201 may for example comprise the following code: pactree / include / pptr.h template <typename T> class pptr { public: pptr(int poolld, unsigned long offset) { rawPtr = ((unsigned long)poolld) « 48 | offset;

[0039] }

[0040] A standard operator 203 may for example be described by the following code:

[0041] T *operator->() { int poolld = (rawPtr&MASK_POOL) » 48; void *baseAddr = PMem::getBaseOf(poolld); unsigned long offset = rawPtr & MASK; return (T *)((unsigned long)baseAddr + offset);

[0042] }

[0043] The standard operator 203 is in particular not optimized for dereferencing. A replacement operator 205 of the standard operator 203 in order to realize the use of the reusable pointer 113 may be for example be described by the following code:

[0044] T *operator->() { return (T *) intrinsic_load_rp(rawPtr, PMem:baseAddresses);

[0045] }

[0046] The first program code 201 may for example further comprise the following code: private: unsigned long rawPtr; / / 16b + 48b 11 nvm

[0047] };

[0048] A second program code 207 may for example further comprise the following code: pactree / include / pmem.h

[0049] #define MASK 0x8000FFFFFFFFFFFF

[0050] #define MASK_POOL 0x7FFFFFFFFFFFFFFF class PMem { private: static void *baseAddresses[6]; / / dram public: static void *getBaseOf(int poolld) { return baseAddresses[poolld];

[0051] }

[0052] };

[0053] The reusable pointer 113 can be used as a compact pointer for multiple persistent memory pools for improving the performance of near-memory processing modules. The hardware implementation can improve performance (latency and throughput) for various HPC and analytics workloads.

[0054] Figure 3 is a schematic diagram illustrating an exemplarily architecture 300 for implementing the reusable pointer 113. As will be appreciated, an implementation of the reusable pointer 113 is not limited to the architecture 300 shown in figure 3.

[0055] As illustrated in figure 3, the architecture 300 may comprise adjusted and / or new instructions for the ISA of the CPU 120 of the processing apparatus 100 for processing the reusable pointer 113. In the following exemplarily instructions “$1” denotes the destination register or value to be stored (for stores), “$2” denotes the register holding the reusable pointer 113 and “$3” holds a pool array pointer (PAP, also referred to as access pointer) of the array 130.

[0056] Instructions for loading through the reusable pointer 113 may for example comprise the instruction operand “LDR_RP $1 , $2, $3” and a corresponding system register “LDR_RP $1 , $2”.

[0057] Instructions for storing through the reusable pointer 113 may for example comprise the instruction operand “STR_RP $1 , $2, $3” and a corresponding system register “STR_RP $1 , $2”.

[0058] Instructions for resolving the address for the reusable pointer 113 may for example comprise the instruction operand “RP_VA $1 , $2, $3” and a corresponding system register “RP_VA $1 , $2”. The CPU 120 may perform loading and / or storing through the reusable pointer 113 or by address calculation for the reusable pointer 113 according to the ISA. As described above, the ISA may further comprise instructions for dereferencing the reusable pointer 113. As will be described in more detail below, the ISA may further comprise instructions for safety checks, for example if the VA is within pool limits. An exemplarily check may be described by the condition “&& !=0” and may lead to an exception in case of violation.

[0059] For a T ranslation Lookaside Buffer (TLB) invalidation of the reusable pointer 111 , the PA may be supplied as an operand for the loading and / or storing instructions. Additionally or alternatively, the instructions may involve writing to a system register for the PAP. This can increase the application context and may require corresponding changes in the operating system. Additionally or alternatively, a 3rdoperand may be used on loading and / or storing instructions for an additional offset.

[0060] Figures 4a and 4b are schematic diagrams illustrating an exemplarily microarchitecture 400 for implementing the reusable pointer 113. As will be appreciated, an implementation of the reusable pointer 113 is not limited to the microarchitecture 400 shown in figures 4a and 4b.

[0061] As illustrated by operator 211 in figures 4a and 4b, the CPU 120 may be configured to check whether the access pointer, i.e. PAP falls within address limits of the respective NVM pool.

[0062] As illustrated in figures 4a and 4b, a pool array cache 230’ may be used by the CPU 120 to cache the frequently used pool IDs’ base and size, for example similar to a TLB like cache. Corresponding to the array 230, the pool array cache 230’ may map pool-id to its base and size.

[0063] Microarchitecture behaviour alternatives for software that uses multiple pool arrays may add the PAP to the ID in the pool array cache 230’ and for a further more simple implementation to flush the pool array cache 230’ on any PAP change, for example typically infrequent.

[0064] On a pool-array-cache miss, the CPU 120 may perform a load to the array 230 in the persistent memory 110 and fill the pool array cache 230’. In a typical usage, the pool array cache 230’ may have a very high hit rate and provide near regular C pointer performance.

[0065] As further illustrated in figure 4b, the CPU 120 may invalidate, i.e. flush the cached array and / or the pool array cache 230’ on any TLB software invalidation instruction, e.g., context switches, virtual memory remapping. The TLB of the array and / or the pool array cache 230’ may be coherent in a first state and if not coherent in a second state, a software implemented by the CPU 120 may be able to trigger the TLB invalidation of the array 230 and / or the pool array cache 230’.

[0066] Alternatively, a dedicated instruction may be used to write to a system register, for example in a load instruction by using 0 as pool array pointer.

[0067] As will be appreciated, the features of the embodiments disclosed above and below can be combined in any way. In particular the data processing apparatus 100 can be implemented with the system register or the third parameter and with or without the TLB. Additionally or alternatively, the data processing apparatus 100 can be implemented with the safety check, i.e. the ISA may check that the offset falls inside the pool. This can be important, for instance, for PM EM which is less protected by the operating system and where corruptions may survive restarts.

[0068] Advantageously, the ISA implemented by the CPU 120 of the data processing apparatus 100 according to an embodiment can by up to three times accelerate the usage of reusable pointers 113 which for example allows reusability of pointers in the mapped persistent memory 110 either in recovery or from a concurrent process. Moreover, by means of the ISA, the CPU 120 can support thousands of reusable pools which is not possible with traditional segments, almost completely eliminates the overheads of dynamic rebasing and can provide the reusable pointer 113 at the performance and simplicity of standard C / C++ pointers.

[0069] Figure 5 is a flow diagram illustrating a method 500 for operating the data processing apparatus 100 according to an embodiment.

[0070] The method 500 comprises storing 501 data in a plurality of non-volatile memory, NVM, pools 111a of a persistent memory 110 of the data processing apparatus 100 addressable by one or more reusable pointers 113.

[0071] The method 500 further comprises executing 503 one or more operations on the one or more reusable pointers 113, wherein the one or more operations on the one or more reusable pointers 113 are defined by one or more instructions of an instruction set architecture, ISA, of a central processing unit, CPU 120, of the data processing apparatus 100. As the method 500 can be implemented by the data processing apparatus 100, further features of the method 500 result directly from the functionality of the data processing apparatus 100 and its different embodiments described above and below.

[0072] The person skilled in the art will understand that the "blocks" ("units") of the various figures (method and apparatus) represent or describe functionalities of embodiments of the present disclosure (rather than necessarily individual "units" in hardware or software) and thus describe equally functions or features of apparatus embodiments as well as method embodiments (unit = step).

[0073] In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus, and method may be implemented in other manners. The described embodiment of an apparatus is merely exemplary. For example, the unit division is merely logical function division and may be another division in an actual implementation. For example, a plurality of units or components may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections may be implemented by using some interfaces. The indirect couplings or communication connections between the apparatuses or units may be implemented in electronic, mechanical, or other forms.

[0074] The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one position, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

[0075] In addition, functional units in the embodiments disclosed herein may be integrated into one processing unit, or each of the units may exist alone physically, or two or more units are integrated into one unit.

Claims

CLAIMS1. A data processing apparatus (100), comprising: a persistent memory (110) configured to store data in a plurality of non-volatile memory, NVM, pools (111) addressable by one or more reusable pointers (113); and a central processing unit, CPU (120), wherein the CPU (120) comprises an instruction set architecture, ISA, and wherein the ISA includes one or more instructions for executing one or more operations on the one or more reusable pointers (113).

2. The data processing apparatus (100) of claim 1 , wherein each of the one or more reusable pointers (113) comprises a first portion (113a) storing an NVM pool identifier for identifying one of the plurality of NVM pools (111) and a second portion (113b) storing an offset from the identified NWM pool.

3. The data processing apparatus (100) of claim 2, wherein each of the one or more reusable pointers (113) has a size of 64 bits, wherein the first portion (113a) has a size of 16 bits and the second portion (113b) has a size of 48 bits.

4. The data processing apparatus (100) of claim 2 or 3, wherein the data processing apparatus (100) further comprises an array (230) of base addresses configured to store base addresses of the plurality of NVM pools (111) and wherein the CPU (120) is configured to determine an access pointer for accessing one of the plurality of NVM pools (111) by adding the offset of the respective reusable pointer (113) from the respective NVM pool to the base address of an NVM heap.

5. The data processing apparatus (100) of claim 4, wherein the CPU (120) is configured to check whether the access pointer falls within address limits of the respective NVM pool.

6. The data processing apparatus (100) of any one of the preceding claims, wherein the one or more instructions for executing one or more operations on the one or more reusable pointers (113) comprise an instruction for loading data from one of the plurality of NVM pools (111) using the one or more reusable pointers (113).

7. The data processing apparatus (100) of any one of the preceding claims, wherein the one or more instructions for executing one or more operations on the one or more reusable pointers (113) comprise an instruction for storing data in one of the plurality of NVM pools (111) using the one or more reusable pointers (113).

8. The data processing apparatus (100) of any one of the preceding claims, wherein the one or more instructions for executing one or more operations on the one or more reusable pointers (113) comprise an instruction for resolving the address of the one or more reusable pointers (113).

9. A method (500) for operating a data processing apparatus (100), wherein the method (500) comprises: storing (501) data in a plurality of non-volatile memory, NVM, pools (111a) of a persistent memory (110) of the data processing apparatus (100) addressable by one or more reusable pointers (113); and executing (503) one or more operations on the one or more reusable pointers (113), wherein the one or more operations on the one or more reusable pointers (113) are defined by one or more instructions of an instruction set architecture, ISA, of a central processing unit, CPU (120), of the data processing apparatus (100).

10. A computer program product comprising a computer-readable storage medium for storing program code which causes a computer or a processor to perform the method (500) of claim 9, when the program code is executed by the computer or the processor.

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