Method for manufacturing a stack comprising an insulating layer

Abstract

The invention relates to a method for manufacturing a stack, which includes providing an initial stack having a base substrate based on a first material and a first insulating layer having an array of walls made of a first insulating material separated by trenches, filling the trenches with a second insulating material, thereby forming a second insulating layer, and forming a semiconductor film on the second insulating layer.

Description

[0001] “Method for manufacturing a stack comprising an insulating layer”

[0002] TECHNICAL FIELD OF THE INVENTION

[0003] The present invention relates to the manufacture of resistive layers and more particularly to the manufacture of substrates comprising a semiconductor layer overlying an insulating layer such as SOI substrates (from the English "Silicon On Insulator"). It finds, for example, a particularly advantageous application in the field of radiofrequency (RF) components.

[0004] STATE OF THE ART

[0005] To improve the performance of microelectronic components, and more specifically RF components, a major area of ​​development concerns the improvement of SOI-type substrates. In particular, to promote signal integrity, it is common to provide a highly resistive base (or pedestal) and to insert a free carrier trapping layer between the base and the buried oxide, commonly called BOX (from the English "Burned Oxide"). The function of this trapping layer is to form a quasi-insulator. In particular, it has a very high electrical resistivity that does not vary with polarization (Fermi level locking).

[0006] Furthermore, in the field of radio frequencies, it is desirable to have a substrate allowing the integrity of the signals to be independent of the operating temperature of the device, for example to produce communicating objects subjected to variable temperatures over a wide range. For example, certain devices can be subjected to temperatures varying from -75°C to 200°C.

[0007] Several types of trapping layers have been explored in the past.

[0008] The most common trapping layers are made of undoped polycrystalline silicon (polySi). The numerous defects present at the grain boundaries of this material ensure the trapping function, which results in a resistivity of up to 10kQ.cm, or 100 Qm. The performance of this type of trapping layer has been studied in particular in the document "RF Performance of a Commercial SOI Technology Transferred Onto a Passivated HR Silicon Substrate", Dimitri Lederer and Jean-Pierre Raskin, IEEE Trans. Electr. Dev. Vol. 55, No. 7, July 2008. However, this solution does not offer sufficient stability of the electrical resistivity in the face of temperature variations, which degrades the performance of the device. The electrical resistivity of the assembly consisting of the highly resistive silicon base and the polySi trapping layer varies greatly with temperature.

[0009] Other trapping layers are made of porous silicon. The use of this insulating material makes it possible to obtain linearity that is weakly dependent on the surrounding temperature for certain porosification conditions. These conditions were investigated in the document "Small - and Large - Signal Performance Up To 175 °C of Low-Cost Porous Silicon Substrate for RF Applications", M. Rack et al., IEEE Trans. Electr. Dev. 2018. However, this material has two major drawbacks: a high thermal resistivity limiting the dissipated power and a low mechanical rigidity complicating its integration into an SOI substrate and its use in a foundry.

[0010] A third solution has been disclosed in particular in document US 7,067,890 B2. It consists of the formation in a silicon substrate of a network of walls 2 separated by trenches 3 (figure 9A) then the oxidation of these walls 2 until their coalescence (figure 9B). The document defines an optimal relationship linking the width l t trenches 3 to width l m walls: 0.46*l t =0.53l m This process makes it possible to obtain a very thick oxide locally (of the order of 10 pm=10' 5m). The mechanical strength of the assembly thus obtained is better than that of the porous silicon trapping layers. However, the thermal conductivity of the oxide is of the same order (approximately 1 W / mK) as that of the porous silicon (approximately 0.5 W / mK), the latter two being low compared to that of silicon (close to 140 W / mK). The same power dissipation problem described for the porous silicon layers therefore also arises in the context of this solution. Furthermore, the production of the thick oxide by the process described in document US 7,067,890 B2 is extremely sensitive to variations in the dimensions of the walls 2 and the trenches 3. If the ratio l t / L m is greater than 0.53 / 0.46, there will remain empty spaces in trenches 3 after total oxidation of walls 2, which is unfavorable for heat evacuation. Conversely, if the ratio l t / L mis less than 0.53 / 0.46, trenches 3 will be filled before the walls are completely oxidized, leaving regions of unoxidized silicon in the layer, to the detriment of RF performance. In addition, this solution does not have sufficient stability in the face of temperature variations.

[0011] The present invention therefore aims to propose a simple solution making it possible to limit at least some of the drawbacks of known solutions. For example, the present invention therefore aims to propose a simple solution making it possible to obtain a buried insulating layer having good mechanical strength, satisfactory thermal resistivity and limited contrast in thermal expansion with the substrate.

[0012] Other objects, features, and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated.

[0013] SUMMARY OF THE INVENTION

[0014] To achieve the above-mentioned objectives, a first aspect of the invention relates to a method for manufacturing a stack comprising the following step: a. Providing at least one initial stack comprising: i. a base substrate based on a base material having a so-called base thermal expansion coefficient a, ii. a first insulating layer overlying the base substrate, the first insulating layer being based on a first insulating material, the first insulating material having a first thermal conductivity λi and a first thermal expansion coefficient ai, the first insulating layer comprising a network of trenches.

[0015] The method is characterized in that it also comprises at least the following steps: b. Filling the trenches with a second insulating material having a second thermal conductivity λ2 and a second coefficient of expansion θ2, thereby forming a second insulating layer, the second thermal conductivity λ2 being different from the first thermal conductivity λ1, α1 and θ2 being greater than 0.3 ppm / K, and c. Forming a semiconductor film above the second insulating layer.

[0016] The buried insulating layer here consists in particular of the first insulating layer and the second insulating layer.

[0017] The use of a second insulating material makes it possible not to be limited to the values ​​of thermal conductivity and / or electrical resistivity and / or thermal expansion that can be offered by the materials for which it is possible to opt for the base substrate. In particular, using a second insulating material with a higher thermal conductivity than that of the first insulating material makes it possible to optimize the power that can be dissipated by the buried insulating layer. It is also possible to use materials whose average coefficients of thermal expansion are close to that of the base material. In this sense, using several materials for the production of the buried insulating layer makes it possible to achieve physical properties that would be impossible to achieve by limiting oneself to a single material that must simultaneously fulfill the role of base substrate, electrical insulator and thermal conductor.

[0018] The solution which would consist of depositing a thick layer of an insulator having a thermal conductivity higher than that of the base substrate, for example silicon nitride (SisN^, would be limited by the difference in coefficient of thermal expansion (CTE) between the silicon base substrate and the nitride layer (and most insulators with high thermal conductivity) which would cause unacceptable deformations during the heat treatment steps linked to the manufacture or use of the substrates.

[0019] In addition, the wall network structure gives the layer good mechanical strength and thus minimizes deformation of the layer compared to a continuous layer of a single material. This advantage is particularly interesting when the process is used to form a full-plate insulating layer. In this context, this results in a lower deflection than when the buried insulating layer is made of a conventional continuous layer.

[0020] Another subject of the invention relates to a microelectronic device comprising a stack of layers, said stack comprising, from a lower face of the stack: a. a base substrate, b. a buried insulating layer comprising: i. a first insulating layer based on a first insulating material and comprising a plurality of walls, the first insulating material having a first thermal conductivity λ1 and a first coefficient of expansion ai, ii. a second insulating layer based on a second insulating material and extending at least in the trenches separating the walls, the second insulating material having a second thermal conductivity λ2 and a second coefficient of expansion λ2, the second thermal conductivity λ2 being different from the first thermal conductivity λ1, and with preferably 0.6 < l(O2+ai) / 2al < 1.7, ai and λ2 being greater than 0.3 ppm / K, c. a semiconductor film.

[0021] A microelectronic device is any type of device made using microelectronics. These devices include, in addition to devices for purely electronic purposes, micromechanical or electromechanical devices (MEMS, NEMS, etc.) as well as optical or optoelectronic devices (MO EM S, etc.).

[0022] It may be a device intended to provide an electronic, optical, mechanical, etc. function. It may also be an intermediate product solely intended for the production of another microelectronic device. The method and device according to the present invention are particularly advantageous for forming a device for radiofrequency (RF) applications.

[0023] BRIEF DESCRIPTION OF THE FIGURES

[0024] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0025] Figures 1A to 1L illustrate the steps of a first example of a method for forming a stack according to one of the embodiments of the invention. Figures 1A to 1E illustrate more particularly the steps for forming an initial stack shown in Figure 1E, from which other steps are carried out to arrive at a stack according to the invention. Figure 1A illustrates the provision of a substrate.

[0026] Figure 1B illustrates the deposition of a lithography mask on the substrate.

[0027] Figure 1C depicts the formation of trenches in the substrate through the lithography mask, thereby forming a network of walls in the substrate.

[0028] Figure 1D illustrates the removal of the lithography mask.

[0029] Figure 1 E illustrates a step in the transformation of the material constituting the walls into a first insulator, thus forming a first insulating layer.

[0030] Figures 1F to 1J illustrate the steps of forming the initial stack shown in Figure 1J, from which further steps are performed to achieve a stack according to the invention. Figure 1F illustrates the provision of a base substrate.

[0031] Figure 1 F illustrates the formation of a first initial insulating layer on the base substrate.

[0032] Figure 1G illustrates the deposition of a lithography mask on the first initial insulating layer.

[0033] Figure 11 shows the formation of trenches in the first initial insulating layer through the lithography mask, thus forming a network of walls in the first initial insulating layer.

[0034] Figure 1J illustrates the removal of the lithography mask.

[0035] Figure 1K shows a step of filling the trenches with a second insulating material, thus forming a second insulating layer.

[0036] Figure 1 L illustrates a step of forming a semiconductor film on the first insulating layer and the second insulating layer.

[0037] Figures 2A to 2E illustrate another example of the production of trenches in the base substrate using a nanoimprinting technique. Figure 2A represents the deposition of a printable resin layer on the base substrate.

[0038] Figure 2B illustrates the printing of a pattern onto the printable resin using a mold by pressing the mold onto the printable resin and UV curing.

[0039] Figure 2C illustrates mold removal.

[0040] Figure 2D illustrates the etching of certain areas of the printable resin layer to form the desired etch mask.

[0041] Figure 2E shows the formation of trenches in the base substrate through the etch mask.

[0042] Figures 3A to 3D illustrate another example of the production of trenches in the base substrate using a block copolymer self-assembly technique. Figure 3A represents the deposition of a layer of copolymers on the base substrate. The mixture of stripes and dotted lines illustrates the fact that this layer initially comprises two mixed and unordered copolymers.

[0043] Figure 3B illustrates a processing step for ordering the copolymers by alternating blocks each comprising only one of the two copolymers.

[0044] Figure 3C illustrates the removal of one of the two copolymers selectively from the other to form an etch mask. Figure 3D shows the formation of trenches in the base substrate through the etch mask.

[0045] Figure 4 represents an optional step, according to one of the embodiments of the invention, of depositing a continuous layer based on the second insulating material on the second insulating layer and the first insulating layer.

[0046] Figure 5 represents an optional step, according to one of the embodiments of the invention, of depositing a third insulating layer on the continuous layer based on the second insulating material.

[0047] Figures 6A to 6D represent another example of the semiconductor film formation step. Figure 6A represents the implantation in a semiconductor layer of a layer rich in gaseous elements.

[0048] Figure 6B illustrates the bonding of the semiconductor layer to the stack.

[0049] Figure 6C represents a step of cleaving the semiconductor layer at the level of the layer rich in gaseous elements so as to form a semiconductor film.

[0050] Figure 6D illustrates the stack obtained after the cleavage step of the semiconductor layer.

[0051] Figure 7 illustrates a stack according to one of the embodiments of the invention, in which the semiconductor film is deposited directly on the second insulating layer.

[0052] Figure 8 illustrates a stack according to one of the embodiments of the invention, in which the semiconductor film is deposited directly on the continuous layer based on the second insulating material.

[0053] Figures 9A and 9B illustrate a method for obtaining a thick oxide layer according to the prior art.

[0054] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, the thicknesses of the different layers and films are not representative of reality.

[0055] DETAILED DESCRIPTION OF THE INVENTION

[0056] Before commencing a detailed review of embodiments of the invention, optional features which may optionally be used in combination or alternatively are set out below:

[0057] Preferably, the first insulating layer consists entirely of the first insulating material.

[0058] Advantageously, the first insulating material and the second insulating material are each distinct from the base material.

[0059] After transformation, the trenches extend into the thickness of the first insulating layer.

[0060] Preferably, the first insulating layer has a lower face which is entirely located under a bottom of the trenches.

[0061] According to an advantageous example, 0 < 2*1(02-01)1 / (02+01) < 1.8 and 0 < I (o-oi)| / o < 2.1. In this way, the coefficients of thermal expansion of the first insulating layer and the second insulating layer on the one hand and of the first insulating layer and the base substrate on the other hand have values ​​quite close to each other. This makes it possible to avoid too large differences in coefficients of thermal expansion between materials at the base of contacting layers. This makes it possible to reduce or even avoid mechanical deformations that can occur during temperature variations. This gives greater robustness and better structural quality to the stack.

[0062] For example, 0.6 < l(O2+ai) / 2al < 1.7. This also ensures a certain proximity between the thermal expansion coefficient values ​​of the different materials in the stack. This reduces or even prevents mechanical deformations that can occur during temperature variations. This gives the stack greater robustness and better structural quality.

[0063] For example, ki < l(À2- Ài) / Ài I , with 0.3 < ki.

[0064] According to one embodiment, the second thermal conductivity Δ2 is strictly greater than the first thermal conductivity Δ1 (Δ2>Δi).

[0065] According to one example, one of the first coefficient of thermal expansion ai and the second coefficient of thermal expansion 02 is greater than a and / or the other of the first coefficient of thermal expansion ai and the second coefficient of thermal expansion 02 is less than a.

[0066] According to one example, the first insulating material has a first Young's modulus E1 and the second insulating material has a second Young's modulus E2, with EI^E2, preferably with rm < l(E2- Ei) / Ei I , with 0.03 < rm, E1 and E2 being greater than 50 GPa.

[0067] According to one example, the step of providing the initial stack comprises the following steps: a. Providing at least one initial substrate based on, preferably made of, the base material and having an upper face, b. Forming in the initial substrate and from the upper face a network of initial trenches, the base material remaining between the trenches forming initial walls, c. Transforming at least the base material on at least a portion of the initial substrate comprising the initial walls of the initial network into the first insulating material, thereby forming the first insulating layer comprising the network of walls separated by the trenches.

[0068] In one example, transforming at least the base material on at least a portion of the initial substrate comprises oxidizing the base material separating the trenches from each other.

[0069] In one example, the step of forming the initial network of initial walls comprises implementing at least one technique among lithography, nanoimprinting, self-assembly of block copolymers and laser processing.

[0070] According to one embodiment, the step of providing the initial stack comprises the following steps: a. Providing the base substrate, b. Forming a first initial insulating layer overlying the base substrate, the first initial insulating layer being based on the first insulating material, c. Forming the network of trenches in the first initial insulating layer, thereby forming the first insulating layer.

[0071] In one example, the step of forming the wall network comprises implementing at least one of lithography, nanoimprinting, block copolymer self-assembly, and laser processing.

[0072] According to one embodiment, the method further comprises, before the step of forming the semiconductor film, a step of continuously forming a continuous layer based on the second insulating material, and preferably made of the second insulating material, directly covering the second insulating layer. According to one example, the continuous layer is insulating. The continuous layer preferably also covers the walls separating the trenches. The continuous layer may optionally be formed at the same time as the second insulating layer, for example during a deposition, preferably conformal, taking place simultaneously on the sides and the tops of the walls separating the trenches. This optional layer improves the electrical resistivity of the stack. It also makes it possible to ensure good solidarity of the different layers included in the buried insulating layer. According to one example, the continuous layer may be described as a fourth layer.

[0073] According to one embodiment, the method further comprises a step of forming a third insulating layer under the semiconductor film. The third insulating layer thus preferably covers the walls separating the trenches. This optional layer improves the electrical resistivity of the stack. It can also be useful for the purpose of planarization of the buried insulating layer and the quality of the interface with the semiconductor film.

[0074] According to one embodiment, the walls separating the trenches have a wall width l m ' and the trenches have a trench width l t ', and in which the ratio It' / lm' is between 0.3 and 3, preferably between 0.5 and 1.5. The widths l t ' and l m ' are preferably chosen such that 0.7 < l(lt'*O2+ l m '*ai) / ((lt'+ l m ')*a)l < 1 ,3.

[0075] In one example, the trenches have a depth e t ', with e t ' between 5 pm and 20 pm, preferably between 8 pm and 15 pm.

[0076] According to one example, the m ' is between 0.5 pm and 4 pm, preferably between 0.8 pm and 1.5 pm.

[0077] According to one example, the t ' is between 0.25 pm and 4 pm, preferably between 0.4 pm and 0.8 pm.

[0078] According to one example, the second insulating material is made or based on one of ALOs, AIN, SiC, Si3N4, BeO, a silicon oxynitride and BN.

[0079] According to one example, the semiconductor film is based on one of Si and its alloys, Ge and its alloys, SiC, InAs, InSb, InGaAs, GaN, AIGaN, InGaN, GaAs and InP.

[0080] According to one example, the third insulating layer is based on one of SiO2, AlN, HFSiON and Al2O3.

[0081] According to one embodiment of the device, the buried insulating layer further comprises a continuous layer based on the second insulating material directly covering the second insulating layer.

[0082] According to one embodiment, the buried insulating layer further comprises a third insulating layer overlying the second insulating layer.

[0083] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition, transfer, bonding, assembly or application of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0084] A layer can also be composed of several sub-layers of the same material or of different materials.

[0085] A substrate, a layer, a device, "based" on a material M, is understood to mean a substrate, a layer, a device comprising this material M only or this material M and possibly other materials, for example alloying elements, impurities or doping elements. Thus a material based on a III-N material may comprise a III-N material with added dopants. Similarly, a GaN-based layer typically comprises GaN and alloys of AIGaN or InGaN.

[0086] The term "III-V material" refers to a semiconductor composed of one or more elements from column III and column V of Mendeleev's periodic table. Elements in column III include boron, gallium, aluminum, and indium. Column V contains, for example, nitrogen, arsenic, antimony, and phosphorus.

[0087] A material whose electrical resistivity is greater than or equal to 1 kilo (103 ) ohms meter (1 k Qm), preferably greater than or equal to 10 k Qm.

[0088] The abbreviation "ppm" stands for "parts per million." This term means the fraction worth 10 -6 , or one millionth.

[0089] The term "selective etching with respect to" or "etching exhibiting selectivity with respect to" means an etching configured to remove a material A or a layer A with respect to a material B or a layer B, and exhibiting an etching rate of the material A greater than the etching rate of the material B. The selectivity is the ratio between the etching rate of the material A and the etching rate of the material B. The selectivity between A and B is denoted SA:B.

[0090] The expression "stability of electrical resistivity in temperature" (or "stability of the applied electric field") can correspond to a maintenance of the resistivity above a given threshold, for example 10 kQ.cm, independently of the temperature (or of the applied electric field).

[0091] A reference frame, preferably orthonormal, comprising the x, y, z axes is represented in figure 1A. This reference frame is applicable by extension to the other figures.

[0092] In this patent application, we will preferably speak of thickness for a layer and height for a structure or device. The thickness is taken along a direction normal to the main extension plane of the layer, and the height is taken perpendicular to the XY base plane. Thus, a layer typically has a thickness along z, when it extends mainly along an XY plane, and a projecting element, for example an isolation trench, has a height along z. The relative terms "on", "under", "underlying" preferably refer to positions taken along the z direction.

[0093] In the context of the present invention, the term "network" covers all distributions of walls separated by trenches. The network may have a constant pitch or not. It may extend over the entire surface of the first insulating layer or only over a part of its surface.

[0094] The steps of the method as claimed are understood in the broad sense and may optionally be carried out in several sub-steps.

[0095] An example of a production method will now be described with reference to FIGS. 1A to 1L. This method makes it possible to obtain the stack 1 illustrated in FIG. 1L, comprising a base substrate 100', an insulating layer 1000, such as a buried oxide, and a semiconductor film 400'. The insulating layer 1000 comprises in this embodiment a first insulating layer 130', itself comprising a plurality of walls 150' separated by trenches 120', and a second insulating layer 200.

[0096] This production method consists first of all in providing an initial stack as illustrated in figures 1 E and 1 J. This stack comprises in particular a base substrate 100' based on a first material, referred to as the base material, and a first insulating layer 130' comprising a network 150' of trenches 120' separated by walls 110'. Two embodiments for producing this initial stack will now be described.

[0097] The first of these two embodiments will first be described with reference to Figures 1A to 1E. As illustrated in Figure 1A, in this embodiment, a first step consists of providing a substrate 100 based on the base material, which can be transformed into an insulating material called the first insulating material. Preferably, the substrate 100 is based on monocrystalline silicon or polycrystalline silicon. Generally, any semiconductor that can become an insulator by oxidation is possible. It is also possible to opt for a material that can be transformed into an insulator by ion bombardment. The possible materials are thus very numerous, which in particular makes it possible to have the possibility of using low-cost materials.

[0098] The initial substrate 100 has an upper face 101 and a lower face 102 both extending mainly in planes parallel to the XY plane of the orthogonal reference frame. It has a thickness e o in the Z direction. For example, e o is between 300 pm and 1000 pm.

[0099] A second step of this embodiment consists of forming in the initial substrate 100 an initial network 150 of initial walls 110 separated by initial trenches 120, as illustrated in FIG. 1 D. The initial walls 110 have a width l m measured along the X direction. The initial trenches 120 have a width l t measured along the X direction and a depth e t measured along the Z direction. The initial walls 110 thus extend into the initial substrate 100 from its upper face 101 and up to a depth e t measured along the Z direction from the upper face 101.

[0100] The initial network 150 of initial walls 110 and initial trenches 120 can be produced from the entire upper face 101 of the initial substrate 100. It can also be produced from only a part of this upper face 101. In a stack 1 manufactured according to this latter embodiment, the parts of the upper face 101 devoid of initial trenches 120 can be used to electrically connect the semiconductor film 400' to the substrate 100.

[0101] The initial walls 110 and initial trenches 120 can be formed in different ways. It is for example possible to use a lithography technique such as photolithography. In this embodiment, a layer of photosensitive resin is deposited on the upper face 101 of the initial substrate 100. Openings are then made in the photosensitive resin by exposure through a photolithography mask and then development. These openings are underlying the initial trenches 120 that it is desired to form. At the scale of the stack 1, they typically form parallel lines extending mainly in the Y direction. On the other hand, during the integration of the stack 1 in a microelectronic device, these lines advantageously do not have a preferential direction at the scale of the device.In this way, the thermal expansion coefficient of the insulating layer 1000 is substantially that of the base substrate 100' in all directions of the plane. The photosensitive resin layer thus etched forms an etching mask 10 as shown in FIG. 1 B. The initial trenches 120 are then formed by etching through the etching mask 10. It is for example possible, if the base substrate 100 is based on monocrystalline or polycrystalline silicon, to implement a Bosch process, favorable to the production of structures with high form factors such as the walls 110. This process alternates a plasma etching based on sulfur hexafluoride (SFe) and a passivation based on fluorocarbon chemistry (C4F8, C2F6, CF4 or CHFs-Ar).

[0102] It is also possible, but not obligatory, to deposit a masking layer between the upper face 101 of the substrate 100 and the photosensitive resin layer. The masking layer is typically based on silicon dioxide. It preferably has a thickness greater than 0.5 μm, preferably greater than 0.8 μm. In this embodiment, after the development of the photosensitive resin, an etching is carried out throughout its thickness of the masking layer through the photosensitive resin layer, so as to obtain a hard mask overlying the initial walls 110 that it is desired to form. The etching of the hard mask and the etching of the initial trenches 120 can be carried out successively by different methods or, advantageously, during the same etching process. The Bosch process previously described can in particular be used for the etching of the silicon dioxide hard mask at the same time as for the etching of the initial trenches 120.

[0103] In all cases, the etching of the trenches can be followed by a step of removing potential etching residues.

[0104] It should be noted that the etching mask 10 can also be formed by other lithography techniques such as electronic lithography, double exposure lithography or even extreme ultraviolet lithography.

[0105] Furthermore, the initial trenches 120 can be made in ways other than lithography.

[0106] For example, the initial trench formation step may include a nanoimprinting step. This embodiment is illustrated in Figures 2A-2E. Figure 2A shows the deposition of a printable resin layer 20 on the upper face 101 of the initial substrate 00. This printable resin layer 20 has an upper face 21 and a lower face 22 extending mainly in the XY plane of the orthogonal reference frame, the lower face 22 being in contact with the upper face 101 of the initial substrate 00. Figure 2B illustrates a step of printing a pattern on the printable resin layer 20 using a mold 25. The mold 25 is pressed against the upper face 21 of the printable resin layer 20, which also undergoes an ultraviolet (UV) treatment, shown in Figure 2B by the set of parallel arrows pointing towards the upper face 21, so as to set the printable resin according to the desired pattern.The printable resin layer 20 is then etched so as to expose certain areas only of the upper face 101 of the initial substrate 100. Finally, the initial trenches 120 are formed in the base substrate by etching through the remaining regions of the printable resin layer 20.

[0107] Another alternative to lithography is illustrated in Figures 3A to 3D. A layer of copolymers 30 is first deposited on the upper face 101 of the initial substrate 100 (Figure 3A). This layer 30 comprises a mixture of a first polymer and a second polymer that are initially unordered. As illustrated in Figure 3B, the layer of copolymers 30 then undergoes a treatment making it possible to order the first polymer and the second polymer in an alternation between blocks of first polymer 31 and blocks of second polymer 32. One of the two polymers is then selectively removed from the other, as illustrated in Figure 3C, so as to expose certain areas of the upper face 101 of the initial substrate 100. An etching is then carried out through the remaining polymer blocks so as to form the initial trenches 120.Lithography can also be replaced by the deposition of a layer on the initial substrate 100 followed by laser treatment of this layer so as to form a network of wrinkles which can then be etched so as to again form an etching mask.

[0108] One of the advantages of the last three embodiments cited for the formation of the network 150 of initial walls 110 and initial trenches 120 is that they do not require the use of lithography equipment. In all cases, the etching of the initial trenches 120 can be carried out by any of the etching methods mentioned previously.

[0109] A third step of this embodiment is represented by the transition from Figure 1 D to Figure 1 E. This involves the transformation of the base material constituting the initial walls 110, and possibly a portion of the initial substrate 100 directly underlying the initial walls 110, into a first insulator. This transformation makes it possible to form a first insulating layer 130' comprising a network 150' of walls 110' and trenches 120'. Thus, the height of the first insulating layer 130', measured along the Z axis, is greater than or equal to the depth of the trenches 120'. Thus, after transformation, the trenches 120' therefore extend into the thickness of the first insulating layer 130'. Preferably, they do not extend into the untransformed portion of the initial substrate 100. The height of the first insulating layer 130' is typically constant.The first insulating layer 130' thus typically has a lower face 132' extending mainly in a plane parallel to the XY plane. The lower face 132' of the first insulating layer 130' is located, along the Z axis, between the lower face 102 and the upper face 101 of the initial substrate 100.

[0110] The lower face 132' of the first insulating layer 130' is entirely located under the bottom 122' of the trenches 120'.

[0111] The transformation step typically comprises an oxidation step, conventionally a wet oxidation. For example, this step makes it possible to transform initial 110 silicon walls into 110' silica walls. The transformation step may also comprise an ion bombardment step. This ion bombardment may for example be based on carbon, oxygen and / or nitrogen ions, in doses making it possible to reach a few percent of atomic concentration to lead to a material having crystalline grains of a size less than 10 nm after rapid annealing above 1000°C for less than one second with ramps of at least 50°C / s. This ion bombardment may be preceded by a preliminary bombardment of Si+ ions making it possible to amorphize the walls to facilitate their transformation by the implantation of one of the species mentioned above (carbon, oxygen and / or nitrogen).The first insulating material has the following parameters: a first thermal conductivity Ài, a first electrical resistivity pi, a first Young's modulus Ei and a first coefficient of thermal expansion ai.

[0112] The thermal conductivity of a material is expressed in the units of the international system in W.m' 1 .K' 1 . It can for example be evaluated by the so-called 3-omega method.

[0113] The coefficient of thermal expansion of a material is expressed in the units of the international system in K' 1 . For example, it can be measured by dilatometry: the length or thickness of a sample is measured while the latter is subjected to a known temperature variation.

[0114] The value of the dimensions characterizing the geometry of the network is likely to be modified during the transformation of the initial walls 110 into walls 110'. We therefore define new dimensions, this time relating to the network 150'. The walls 110' have a width l m ' measured along the X direction. The 120' trenches have a width l t ' measured along the X direction and a depth e t ' measured along the Z direction. The walls 110' thus extend into the substrate 100 from its upper face 101 and up to a depth e t ' measured along the Z direction from the upper face 101.

[0115] The width l m 'walls 110', width l t 'trenches 120' and depth e t'120 trenches' are sized in particular according to the functional requirements of the systems carried by stack 1, in particular their operating frequency, the losses that can be tolerated in these systems or even crosstalk. The depth e t ' of the trenches 120' is typically between 5 and 20 pm. It is more advantageously at least five times greater, preferably ten times greater, than the width l m ' walls 110'. The width l m ' of the walls 110' is typically between 0.5 and 4 pm, while the width l t ' of the 120' trenches is typically between 0.25 and 4 pm. The width l m ' walls 110' and width l t ' trenches 120' are advantageously substantially equal. They are preferably chosen so that the average of the coefficients ai and 02 of thermal expansion of the first insulator and the second insulator weighted respectively by l m' and l t ' is between 0.7*a and 1.3*a, and preferably is substantially equal to the basic thermal expansion coefficient a. For example, it is possible to proceed as follows to dimension the walls 110' and trenches 120': a. Choose the first insulating material and the second insulating material which will fill the trenches 120', b. Fix the ratio between the width of the walls 110' and the width of the trenches 120' so as to satisfy the relationship mentioned above: 0.7 < l(lt'*O2+ l m '*garlic t '+ l m ')*a)l < 1 ,3, c. Choose the depth e t ' trenches so that the ratio between the relative permittivity equivalent to the set of the first and second insulating materials and the depth e t ' lead to a sufficiently weak capacitive coupling between the semiconductor film 400' and the base substrate 100'. For example, one can seek to achieve a ratio substantially equal to 7 / 15 pm-1 . The equivalent relative permittivity is the average of the relative permittivities of the first and second insulating materials, weighted by U and If. d. Choose a value for trench width l t ' such that the aspect ratio between the t ' summer t ' makes trenches easy to fill. For example, t 7th t ' of the order of 1 / 10. Then deduce the m '.

[0116] After transformation of the initial network 150 into an insulating network 150', the initial stack shown in Figure 1 E is obtained. In particular, the untransformed part of the initial substrate 100 corresponds to the base substrate 100' included in the initial stack shown in Figure 1 E. The lower face 132' of the first insulating layer 130' coincides with the upper face 10T of the base substrate 100'. The first insulating layer 130' thus extends entirely above the upper face 10T of the base substrate 100'. Like the lower face 132' of the first insulating layer 130', the upper face 10T of the base substrate 100' extends mainly in a plane parallel to the XY plane.

[0117] A second embodiment of the step of providing the initial stack will now be described with reference to Figures 1F to 1J.

[0118] As illustrated in Figure 1 F, in this embodiment, a first step consists of providing the base substrate 100'. The latter has an upper face 101' and a lower face 102' both extending mainly in planes parallel to the XY plane of the orthogonal reference frame.

[0119] A first initial insulating layer 130 is then deposited on the upper face 101' of the base substrate 100'.

[0120] A second step of this embodiment consists of forming in the first initial insulating layer 130 the network 150' of walls 110' separated by the trenches 120' as illustrated in Figures 1H and 11. The trenches 120' are formed in the thickness of the first initial insulating layer 130. Preferably, the trenches do not extend into the base substrate 100'. The first initial insulating layer 130 in which the network 150' of walls 110' has been formed corresponds to the first insulating layer 130' previously described.

[0121] The formation of the walls 110' and trenches 120' may involve the implementation of any one or more of the techniques previously described for the formation of the initial walls 110 and initial trenches 120: lithography (photolithography, electron beam lithography, double exposure lithography, extreme ultraviolet lithography), nanoimprinting, selective spreading and removal of block copolymers, or laser processing. The final etching of the trenches 120' common to all these techniques must be adapted to the nature of the first insulating material. Thus, in this embodiment, the following chemistries may be used, for example (in parentheses, the materials envisaged for the first insulating material): BCh-Ar (for AIN, BeO), O2-SF6 (for SiC), CHF3 (for SiON) and O2-CF4 (for BN and AI2O3).

[0122] In this embodiment, no transformation step is necessary. The dimensions of the network after etching therefore correspond to the dimensions If, lm', and' previously mentioned and whose sizing characteristics have already been described.

[0123] After removing the etching mask used during the step of forming the network 150, the initial stack illustrated in FIG. 1 J is obtained, similar to that obtained (FIG. 1 E) by implementing the first embodiment of the provision of this initial stack. The rest of the steps of the method will now be described with reference to FIGS. 1 K, 1 L and 4 to 8.

[0124] During a fourth step illustrated in Figure 1K, the trenches 120' are filled with the second insulating material, thus forming a second insulating layer 200. This second insulating layer 200 is formed from a plurality of regions each extending in a trench 120. It has a thickness 6200 measured along the Z direction. The thickness 6200 of the second insulating layer 200 is preferably substantially equal to the depth e t ' trenches 120'. In the common case of formation of the second insulating layer 200 by conformal deposition, a secondary thickness of second insulating material deposited from the sides of the wall network 110' can be defined. This secondary thickness, measured in the XY plane, is substantially equal to the t72. Indeed, in a trench 120', the growth fronts starting from the sides of the walls 110' surrounding the trench 120' meet when the secondary thickness is equal to half the width of the trench 120'. This secondary thickness of the second insulating layer 200 is preferably between 5 and 20 μm.

[0125] The fact that the second insulating layer 200 is formed in the trenches 120' of the first insulating layer 130' gives good mechanical strength to the assembly. More particularly, the network structure of the first insulating layer 130' and the complementary shape of the second insulating layer 200 makes it possible to obtain better mechanical strength than the simple stacking of a flat layer of first insulating material and a flat layer of second insulating material.

[0126] The second insulating material has the following parameters: a second thermal conductivity λ2, a second electrical resistivity P2, a second Young's modulus E2 and a second coefficient of thermal expansion θ2. The widths of the trenches 120' and walls 110', the first coefficient of thermal expansion α1 and the second coefficient of thermal expansion θ2 are advantageously such that the coefficient of thermal expansion of the assembly consisting of the first insulating layer 130' and the second insulating layer 200 in the X direction is substantially close to that of the base substrate 100'.

[0127] The second insulating material preferably has a high thermal conductivity λ2. It may, for example, be ALOs, AIN, SiC, SisN^ BeO or BN. These insulators in particular have a better thermal conductivity than SiC>2 which can typically be used as the first insulator. It is advantageous for the thermal conductivity λ2 of the second insulating material to be greater than the thermal conductivity λ1 of the first insulator.

[0128] The deposition of the second insulating material in the transformed trenches 120' is preferably carried out by a method making it possible to achieve high conformality. For example, the deposition of the second insulating material is carried out by LPCVD (acronym for "Low Pressure Chemical Vapor Deposition") or by ALD (acronym for "Atomic Layer Deposition").

[0129] Advantageously but optionally, provision is made, after the step of depositing the second insulating layer 200, for the deposition of a continuous layer 250 based on the second insulating material directly on the second insulating layer 200. The continuous layer 250 based on the second insulating material extends in particular directly above the network 150'. More precisely, it covers the tops 11T of the transformed walls 110'. It can also extend into the transformed trenches 120', up to a depth depending on the thickness 6200 of the second insulating layer. Advantageously, the second insulating layer 200 completely fills the trenches 120' and the continuous layer 250 does not extend into the transformed trenches 120'. The continuous layer 250 and the second insulating layer 200 thus form a continuous assembly based on the second insulating material. This optional step is illustrated in Figure 4.In this embodiment, the buried insulating layer 1000 comprises the first insulating layer 130', the second insulating layer 200 and the continuous layer 250. Advantageously but optionally, after the step of depositing the second insulating layer 200, a step of depositing a third insulating layer 300 of thickness e300 measured in the Z direction and having an upper face 301 extending mainly in the XY plane of the orthogonal reference frame is provided. This third insulating layer 300 is deposited on the second insulating layer 200 or on the continuous layer 250 if such a layer has been deposited. It is based on a third insulating material which may possibly be identical to the first insulator. For example, it may be based on silica.The third insulator has the following parameters: a third thermal conductivity 3, a third electrical resistivity ps, a third Young's modulus E3 and a third coefficient of thermal expansion 03.

[0130] In this embodiment, the insulating layer 1000 comprises the first insulating layer 130', the second insulating layer 200, the third insulating layer 300 and optionally the continuous layer 250, as shown in FIG. 5.

[0131] The method may comprise, after the step of depositing the second insulating layer 200 and any other insulating layers, an optional step of planarizing the buried insulating layer 1000. This may be carried out by means of a chemical-mechanical planarization (CMP) step starting from the upper face 1001 of the buried insulating layer 1000. In the event that a third insulating layer 300 has been deposited on the second insulating layer 200, it is advantageous, in the context of the planarization of the buried insulating layer 1000, for the thickness 6300 to be greater than twice, preferably four times, the maximum roughness of the surface of the underlying layer of second insulating material. This prevents the roughness of this surface from being transferred to the upper face 301 of the third insulating layer 300.In all cases, the CMP step aims for a removal greater than twice, preferably substantially equal to three times the maximum roughness of the upper face 1001 of the buried insulating layer 1000.

[0132] Planarization can alternatively be obtained by carrying out a planarizing deposition on the upper face 1001 of the buried insulating layer 1000. This can for example be a deposition of hydrogen silsesquioxane (HSQ).

[0133] This optional step aims in particular to prepare the upper face 1001 of the buried insulating layer 1000 for the step of supplying the semiconductor film 400' which will be described later, in particular when the semiconductor film 400' is supplied by bonding.

[0134] A fifth step is shown in Figure 1 L. It consists of the formation of a semiconductor film 400' on the buried insulating layer 1000. More precisely, the semiconductor film 400' can directly cover the second insulating layer 200, the continuous layer based on the second insulating material 250 or even the third insulating layer 300, depending on whether optional layers have previously been deposited on the second insulating layer.

[0135] The 400' semiconductor film can, for example, be based on Si, or a III-V material such as InP, GaAs or GaN. These materials are commonly used for the production of RF devices.

[0136] According to one embodiment of the method, the formation of the semiconductor film 400' includes the implementation of a Smart Cut® type method. An embodiment of this method is illustrated in Figures 6A to 6D.

[0137] Figure 6A illustrates the provision of a semiconductor layer 400 having an upper face 401 and a lower face 402 both extending mainly in the XY plane of the orthogonal reference frame. This same figure illustrates the implantation of light ions into the semiconductor layer 400 from its upper face 401 to form an implanted zone 500. The semiconductor layer 400 thus defines, between its upper face 401 and the implanted zone 500, a semiconductor film 400'. The implanted zone 500 advantageously extends parallel to the upper face 401 and the lower face 402 of the semiconductor layer 400.

[0138] As shown in Figure 6B, the semiconductor layer 400 is then bonded at its upper face 401 to the upper face 1001 of the buried insulating layer 1000. Carrying out the optional step of planarizing the buried insulating layer 1000 previously described makes it possible to improve the quality of the bonding interface between the semiconductor film 400' and the upper face 1001 of the buried insulating layer 1000.

[0139] After the bonding step, the semiconductor layer 400 is subjected to a treatment allowing its embrittlement at the level of the zone implanted with gaseous elements. As shown in FIG. 6C, the semiconductor layer 400 can then be cleaved. Then remains on the buried insulating layer the semiconductor film 400' of the same material as the semiconductor layer 400 and whose thickness 6400' along Z depends on the implantation depth of the implanted zone 500 in the semiconductor layer 400. Thus, the semiconductor film 400' is transferred onto the stack 1. The stack 1 thus obtained is shown in FIG. 6D. More precisely, this figure illustrates the stack 1 obtained in the embodiment comprising the optional steps of depositing a continuous layer based on the second insulating material 250 and of depositing a third insulating layer 300.

[0140] It is also possible to bond the semiconductor layer 400 to the upper face 1001 of the buried insulating layer 1000 at its lower face 402. The semiconductor film 400 is then defined between the implanted area 500 and the lower face 402. Other embodiments of the Smart Cut® method can be implemented. For example, it is possible to choose a semiconductor material for the base substrate 100'. The implantation of light ions to form the implanted area can then be carried out in the base substrate 100', for example through the buried insulating layer 1000. It is then possible to bond a handle to the buried insulating layer (and therefore either to the second insulating layer 200, or to the continuous layer based on the second insulating material 250, or to the third insulating layer 300).Like the semiconductor layer 400 in the previously described embodiment, the base substrate 100' can then be cleaved at the transferred light ion layer to obtain a semiconductor film. The handle can then be polished to form a substrate for the final structure.

[0141] The methods that can be used to provide the semiconductor film 400' on the buried insulating layer 1000 are however not limited to the Smart Cut® processes just described. Any other thin film transfer technique is conceivable.

[0142] For example, it is possible to bond the semiconductor layer 400 to the upper face 1001 of the buried insulating layer 1000, then to carry out lapping steps, possibly supplemented by a CMP polishing step, and etching from its lower face 402 allowing this layer to be thinned until the semiconductor film 400' is obtained.

[0143] According to another embodiment, the semiconductor film is formed on a fusible layer itself deposited on a transparent material. The semiconductor film 400' is bonded to the upper face 1001 of the buried insulating layer 1000 by direct bonding at the level of the face opposite the fusible layer. The fusible layer is then exposed so as to degrade it and detach it from the semiconductor film 400'.

[0144] According to another embodiment, the semiconductor film 400' is epitaxially grown on a weakened zone, for example by porosification, on the surface of a semiconductor layer. The semiconductor film 400' is then bonded, at its face opposite the weakened zone, to the upper face 1001 of the buried insulating layer 1000. The transfer is then carried out by mechanical separation at the weakened layer, for example by inserting a blade or by water jet.

[0145] Figures 7 and 8 represent the devices that can be obtained by the method according to the invention, in the cases where, respectively, no optional layer has been deposited, and where only a continuous layer based on the second insulating material 250 has been optionally deposited. The proposed method is particularly advantageous for RF applications. In this case, the semiconductor film 400' will preferably be based on InP, GaAs or GaN.

[0146] The invention is not limited to the embodiments previously described and extends to all embodiments covered by its spirit.

[0147] DIGITAL REFERENCES stack . etching mask . printable resin layer . top face of the printable resin layer . bottom face of the printable resin layer . nanoimprint mold . polymer layer . block of first polymer . block of second polymer 0. initial substrate 1. top face of the initial substrate 2. bottom face of the initial substrate 0'. base substrate T. top face of the base substrate 2'. bottom face of the base substrate 0. walls 0'. transformed walls T. tops of the oxidized walls 0. trenches 0'. transformed trenches 2'. bottom of the trenches 0. first initial insulating layer 1. top face of the first initial insulating layer 2. bottom face of the first initial insulating layer 0'. first insulating layer 2'. bottom face of the first insulating layer 0. network of walls 0'. network of oxidized walls 0. second insulating layer 1 . upper face of the second insulating layer 0.continuous layer based on second insulating material 300. third insulating layer.

[0148] 301. upper face of the third insulating layer

[0149] 400. semiconductor layer

[0150] 401. upper face of the semiconductor layer 402. lower face of the semiconductor layer

[0151] 400'. semiconductor film

[0152] 500. implanted area

[0153] 1000. buried insulating layer

[0154] 1001. upper face of the buried insulating layer

Claims

CLAIMS 1. Method for manufacturing a stack (1) comprising the following step: • Providing at least one initial stack comprising: i. a base substrate (100') based on a base material having a so-called base thermal expansion coefficient a, the base substrate (100') having an upper face (10T) and a lower face (102') both extending mainly along an XY plane, ii. a first insulating layer (130') overlying the upper face (10T) of the base substrate (100'), the first insulating layer (130') being based on a first insulating material, the first insulating material having a first thermal conductivity Δi and a first thermal expansion coefficient ai, the first insulating layer (130') comprising a network (150') of trenches (120'), characterized in that the method also comprises at least the following steps: • Filling the trenches (120') with a second insulating material having a second thermal conductivity λ2 and a second coefficient of thermal expansion θ2, thus forming a second insulating layer (200), the second thermal conductivity λ2 being different from the first thermal conductivity λ1, θ1 and θ2 being greater than 0.3 ppm / K, and • Form a semiconductor film (400') above the second insulating layer (200).

2. Method for manufacturing a stack (1) according to the preceding claim in which 0 < 2*1(02-01)1 / (02+01) < 1.8 and 0 < I (o-oi ) | / o < 2.

1.

3. Method of manufacturing a stack (1) according to any one of the preceding claims in which ki < I (À2-À1 ) / Ài I , with 0.3 < ki.

4. Method of manufacturing a stack (1) according to any one of the preceding claims in which the second thermal conductivity λ2 is strictly greater than the first thermal conductivity λ1.

5. Method of manufacturing a stack (1) according to any one of the preceding claims in which one of the first coefficient of thermal expansion 01 and the second coefficient of thermal expansion 02 is greater than o and the other among the first coefficient of thermal expansion ai and the second coefficient of thermal expansion 02 is less than a.

6. Method for manufacturing a stack (1) according to any one of the preceding claims in which the first insulating material has a first Young's modulus E1 and the second insulating material has a second Young's modulus E2, with EI^E2, preferably with rm < I(E2-EI) / EI I , with 0.03 < rm, E1 and E2 being greater than 50 GPa.

7. A method of manufacturing a stack (1) according to any one of the preceding claims wherein the step of providing the initial stack comprises the following steps: • Provide at least one initial substrate (100) based on, preferably made of, the base material and having an upper face (101), • Form in the initial substrate (100) and from the upper face (101) an initial network (150) of initial trenches (120), • Transforming at least the base material on at least a portion of the initial substrate (100) into the first insulating material, thereby forming the first insulating layer (130').

8. Method for manufacturing a stack (1) according to the preceding claim in which transforming at least the base material on at least a portion of the initial substrate (100) comprises an oxidation of the base material separating the initial trenches (120) from each other.

9. Method of manufacturing a stack (1) according to any one of claims 1 to 6 in which the step of providing the initial stack comprises the following steps: • Provide the base substrate (100'), • Forming a first initial insulating layer (130) overlying the base substrate (100'), the first initial insulating layer (130) being based on the first insulating material, • After the step of forming a first initial insulating layer (130), forming in the first initial insulating layer (130) the network (150') trenches (120'), thus forming the first insulating layer (130').

10. Method for manufacturing a stack (1) according to any one of the preceding claims further comprising, before the step of forming the semiconductor film, a step of forming a continuous layer (250) based on the second insulating material directly covering the second insulating layer (200).

11. Method for manufacturing a stack (1) according to any one of the preceding claims, further comprising a step of forming a third insulating layer (300) based on a third insulating material distinct from the second insulating material, under the semiconductor film (400').

12. A method of manufacturing a stack (1) according to any one of the preceding claims, in which the first insulating material remaining between consecutive trenches forms a wall (110'), each wall (110') has a wall width lm' and the trenches (120') have a trench width l t ', in which the ratio lt' / lm' is between 0.3 and 3, preferably between 0.5 and 1.5, and in which preferably 0.7 < l(l t '*a2+ l m '*ai) / ((lt'+ l m ')*a)l < 1 ,3.

13. Method of manufacturing a stack (1) according to any one of the preceding claims in which the trenches (120') have a depth e t ', with e t ' between 5 pm and 20 pm, preferably between 8 pm and 15 pm.

14. Method of manufacturing a stack (1) according to any one of the preceding claims in which the second insulating material is made or is based on one of AfeOs, AIN, SiC, Sisl^, BeO, a silicon oxynitride and BN.

15. Method of manufacturing a stack (1) according to any one of the preceding claims in which the first insulating layer is entirely made of the first insulating material.

16. Method of manufacturing a stack (1) according to any one of the preceding claims in which the first insulating material and the second insulating material are each distinct from the base material.

17. Microelectronic device comprising a stack (1) of layers comprising: • a base substrate (100') having an upper face (10T) and a lower face (102') both extending mainly along an XY plane, • a buried insulating layer (1000) comprising: a first insulating layer (130') based on a first insulating material and comprising a plurality of walls (110'), the first insulating material having a first thermal conductivity Δ1 and a first thermal expansion coefficient α1, the first insulating layer (130') surmounting the upper face (101') of the base substrate (100'), a second insulating layer (200) based on a second insulating material and extending at least in the trenches (120') separating the walls (110'), the second insulating material having a second thermal conductivity λ2 and a second coefficient of thermal expansion a2, the second thermal conductivity λ2 being different from the first thermal conductivity λ1, a1 and a2 being greater than 0.3 ppm / K, and preferably a third insulating layer (300) overlying the second insulating layer (200), • a semiconductor film (400').

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