Electronic arrangement and method for forming an electronic arrangement
Patent Information
- Application Number
- EP2023813313
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-12-13
- Filing Date
- 2023-11-22
- Publication Date
- 2025-10-22
AI Technical Summary
Existing electronics arrangements with semiconductor components face mechanical stress issues due to thermal gradients, leading to reliability concerns under electrical and thermal loads, particularly in power semiconductor applications where heat release causes thermal stresses.
The use of mechanically flexible pins with specific dimensions and materials, such as copper, silver, or aluminum, on contacting elements that contact circuit carriers, combined with a soft casting to enhance mechanical stability and heat dissipation, and additive manufacturing for precise pin production.
This solution effectively compensates for mechanical stresses and thermal voltages, ensuring reliable operation and extended lifespan of the electronics arrangement by maintaining flexibility and mechanical stability, while improving heat dissipation through thermally conductive circuit carriers and heat sinks.
Smart Images
Figure 1.1
Abstract
Description
[0001] Description
[0002] title
[0003] Electronic arrangement and method for forming an electronic arrangement
[0004] State of the art
[0005] The invention relates to an electronic arrangement and a method for forming an electronic arrangement.
[0006] DE 10 2015 205 704 A1 discloses a contact arrangement for at least one semiconductor component. The contact arrangement comprises the semiconductor component, in particular a power semiconductor component. The semiconductor component has a top side and a bottom side. An electrical connection of the semiconductor component is formed on the bottom side. This bottom-side connection is connected to a circuit carrier. The circuit carrier is designed, for example, as DBC (direct bonded copper) and has a ceramic layer arranged between two copper layers. The electrical contact between the top side of the semiconductor component and the circuit carrier is established via bond wire connections.
[0007] Disclosure of the invention
[0008] Advantages of the invention
[0009] The electronic arrangement according to the invention comprising a semiconductor component, a first circuit carrier and at least one contacting element, wherein the at least one contacting element contacts the first circuit carrier, in particular contacts it in an electrically conductive and / or thermally conductive manner, wherein the at least one contacting element has a plurality of pins, in particular a plurality of pins arranged next to one another, wherein the pins have an average diameter of between 100 pm and 2000 pm, has the advantage that mechanical stresses occurring due to thermal gradients are compensated by the mechanically flexible pins within the electronic arrangement, so that the electronic arrangement operates reliably even under changing electrical and thermal loads. This thus contributes to a long-lasting electronic arrangement.The pins of the at least one contacting element compensate for stresses in the x- and / or y-direction, i.e. in a plane perpendicular to an extension of the pins, which arise due to thermal gradients. The pins are designed as individual, free-standing structures, wherein the pins of a contacting element are or will be constructed on the same contact surface on a circuit board or a circuit carrier or a semiconductor component. In particular, a pin has a long and thin, pin-shaped, three-dimensional basic shape. Preferably, the height of the pin is greater than the diameter of the pin; in particular, the height of the pin is at least twice as large, preferably more than five times as large, particularly preferably ten times as large, as the diameter of the pin. In particular, the pins have a round cross-section that remains constant with the height. In one variant, the cross-section of the pins is square and / or the cross-section of the pins has a freeform shape.The at least one contacting element has free spaces between the pins, so that the pins fill part of the volume of the contacting elements and the remaining part is free space, so that the pins and the free spaces form the volume of the contacting elements. Preferably, the ratio of the volume of the pins to the volume of the contacting element is greater than 1 to 20, in particular alternatively or additionally at least 1 to 3.
[0010] Preferably, the pins consist of or comprise copper and / or silver and / or aluminum and / or alloys with one of the materials from the group of copper, silver and aluminum as a base component or a metal matrix composite with at least one of the materials from the group of copper and / or silver and / or aluminum as a base component.
[0011] An electronics arrangement in which the pins have an average diameter of between 100 pm and 2000 pm and an average height of between 200 pm and 3000 pm is also advantageous, since pins dimensioned in this way are sufficiently flexible to absorb the mechanical stresses, but at the same time have the necessary mechanical stability. It is advantageous that there are free spaces between the pins of the at least one contacting element. The pins are particularly preferably aligned parallel to one another and / or perpendicular to a surface of the first circuit carrier, since pins designed in this way can absorb mechanical stresses in both the x-direction and the y-direction. In one variant, the pins are aligned parallel in one direction and non-parallel in a different direction. This has the advantage that the mechanical strength in the x-direction and the y-direction can be adjusted independently of one another.
[0012] An electronic arrangement in which a first contacting element with pins dimensioned in such a way electrically conductively contacts a first contact surface of the semiconductor component with a contact surface of the first circuit carrier and a second contacting element with pins dimensioned in such a way contacts the first circuit carrier with a second circuit carrier, in particular electrically conductively, is particularly advantageous, since this compensates for thermal stress both between the semiconductor component and the circuit carrier and between the two circuit carriers.
[0013] Also advantageous is an electronic arrangement in which the second circuit carrier is electrically conductively connected to a second contact surface of the semiconductor component, in which the first contact surface of the semiconductor component is electrically conductively connected to the first circuit carrier via the first contacting element, and in which the first circuit carrier is connected, in particular electrically conductively connected, to the second circuit carrier via the second contacting element, since this compensates for thermal stresses in the overall structure between the first circuit carrier, the second circuit carrier and the semiconductor component.
[0014] The design of the contacting elements with such pins is particularly advantageous in electronic assemblies in which the semiconductor component is designed as a power semiconductor component, since power semiconductor components convert high electrical power, which causes thermal stresses in the electronic assembly due to unavoidable power losses caused by heat dissipation. In particular, the power semiconductor component is an insulated-gate bipolar transistor (IGBT) and / or a metal oxide semiconductor field-effect transistor (MOSFET), in particular a power MOSFET.
[0015] Also advantageous is an electronic arrangement in which the first circuit carrier and / or the second circuit carrier are a direct-bonded copper substrate (DBC substrate) and / or an active-metal-brazed substrate (AMB substrate) and / or an insulated-metal substrate (IMS) and / or a metal-core printed circuit board and / or a lead frame, since such circuit carriers can dissipate the heat generated by losses in the power semiconductor component particularly well, since such circuit carriers have a high thermal conductivity.
[0016] An electronics assembly with soft encapsulation is particularly advantageous. The soft encapsulation is designed such that the soft encapsulation encapsulates at least one component, in particular the power semiconductor component, the contacting elements, and the circuit carriers. The soft encapsulation has the advantage of being flexible and allowing compensatory movements of the pins of the contacting elements without being damaged itself. It is also particularly advantageous that the soft encapsulation fills the spaces between the pins of the contacting element(s), since filling the spaces between the pins with the soft encapsulation contributes to the mechanical stability of the contacting element and increases the mechanical stability and resilience of the electronics assembly, for example against vibrations or other mechanical loads, while at the same time maintaining the flexibility of the pins.The soft encapsulation preferably consists of or comprises plastic, for example, an epoxy and / or a polymer. The material of the soft encapsulation is designed to withstand operating temperatures up to 200°C and / or dielectric strengths up to 1500V.
[0017] Also advantageous is an electronics arrangement having at least one heat sink, wherein the first circuit carrier or the second circuit carrier, in particular both circuit carriers, is / are thermally conductively connected to a heat sink on a side of the circuit carrier facing away from the semiconductor component, since this improves heat dissipation from the power semiconductor component. This contributes to a long service life of the power semiconductor component and the entire electronics arrangement. Preferably, the electronics arrangement has two heat sinks, wherein the first circuit carrier is thermally conductively connected to a first heat sink and the second circuit carrier is thermally conductively connected to a second heat sink, each on the side of the circuit carrier facing away from the semiconductor component.
[0018] The invention further relates to a method for forming an electronic arrangement with a first circuit carrier and a semiconductor component, wherein the electronic arrangement is formed as described above, wherein at least one contacting element is contacted with the first circuit carrier, in particular contacted in an electrically conductive and / or thermally conductive manner, wherein a plurality of pins of the at least one contacting element are produced with an average diameter between 100 pm and 2000 pm. A method in which the pins are produced by means of an additive manufacturing process is particularly advantageous, in particular in which the pins are printed onto the first circuit carrier and / or onto a first contact surface of the semiconductor component and / or onto a second circuit carrier by means of an additive manufacturing process.Additive manufacturing processes have the advantage that the fine structures of the pins are easy to produce and, secondly, that the material properties of the pins can be adjusted and individually adapted to the respective contact partner by adjusting the process parameters of the additive manufacturing process, for example by adjusting the flexibility of the pins. The pins therefore have an additively manufactured material structure. The additive manufacturing process is preferably selective laser beam melting (SLM). A further advantageous method is one in which the pins are manufactured with an average height between 200 pm and 3000 pm and / or aligned parallel to one another and / or perpendicular to a surface of the first circuit carrier.
[0019] Further advantages will become apparent from the following description of exemplary embodiments with reference to the figures and the dependent claims. Brief description of the drawings
[0020] Embodiments of the invention are illustrated in the drawings using several figures and explained in more detail in the following description.
[0021] They show:
[0022] Fig. 1 an electronic arrangement, and
[0023] Fig. 2 is a flowchart of a method for forming an electronic assembly.
[0024] Description of implementation examples
[0025] The following describes an electronic arrangement comprising a semiconductor component, a first circuit carrier and at least one contacting element, wherein the at least one contacting element contacts the first circuit carrier, in particular in an electrically conductive and / or thermally conductive manner, wherein the at least one contacting element has a plurality of pins, wherein the pins have an average diameter of between 100 pm and 2000 pm. Furthermore, a method for forming an electronic arrangement with a first circuit carrier and a semiconductor component is described, wherein at least one contacting element is contacted with the first circuit carrier, in particular in an electrically conductive and / or thermally conductive manner, wherein a plurality of pins of the at least one contacting element with an average diameter of between 100 pm and 2000 pm are produced by means of an additive manufacturing method.
[0026] The contacting elements (spacers) described below with reference to the figures, which are flexible in the x-direction and / or y-direction, are preferably presented in the form of free-standing fine pins. Flexibility is achieved by subdividing the contacting element (spacer) into many fine structures. These structures are preferably printed directly onto the substrates using hybrid 3D printing. The pins have a diameter in the range of 100 pm to 2000 pm. The cross-sectional shape of the pins is variable. Alternatively or additionally, the pins have a height in the range of 200 pm to 3000 pm. Metals or metal matrix composites are used as the material for the pins, for example, copper with admixtures of SiC particles to adjust the thermal expansion coefficient.The metals used exhibit high electrical conductivity, ensuring low contact resistance of the contact element even with the fine structures of the pins, as the contact element has a reduced cross-section compared to a contact element made of solid material. Furthermore, the contact element is designed to exhibit high thermal conductivity, particularly when the semiconductor component is cooled by means of double-sided cooling.
[0027] Figure 1 shows an electronic arrangement 10 comprising a semiconductor component 12, a first circuit carrier 14, and a first contacting element 18. In the preferred exemplary embodiment, the semiconductor component 12 is a power semiconductor component, for example an insulated-gate bipolar transistor (IGBT) or a metal oxide semiconductor field-effect transistor (MOSFET), in particular a power MOSFET. For example, the semiconductor component 12 is an IGBT with a diode connected in parallel. The first contacting element 18 is electrically conductively contacted with a contacting surface of the first circuit carrier 14 by a first contacting side.Furthermore, the first contacting element 18 is electrically conductively contacted with a first contact surface 24 of the semiconductor component 12 by a second contacting side facing away from the first contacting side. Furthermore, the electronic arrangement 10 comprises a second contacting element 20 and a second circuit carrier 16. The second contacting element 20 is electrically conductively contacted with the first circuit carrier 14 by a first contacting side, in particular with a contact surface of the first circuit carrier 14.Furthermore, the second contacting element 20 is contacted with the second circuit carrier 16 by way of a second contacting side facing away from the first contacting side, in particular is electrically conductively contacted with a contacting surface of the second circuit carrier 16. The first contacting element 18 and the second contacting element 20 comprise a plurality of pins 22 which are aligned parallel to one another and perpendicular to a surface 32 of the first circuit carrier 14 and which have an average diameter of between 100 pm and 2000 pm. In the preferred exemplary embodiment, the pins 22 are also aligned perpendicular to a surface of the semiconductor component 12 and / or perpendicular to a surface of the second circuit carrier 16. The pins 22 have an average height of between 200 pm and 3000 pm.In the preferred embodiment, the pins 22 of the first contacting element 18 have a smaller height than the pins 22 of the second contacting element 20 because the second contacting element 20 has to bridge a greater distance than the first contacting element 18. Furthermore, there are free spaces 30 between the pins 22 of the two contacting elements 18, 20, so that the pins 22 fill part of the volume of the contacting elements 18, 20 and the remaining part is free spaces 30, so that the pins 22 and the free spaces 30 form the volume of the contacting elements 18, 20. In the preferred embodiment, the pins 22 have a cylindrical shape with a circular cross-section. In the preferred embodiment, the first circuit carrier 14 and the second circuit carrier 16 are formed as a direct-bonded copper substrate.A direct-bonded copper substrate comprises a carrier plate made of a ceramic material that is directly coated with copper to form conductive tracks. In one variant, the first circuit carrier 14 and the second circuit carrier 16 are designed as an active-metal-brazed substrate. In an active-metal-brazed substrate, the copper is brazed to the carrier plate made of a ceramic material. The ceramic material of the carrier plate in the direct-bonded copper substrate or the active-metal-brazed substrate is, for example, aluminum oxide (Al2O3) and / or zirconium oxide-doped aluminum oxide and / or aluminum nitride (AlN) and / or silicon nitride (SiNzi). In one variant, the first circuit carrier 14 and the second circuit carrier 16 are designed as an insulated-metal substrate.An insulated metal substrate comprises a carrier plate made of aluminum coated with a thin insulating layer, on which a copper layer is then located to form the conductor tracks. In a further variant, the first circuit carrier 14 and the second circuit carrier 16 are designed as a metal-core printed circuit board (insulated metal substrate, IMS) and / or a lead frame. A metal-core printed circuit board comprises a heat-dissipating plate, for example made of aluminum, and a dielectric layer made of a polymer filled with ceramic powder, as well as conductor tracks arranged on the dielectric layer. In a further variant, the first circuit carrier 14 and the second circuit carrier 16 are formed from different substrates.The electronic arrangement 10 has the following structure: the second circuit carrier 16 is electrically conductively connected to a second contact surface 26 of the semiconductor component 12, the first contact surface 24 of the semiconductor component 12 is electrically conductively connected to a contact surface of the first circuit carrier 14 via the first contacting element 18, and the first circuit carrier 14 is connected to the second circuit carrier 16 via the second contacting element 18, in particular electrically conductively connected via a contact surface.
[0028] The electronics assembly 10 further comprises a soft encapsulation 28. The soft encapsulation 28 encapsulates at least the semiconductor component 12 and the first contacting element 18. In the preferred embodiment, the soft encapsulation 28 additionally encapsulates the second contacting element 20. Furthermore, the soft encapsulation 28 preferably encapsulates at least a portion of the first circuit carrier 14 and / or a portion of the second circuit carrier 16. In the preferred embodiment, the soft encapsulation 28 fills the free spaces 30 between the pins 22 of the first contacting element 18 and / or the free spaces 30 between the pins 22 of the second contacting element 20. In the preferred embodiment, the pins 22 have an additively manufactured material structure.Furthermore, in the preferred embodiment, the first circuit carrier 14 is thermally conductively connected to a first heat sink (not shown) on a side facing away from the semiconductor component 12, and the second circuit carrier 16 is thermally conductively connected to a second heat sink (not shown) on a side facing away from the semiconductor component 12.
[0029] Figure 2 shows a flowchart of a method for forming an electronic assembly described with reference to Figure 1. In a first method step 40, the second circuit carrier is provided. The second circuit carrier comprises a carrier plate with copper lines as described above. In a second method step 42, the semiconductor component, in particular a power semiconductor component, is provided, and the semiconductor component is electrically conductively connected with its second contact surface to a contacting surface of a copper line of the second circuit carrier, for example by soldering and / or sintering.In a third method step 44, the pins of the first contacting element are printed in a first sub-step onto the semiconductor component and the pins of the second contacting element are printed in a second sub-step onto the second circuit carrier, in particular onto a contacting surface of a copper line of the second circuit carrier, using an additive manufacturing method. In one variant, after the first sub-step and the printing of the pins of the first contacting element onto the semiconductor component in the second sub-step, the pins of the second contacting element are printed onto the first circuit carrier using an additive manufacturing method. The printed pins have an average diameter of between 100 pm and 2000 pm, the pins of a contacting element having substantially the same average diameter in the region forming the contacting element.The pins are aligned substantially parallel to one another and perpendicular to a surface of the second circuit carrier. In a fourth method step 46, the first circuit carrier is provided, and the first circuit carrier is connected to the two printed contacting elements, for example by soldering and / or sintering. The second circuit carrier comprises a carrier plate with copper lines. After connection, the pins of the first contacting element and the pins of the second contacting element are aligned substantially perpendicular to a surface of the first circuit carrier. In a fifth method step 48, the electronic assembly is encapsulated with a soft encapsulation. The soft encapsulation is applied such that the soft encapsulation fills the spaces between the pins of the contacting elements.
[0030] In a variant of the described method for producing an electronic assembly, after the first method step 40 and the second method step 42, the third method step 44 is carried out in a modified manner in that the pins are applied to a provided first circuit carrier using an additive manufacturing process. The pins are also applied essentially parallel to one another and perpendicular to a surface of the first circuit carrier. In a subsequent modified fourth method step 46, the first and second contacting elements produced on the first circuit carrier are connected to the component assembly produced by the second method step 42, consisting of the second circuit carrier and the semiconductor component, for example by soldering and / or sintering.The first contacting element is electrically conductively contacted with a first contact surface of the semiconductor component, thereby establishing an electrically conductive connection between the semiconductor component and a contact surface of the first circuit carrier. Furthermore, the second contacting element is contacted with the second circuit carrier, in particular, electrically conductively contacted. In a fifth method step 48, the electronic assembly is encapsulated with a soft encapsulation. The soft encapsulation is applied such that it fills the spaces between the pins of the contacting elements.
Claims
Claims 1 . Electronic arrangement (10) comprising a semiconductor component (12), a first circuit carrier (14) and at least one contacting element (18, 20), wherein the at least one contacting element (18, 20) contacts the first circuit carrier (14), in particular contacts it in an electrically conductive and / or thermally conductive manner, characterized in that the at least one contacting element (18, 20) has a plurality of pins (22), wherein the pins (22) have an average diameter between 100 pm and 2000 pm.
2. Electronic arrangement (10) according to claim 1, characterized in that the pins (22) have an average height between 200 pm and 3000 pm and / or that pins (22) are aligned parallel to one another and / or perpendicular to a surface (32) of the first circuit carrier (14).
3. Electronic arrangement (10) according to one of the preceding claims, characterized in that there are free spaces (30) between the pins (22) of the at least one contacting element (18, 20).
4. Electronic arrangement (10) according to one of the preceding claims, characterized in that a first contacting element (18) of the contacting elements (18, 20) electrically conductively contacts a first contact surface (24) of the semiconductor component (12) with the first circuit carrier (14).
5. Electronic arrangement (10) according to one of the preceding claims, characterized in that that a second contacting element (20) of the contacting elements (18, 20) contacts the first circuit carrier (14) with a second circuit carrier (16), in particular electrically conductively. Electronic arrangement (10) according to claim 5, characterized in that the electronic arrangement (10) has the following structure: - the second circuit carrier (16) is electrically conductively connected to a second contact surface (26) of the semiconductor component (12), - the first contact surface (24) of the semiconductor component (12) is electrically conductively connected to the first circuit carrier (14) via the first contacting element (18), and - the first circuit carrier (14) is connected, in particular electrically conductively connected, to the second circuit carrier (16) via the second contacting element (18). Electronic arrangement (10) according to one of the preceding claims, characterized in that the semiconductor component (12) is a power semiconductor component. Electronic arrangement (10) according to one of the preceding claims, characterized in that the first circuit carrier (14) and / or the second circuit carrier (16) are a direct-bonded copper substrate and / or an active-metal-brazed substrate and / or an insulated-metal substrate and / or a metal-core printed circuit board and / or a lead frame. Electronic arrangement (10) according to one of the preceding claims, characterized by a soft encapsulation (28) in which at least one component of the electronic arrangement (10) is encapsulated. Electronic arrangement (10) according to claim 9, characterized in that the soft encapsulation (28) fills the free spaces (30) of at least one of the or all of the contacting elements (18, 20) between the pins (22). Electronic arrangement (10) according to one of the preceding claims, characterized in that the pins (22) have an additively manufactured material structure. Electronic arrangement (10) according to one of the preceding claims, characterized in that the electronic arrangement (10) comprises at least one heat sink, wherein the first circuit carrier (14) or the second circuit carrier (16), preferably the first circuit carrier (14) and the second circuit carrier (16), is thermally conductively connected to the heat sink with a side of the circuit carrier (14, 16) facing away from the semiconductor component (12).Method for forming an electronic arrangement (10) with a first circuit carrier (14) and a semiconductor component (12), wherein the electronic arrangement (10) is designed in particular according to one of claims 1 to 12, wherein at least one contacting element (18, 20) is contacted with the first circuit carrier (14), in particular contacted in an electrically conductive and / or thermally conductive manner, characterized in that a plurality of pins (22) of the at least one contacting element (18, 20) are produced with an average diameter between 100 pm and 2000 pm. Method according to claim 13, characterized in that the pins (22) are produced with an average height between 200 pm and 3000 pm and / or aligned parallel to one another and / or perpendicular to a surface (32) of the first circuit carrier (14).Method according to one of claims 13 or 14, characterized in that the pins (22) are connected to the first circuit carrier (14) and / or to a first contact surface (24) of the semiconductor component (12) and / or to a. second circuit carrier (16) by means of an additive manufacturing process.