A design for enhancing the long term reliability of a large joining area in a power semiconductor module

Abstract

A new substrate design for power semiconductor modules, and semiconductor modules comprising the same, with a grid-patterned bottom layer configures such that large-area abonding layer is converted into a plurality of small-area bonding layers. The substrate according to the present disclosure facilitate the use of pressure-less or pressure assisted sintering technology, and / or transient liquid phase bonding (TLPS) technology for the bonding surface, thereby greatly improving the reliability of the connection between the substrate and a baseplate or heatsink.

Description

[0001]M&C Folio: PC932609WO A Design for Enhancing the Long Term Reliability of a Large Joining Area In a Power Semiconductor Module Field of the Disclosure The present application relates to power semiconductor packaging, particularly but not exclusively, to substrates suitable for use in power semiconductor packaging with large area attachments. Background Power semiconductor modules are utilised in a wide variety of applications, and face various challenges in order to meet the high standard requirements for the disparate conditions found in e.g. automotive, aerospace, renewable energy and other industries. It is generally desired that semiconductor modules should be compact with a high power density, and be able to operate in harsh environments for a relative long lifetime span (e.g. more than 15 years). Various devices have been provided that aim to improve the operational capability and stability of power semiconductor modules under various conditions, such as at high temperatures, high humidity levels, under high mechanical shock and vibration, high radiation levels and other harsh environments. However, there remains scope for improvements in the reliability of semiconductor packages under various conditions. One such state-of-the-art power semiconductor module is shown in Figure 1. The module of Figure 1A comprises a semiconductor device or chip 1 attached to a substrate 3 via a joining layer 2, also called a bonding or attach layer. The substrate 3 (as illustrated in Figures 1B and C) has a three-layer structure: a top copper circuit layer 4, to which the power semiconductor device 1 is attached, and which generally provides the electrical circuit and connection for the power device; a bottom backing copper layer 6, which provides a thermal transfer path for the heat generated inside the power devices; and a middle ceramic insulating layer 5, configured to electrically isolate the top (circuit) layer 5 from the bottom layer 6. The bottom layer 6 (and therefore the substrate 3) is in turn attached to a baseplate 8, via a second joining layer 7. To provide or enhance the cooling of a semiconductor chip, modules such as that depicted in Figure 1 may be joined to heatsinks, e.g. in place of baseplate 8. Examples of a state-of-the- art modules attached to heatsinks are shown in Figures 2A and B. Figure 2A illustrates a single sided cooling module, comprising a semiconductor module 10 attached via joining layers 11 1 12729437-1 M&C Folio: PC932609WO to heatsink 12. The semiconductor module 10 may be similar in construction to the semiconductor module depicted in Figure 1, comprising a semiconductor device or chip 1 and substrate 3, with the substrate attached to the heatsink 12 e.g. in place of baseplate 8. Figure 2B illustrates an alternative double side cooling (DSC) module, in which module 10 is attached to upper and lower heatsinks 12a,b by upper and lower joining layers 11a,b, so as to facilitate improved cooling from both the top and bottom of the module 10. Relative to the module of Figure 2A, module 10 of Figure 2B may comprise an additional (upper) substrate layer joined to the upper side of a semiconductor chip, such that the upper and lower heatsinks 12a,b are each attached to respective upper and lower substrates. The joining layers 2, 7, 11a,b in such state-of-the-art packages are commonly formed with soft solder. These joining layers inside the power module heavily influence the reliability of the whole power module package, as they effect the attachment of both the device 1 to the substrate 3 and the substrate’s 3 attachment to the baseplate 8 or heatsink, and therefore any thermal or electrical transfers between these layers. Due to the long operational lifetime of some power modules, a highly reliable connection is therefore generally desirable between the substrate and any baseplate or heatsink. In existing designs such as those shown in Figures 1 and 2, a large joining area is generally applied between some component layers, to improve the mechanical stability of the module and the uniformity of heat transfer between each of the layers. However, the large area of joining material is vulnerable to thermo-mechanical stress and delamination during temperature swings, or thermal cycling. This thermo-mechanical stress and delamination may reduce the lifetime and reliability of a power module. Despite this, there is an increasing demand for high-temperature, high-power density and high-reliability power modules, for example modules that can operate in environments above 200°C. One reason for this is because of the increased use of wide-bandgap semiconductors such as SiC semiconductors, as the working junction temperature of SiC semiconductor devices can reach more than 400°C. A second reason is because the application requirements of power electronics operating in harsher environments, such as in electric vehicles, is gradually increasing. This poses a huge challenge to the reliability of the soft soldered joints, which then bottleneck the reliability of the power module as a whole. These issues are particularly prominent for applications which require repetitive temperature cycling and / or power cycling. 2 12729437-1 M&C Folio: PC932609WO Thus, with the increasingly common requirements for high-temperature, high-power density and high-reliability power modules, the soft solder attachment layer(s) are a common failure point for thermo-mechanical stresses. For example, soft soldering techniques for Tin (Sn) based solder alloys are commonly used for semiconductor-to-substrate and substrate-to- baseplate connections. The melting point of Sn-based soft soldering materials is typically between 230°C and 280°C, which means that the reliability of these solder joints generally cannot be guaranteed above 150°C, leading to degradation and instability of power modules during operations. Recently, new bonding technologies such as silver (Ag) sintering, Transient Liquid Phase Soldering (TLPS), and copper (Cu) sintering technologies have been adopted in power module packaging, with advantages such as higher operating temperatures, higher reliability, higher thermal and electrical performance, and lower process temperature over soft soldering techniques. However, the requirement for applying pressure in the sintering process complicates the power module manufacturing. In particular, when used in larger-area joints (such as sintering the substrate 3 to a baseplate 8 or heatsink), these sintering techniques often need to be performed under relatively high pressures, which increases processing cost and time. Another limitation of these sintering technologies is that they are currently only suitable for small area bonding such as bonding of semiconductor chips to the substrate. The sintering process and sintering materials currently available are unsuitable for the connection between the relatively large area required for substrate to baseplate or heatsink bonding. The Applicant has therefore recognised a need for a new substrate design to address these and other limitations, to thereby improve the long-term reliability of semiconductor power modules. Documents relevant to the field of the invention include: ^ JP4206915 B2; ^ US8921996 B2; ^ CN103035601 B; ^ Novel Large-Area Attachment for High-Temperature Power Electronics Module Application (Liu et al, 2017 IEEE 67th Electronic Components and Technology Conference (ECTC)); ^ Cu Sinter Pastes for Pure-Cu Die-Attach Applications of Power Modules (Eichinger et al, 2018 IEEE 20th Electronics Packaging Technology Conference (EPTC)); 3 12729437-1 M&C Folio: PC932609WO ^ The bonding properties of various surface finishes with Cu paste for pressure sintering (Jo et al, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC)); and ^ Nano-Cu sintering paste for high power devices die attach applications (Zhao et al, IEEE, 2017 12th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)). Summary Aspects and preferred features are outlined in the accompanying claims. Generally speaking, the present invention facilitates the use of improved bonding technologies such as pressure-less sintering, low pressure sintering, or TLPS bonding for bonding a substrate with a large metal (e.g. copper area) to a baseplate or heatsink, in the manufacturing of highly reliable, high operating temperature semiconductor power modules. By reducing a large bonding area into several smaller areas, the present invention facilitates the use of pressure-assisted or pressure-less sintering pastes for the substrate joining layers, and thereby improves the long-term reliability of semiconductor power modules. According to a first aspect of the present disclosure, there is provided a substrate for a semiconductor module, comprising: a first layer; a second layer, wherein the second layer comprises a first surface and an opposing second surface, and wherein the first layer is attached to the first surface; and a third layer comprising a plurality of sections separated by one or more channels, each section attached to the second surface. A substrate according to the present invention may be incorporated into the design of any semiconductor module comprising a semiconductor device, such as Si, SiC, GaN, IGBT, MOSFET, JFET, Diode, HEMT, FET or Cascode devices, and including but not limited to power semiconductor modules. In particular, but not exclusively, the substrate according to the present invention may be incorporated into a semiconductor module or package comprising a heatsink or a baseplate. To facilitate sintering for low pressure or pressure-less large area attachment, a substrate according the present disclosure comprises a third, lower or bottom layer with a grid pattern formed by sections or islands separated by channels. By providing a plurality of smaller area 4 12729437-1 M&C Folio: PC932609WO sections in place of a single larger continuous surface, the substrate facilitates the use of joining technologies that can greatly improve the reliability of connections which generally require a large surface area, such as between the substrate and a baseplate or heatsink. Examples of these joining technologies include, for example, pressure-less or pressure assisted sintering technology, and transient liquid phase bonding (TLPS) technology, among others. Thus, by replacing a single large-area bonding layer with a plurality of small-area bonding layers, the reliability of a joint between the substrate, and a baseplate or heatsink may be enhanced. The grid pattern of the bottom or third layer of the substrate may be designed according to the intended use of the substrate, for example the semiconductor module or packaging for which the substrate is intended to be used. In some implementations, at least two of the plurality of sections of the third layer have different surface areas and / or shapes. For example, some or all of the sections may be different shapes. Similarly, the separation between neighbouring sections, corresponding to a width of a channel separating the islands of the third layer, may vary. For example, two sections may be separated by a first distance, while a different two sections may be separated by a different second distance. By providing e.g. a non-symmetric grid pattern, the substrate may be designed to reduce or minimise a thermal resistance experienced by each semiconductor device to which it is attached. Additionally, or alternatively, at least two of the plurality of sections may have substantially identical surface areas and / or shapes. For example, some or all of the sections may be substantially identical in terms of shape and / or surface area, and / or some or all of the sections may have the same separation from neighbouring sections. In one implementation, the substrate is symmetric, with all sections of the third layer being substantially identical in terms of shape and surface area, and having equal separations to neighbouring sections. Such symmetric grid patterns may advantageously provide a more symmetrical thermal profile for the substrate in use. One or more of the plurality of sections of the third section may comprise corner areas that are rounded or chamfered. The layers of the substrate may comprise various materials. For example, the second layer (also called the middle layer) may comprise an insulating material, for example one or more of Al2O3, AlN, Si3N4, or any other ceramic material. The first layer (also called the top or 5 12729437-1 M&C Folio: PC932609WO upper layer) and third layer may comprise one or more metals, such as copper, aluminium or other materials suitable for a metallization layer of a semiconductor substrate. In one implementation, the first and third layers comprise copper, while the second layer comprises a ceramic material. The metal (first and third) layers of the substrate may be plated with a single metal or a combination of thin metal layers, to aid joining technology processes. The first layer may be connectable to one or more semiconductor devices by soldering or sintering technology. For example, the first layer may comprise a circuit connectable to one or more semiconductor devices. The substrate may be compatible with various joining technologies, including but not limited to: Vacuum reflow soldering by solder paste or by solder preform; Transient Liquid Phase Soldering / Sintering (TLPS); Diffusion soldering with pressure; Pressure-less silver (Ag) sintering; Pressure-assisted Ag sintering; Pressure-less copper (Cu) sintering; Pressure- assisted Cu sintering. For a substrate with a copper-based bottom or third layer, copper sintering is generally desirable to increase the reliability and lifetime of the power module, and pressure-less copper sintering in particular is desirable to further simplify the manufacturing process, without increasing the process or material cost of the power module. The channels forming the substrate grid pattern may be void of any material (e.g. providing an air gap between the islands or section of the third layer), or may otherwise comprise an insulating material, such as a thermally and / or electrically insulating material. A substrate according to the present disclosure may be incorporated into a semiconductor module or package, e.g. with a first surface attached to one or more semiconductor devices (e.g. via sintering or soldering), and a second surface of the substrate attached to a heatsink or baseplate. Thus, according to a second aspect of the invention there is provided a semiconductor module, comprising: a substrate comprising: a first layer; a second layer, wherein the second layer comprises a first surface and an opposing second surface, and wherein the first layer is attached to the first surface; and 6 12729437-1 M&C Folio: PC932609WO a third layer comprising a plurality of sections separated by one or more channels, each section attached to the second surface; one or more semiconductor devices attached to a surface of the substrate; and a heatsink or baseplate attached to an opposing surface of the substrate. In implementations, the one or more semiconductor devices may be attached to the first layer of the substrate, while the heatsink or baseplate may be attached to the third layer of the substrate. The smaller joining areas provided by the islands or sections of the third layer of the substrate facilitate the utilisation of e.g. Ag or Cu sintering technologies, without requiring the application of pressure or low pressure during the sintering process. The smaller sintered areas are therefore less vulnerable to thermo-mechanical stress and delamination, and as a result may prolong the lifetime of the power module. Additionally, the reduced size of the joining areas between the substrate and the baseplate or heatsink mean that the substrate and the joining material will generally experience less thermo-mechanical stress (e.g. due to temperature swings or thermal cycling), thereby further improving the long-term reliability of the power module. Thus, a semiconductor according to the present disclosure provides several advantages to power modules and power module manufacturing, without significantly impacting the cost of the module or substrate. Advantageously, no new joining technology or technique is required by a power module manufacturer to utilise the substrate design of the present disclosure in power module manufacturing. In implementations, the heatsink or baseplate is attached to the at least one of the plurality of sections of the third layer by sintering. The smaller areas of the islands or sections may be attached to the baseplate or heatsink by, for example, pressure assisted copper sintering, pressure-less copper sintering, pressure assisted silver sintering, transient liquid phase bonding technologies. These sinter materials may increase the thermal conductivity of the connection between the substrate and baseplate or heatsink, further reducing the thermo- mechanical stress and delamination due to temperature swings, and increasing the expected lifetime reliability of the power module. In implementations, the third layer of the substrate comprises one or more first channels in a first direction and one or more second channels in a second direction, and wherein the one or more semiconductor devices are positioned such that they do not overlap with the one or more 7 12729437-1 M&C Folio: PC932609WO first channels. Optionally, the one or more semiconductor devices may be positioned such that they also do not overlap with the one or more second channels. For example, the one or more semiconductor devices may each be attached to the first layer in a position corresponding to an island region or section of the third layer of the substrate, or otherwise be misaligned with the channels of the third layer. By aligning each of the semiconductor devices with the islands or sections of the third layer, the thermal resistance of the semiconductor modules (and therefore their temperature in operation) may be improved compared to no alignment of devices with island or section of the third layer. In implementations, the one or more semiconductor devices comprises a plurality of semiconductor devices, and a first at least two of the semiconductor devices are separated by a first distance while a second at least two of the semiconductor devices are separated by a second distance, wherein the first and second distances are not equal. By optimising a positioning of each semiconductor device in the module relative to each other and / or the channels of the third layer, the thermal resistance of the semiconductor devices (and therefore their temperature in operation) may be improved compared to no optimization of distances. Additionally, suitable placements of the semiconductor devices and channels may improve the symmetry of the semiconductor module in terms of thermal resistance. The semiconductor module may also comprise a second substrate. For example, the second substrate may be attached to the one or more semiconductor devices such that the one or more semiconductor devices are positioned or sandwiched between the substrate and the second substrate. The second substrate may be attached to a second heatsink or baseplate. The second substrate may be any suitable substrate, and in one implementation is a substrate comprising a first layer; a second layer, wherein the second layer comprises a first surface and an opposing second surface, and wherein the first layer is attached to the first surface; and a third layer comprising a plurality of sections separated by one or more channels, each section attached to the second surface, with the one or more semiconductor devices attached to the first layer of the second substrate. The second substrate may be attached to the second heatsink or baseplate via the third layer of the second substrate. Discussions above regarding substrates according to the present disclosure apply equally to the second substrate. According to a third aspect of the invention, there is provided a method of forming a substrate for a semiconductor module, the method comprising: 8 12729437-1 M&C Folio: PC932609WO forming a first layer; forming a second layer, wherein the second layer comprises a first surface and an opposing second surface, and wherein the first layer is attached to the first surface; and forming a third layer comprising a plurality of sections separated by one or more channels, each section attached to the second surface. According to a fourth aspect of the invention, there is provided a method of assembling a semiconductor module, the method comprising: providing a substrate comprising: a first layer; a second layer, wherein the second layer comprises a first surface and an opposing second surface, and wherein the first layer is attached to the first surface; and a third layer comprising a plurality of sections separated by one or more channels, each section attached to the second surface; attaching one or more semiconductor devices to a surface of the substrate; and attaching a heatsink or baseplate to an opposite surface of the substrate. Providing the substrate may comprise forming the substrate according to the third aspect of the invention. In implementations, attaching the heatsink or baseplate comprises attaching the heatsink or baseplate to at least one of the plurality of sections of the third layer by sintering. It will be understood that references to component being ‘attached’ or ‘joined’ to one another generally refers to the components being connected via one or more suitable joining techniques, such as sintering or soldering. Brief Description of the Figures Some preferred embodiments of the invention will now be described, by way of example only and with reference to the accompanying drawings, in which: Figures 1A-C illustrate a semiconductor module according to the state of the art. Figures 2A and B illustrate semiconductor modules with heatsinks according to the state of the art. 9 12729437-1 M&C Folio: PC932609WO Figures 3A and B illustrate a substrate for a semiconductor module according to an embodiment of the disclosure. Figure 4 illustrates a single sided cooling semiconductor module according to an embodiment of the disclosure. Figure 5 illustrates a double sided cooling semiconductor module according to an embodiment of the disclosure. Figures 6A and B illustrate a semiconductor module assembly according to an embodiment of the disclosure. Figures 7A and B illustrate an alternative semiconductor module assembly according to an embodiment of the disclosure. Figures 8A and B illustrate an alternative semiconductor module assembly according to an embodiment of the disclosure. Figure 9A-F illustrate various example substrate grid patterns according to embodiments of the disclosure. Detailed Description of the Preferred Embodiments Figure 3A illustrates a schematic cross-sectional view of a substrate 20 for a semiconductor module according to an embodiment of the disclosure. The substrate 20 comprises a middle (i.e. second) layer 21 joined to top or upper (i.e. first) and lower or bottom (i.e. third) metal layers 22, 23. The middle or second layer 21 is formed from a ceramic material, to provide advantageous thermal mechanical behaviour such as relatively high-heat conductivity, extended heat capacity and enhanced thermal spreading. However, it will be understood that middle layer 21 may be formed from or comprise any suitable material, such as polymers or metals. Similarly, the upper and lower metal layers 22, 23 are copper-based layers, but also may be formed from or comprise any suitable materials, such as aluminium or other metals. The layers 21, 22, 23 of the substrate 20 may be joined to one another via any suitable means or method, such as direct copper bonding (DCB) or active metal brazing or bonding (AMB). 10 12729437-1 M&C Folio: PC932609WO Instead of the bottom layer being a single large copper area as in Figure 1, the bottom layer 23 of the substrate of Figure 3 comprises a plurality of (metal) islands or sections 25 separated from one another by channels 24, which may be void of any material or comprise e.g. a thermally and / or electrically insulating material. Each island 25 is joinable to further layers, such as a baseplate or heatsink, via any suitable means, for example pressureless sintering techniques. Individually, the joining layers for each island 25 comprise a relatively small area compared to a single joining layer provided for the entirety of the layer 23, such as the joining layer 7 of Figure 1. As a result, the uniformity and quality of the joining layer for each island may be improved relative to a single joining layer with a large area. As shown in Figure 3B, the combination of islands 25 and channels 24 form a grid pattern. The grid pattern can be designed according to the size and thermal dissipation requirements of the semiconductor devices, and does not need to form a regular pattern such as that shown in Figure 3B. The pattern layout may be designed to ensure sufficient heat spreading from any semiconductor devices which may be e.g. attached to the top layer 22. For example, the grid shape may comprise varied separation gaps between the small areas 25. Thus, while all of the islands 25 and channels 24 illustrated in Figures 3A and B are uniform in size and shape, it will be understood that more generally any configuration of islands 25 and channels 24 may be used to provide a grid pattern suitable for the intended use of a given semiconductor module. For example, the optimal configuration of the lower metal layer 23, including as the size, shape and number of islands 25 and channels 24, may depend on the desired or intended number, size, layout and / or positioning of semiconductor chips in a semiconductor module, as will be discussed further below. Various example grid patterns are illustrated in Figures 9A-F. While the area of the joining layer for each island 25 is reduced relative to joining layer 7 of Figure 1, generally the total area of the joining layers for all islands 25 may not be significantly reduced relative to joining layer 7 of Figure 1 (for example, if the total area of the islands 25 is greater than the total area of the channels 24). This means that the use of a grid pattern for the lower metal layer 23 may generally facilitate an enhancement to the long term reliability of a semiconductor module, without a corresponding substantial reduction in the mechanical stability of the module. Figure 4 illustrates a schematic cross-sectional view of a semiconductor package 40 with single sided cooling. The module 41 comprises a substrate such as substrate 20 of Figures 3A and 3B and one or more semiconductor chips attached via a joining layer to the top layer 11 12729437-1 M&C Folio: PC932609WO of the substrate (e.g. layer 22 of substrate 20). The heatsink 42 is attached to the islands of the bottom layer 23 via multiple join layers 42, each corresponding to one of the islands of the bottom layer 23 as described above, by sintering or any other suitable joining means. Figure 5 illustrates a schematic cross-sectional view of a semiconductor package 50 with double sided cooling (DSC). In contrast to module 41 of Figure 4, module 51 comprises a first and second substrates attached to opposite sides of the semiconductor chip(s), such that the semiconductor chips or devices are sandwiched between first (lower) and second (upper) substrates. The second substrate is also a substrate such as substrate 20 of Figures 3A and B, but alternatively any other suitable substrate may be used. As with the first substrate, the top layer 22 of the second substrate is attached to the semiconductor chips, while the islands of the bottom layer 23 of the second substrate are attached to the upper heatsink 53b via joining layers 52b, to provide a semiconductor module 51 with double sided cooling. While the ‘top’ and ‘bottom’ layers of the second substrate are referred to as such for consistency with earlier descriptions, it will be understood that, in the orientation depicted in Figure 5, the ‘bottom’ layer of the upper (second) substrate is positioned above the ‘top’ layer of the upper substrate, forming a mirror image of the lower (first) substrate along the axis of the semiconductor devices. In both the single sided cooling and double sided cooling modules, indirect liquid cooling may be provided to maintain the semiconductor module at a desired or intended temperature during operations. However, double sided cooling may be preferred for some applications, as relative to single side cooling modules it facilitates improvements to the thermal stability of the module, thereby generally enhancing the module’s reliability. Various methods and technologies may be used to join the islands of the lower metal layer to a heatsink or baseplate, including but not limited to vacuum reflow soldering by solder paste, preform, Transient Liquid Phase Soldering / Sintering (TLPS), diffusion soldering with pressure, pressureless Ag or Cu soldering, and / or pressure assisted Ag or Cu sintering. One or more semiconductor devices may be attached to the top or first metal layer by any suitable means, for example by sintering or soldering. However, if the semiconductor chips are spaced uniformly across the substrate, and / or the grid pattern of the lower metal layer is uniform, some chips may experience reduced heat dissipation. This is because the channels 24 may disrupt the spreading of heat between the islands 25 of the lower metal layer 23. Various arrangements may be implemented to facilitate a reduction in this effect. 12 12729437-1 M&C Folio: PC932609WO Thermal simulations may be performed on substrate modules according to the present disclosure to optimise the designs of semiconductor packages for a given number of semiconductor chips. This may include optimizing one or more of the distance between channels and semiconductor chips, and / or the shape, number or size of islands 25, in order to facilitate a low and symmetrical thermal resistance. Figures 6-8 illustrate example simulation processed for optimising these factors such as those described above. Figure 6A illustrates a top-view of a first arrangement 60 of semiconductor devices according to an embodiment. The semiconductor module of Figure 6A comprises 12 semiconductor chips, including lower chips L1-L6 and upper chips U1-U6. The lower metal layer of the substrate comprises a first set of lateral channels 24a and a second set of longitudinal channels 24b. It will be understood that the references to ‘lateral’ and ‘longitudinal’ channels herein are provided for clarity with reference to the orientation of the device shown in Figure 6A, and are not intended to be limiting in nature. In the arrangement 60, the chips L1-L6 and U1-U6 are positioned so as to be misaligned with the longitudinal channels 24b of the lower metal layer. It will be appreciated that the misaligning of the semiconductor chips with the channels may comprise placing the channels away from the semiconductor chips, forming the third layer such that the channels are positioned away from the intended or desired location of the semiconductor chips, or a combination of the two. Figure 6B illustrates a graph depicting a thermal resistance of the upper chips U1-U6. The ‘Plain’ line depicts the thermal resistance of the upper chips in a state-of-the-art module, such as that depicted in Figure 1, with a single large area contiguous third metal layer that does not include any channels. The ‘Grid-Original’ line depicts a thermal resistance of the upper chips in a module formed with a substrate comprising a uniform grid pattern formed without regard for the placement of the chips. The ‘Grid-Improved strategy1’ line depicts a thermal resistance of the upper chips in the arrangement 60 of Figure 6A. As shown, by misaligning the upper chips with the longitudinal channels 24b, or otherwise separating the longitudinal channels from the semiconductor chips as far as possible, arrangement 60 facilitates a reduction in the thermal resistance of the semiconductor chips, as compared to the ‘uniformed grid pattern’ design where the channels are overlapped with the semiconductor chips. As shown in Figure 6B, in the arrangement 60, middle chips such as upper chips U2 and U5 may experience thermal coupling, and possess the highest thermal resistance (and therefore temperature) when in use. Figure 7A illustrates a top-view of a second arrangement 70 of 13 12729437-1 M&C Folio: PC932609WO semiconductor chips according to an embodiment. Like reference numerals are provided for the lateral and longitudinal channels. In arrangement 70, in addition to the misalignment of the semiconductor chips and longitudinal channels 24a described with reference to Figure 6A, the channels are positioned away from the middle chips L2-L5 and U2-U5 such that they do not overlap with any lateral or longitudinal channels. As illustrated in Figure 7B, positioning the semiconductor chips away the lateral channels 24b, or otherwise forming the lateral channels 24b away from the intended positions of the semiconductor chips, facilitates a reduction in the thermal resistances of the middle chips U2- U5. This is depicted by the ‘Grid-Improved strategy2’ line of this graph. The reduction in the thermal resistance is particularly pronounced for semiconductor chips which may otherwise have overlapped the lateral channels 24a, such as upper chips U2 and U5 in arrangement 60 of Figure 6A. Figure 8A illustrates a top-view of a third arrangement 80 of channels according to an embodiment. In this simulation, the size of the lateral channels 24a, along with the distance between the lateral channels 24a and the semiconductor chips L1-L6, U1-U6 grid, were progressively altered to optimise the size and shape of the grid islands on the third layer of the substrate, e.g. to make the size of the grid islands as small as possible without significantly impacting the thermal performance of the module so as to reduce or minimise the time and pressure required for the sintering process. In Figure 8B, each plot line Dsgn1-Dsgn5 corresponds to a potential grid configuration, with the ‘ny’ value (e.g. ny 7) representing the number of lateral channels 24a (i.e.7) and the ‘x’ value (e.g. x3mm) representing the distance between the longitudinal channels 24b and the semiconductor chips (i.e.3mm). As shown, by optimising the configuration of the grid (e.g. with respect to the shape, number and size of the grid islands and channels, and the separation of the channels from the semiconductor chips) as previously discussed, a low and symmetrical thermal resistance can be achieved. While the inclusion of the channels 24a in the third layer does result in a slight increase in the thermal resistance of the semiconductor chips relative to a single large layer (shown by the ‘Plain’ and ‘Upper-Plain’ plot lines), this increase falls well within the acceptable parameters for most applications. Thus, the substrate according to the present invention may facilitate the provision of a semiconductor package addressing the above described deficiencies of state-of-the-art semiconductor packages, without a substantial decline in the thermal performance of the semiconductor module. 14 12729437-1 M&C Folio: PC932609WO It will be understood that the bottom layer may not be a regular grid pattern. Instead, the shapes and / or sizes of the individual areas or islands may vary due to the substrate being designed according to the thermal dissipation requirements of the particular semiconductor devices. For example, the grid pattern may be designed according to the target of making the island area as small as possible to facilitate or enable pressureless or low-pressure sintering. The spacing (e.g. channel sizes) between the copper areas may also vary within the design for the same reason. Additionally, the corners of the island areas do not need to be provided at right angles, and may instead be, for example, rounded or chamfered. Figures 9A-F illustrate bottom-views of various arrangements for grid patterns of the semiconductor substrate, which may each be suitable for various configurations of semiconductor chips and / or intended uses. Figure 9A illustrates a grid pattern with symmetric islands and channels, such as that shown in Figure 3. Figure 9B illustrates an alternative grid pattern, in which the size of the islands of the grid pattern are varied. Figure 9C illustrates a further alternative grid pattern, in which both the size and spacing of the islands of the grid pattern are varied. Figure 9D illustrates a further alternative grid pattern, in which both the size and spacing of the islands of the grid pattern are varied to form an irregular pattern. Figure 9E illustrates a further alternative grid pattern, in which both the size and spacing of the islands of the grid pattern are varied and the islands corners of the islands are rounded. Figure 9F illustrates a further alternative grid pattern, in which both the size and spacing of the islands of the grid pattern are varied and the islands corners of the islands are chamfered. The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘upper’, ‘lower’, ‘above’, ‘overlap’, ‘under’, ‘lateral’, etc. are made with reference to conceptual illustrations of an apparatus, such as those showing standard cross- sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings. Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure, which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may 15 12729437-1 M&C Folio: PC932609WO be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein. 16 12729437-1

Claims

M&C Folio: PC932609WO CLAIMS:

1. A substrate for a semiconductor module, comprising: a first layer; a second layer, wherein the second layer comprises a first surface and an opposing second surface, and wherein the first layer is attached to the first surface; and a third layer comprising a plurality of sections separated by one or more channels, each section attached to the second surface.

2. The substrate of claim 1, wherein at least two of the plurality of sections have different surface areas and / or shapes.

3. The substrate of claim 1 or 2, wherein at least two of the plurality of sections have identical surface areas and / or shapes.

4. The substrate of any one of claims 1 to 3, wherein the plurality of sections are each separated from neighbouring sections by a same distance.

5. The substrate of any one of claims 1 to 3, wherein a first at least two of the plurality of sections are separated a first distance and a second at least two of the plurality of sections are separated by a second distance, wherein the first and second distances are not equal.

6. The substrate of any preceding claim, wherein: the first comprises a metal; the third layer comprises a metal; and / or the second layer comprises a ceramic material.

7. The substrate of claim 4, wherein the first and third layers comprise copper.

8. The substrate of any preceding claim, wherein one or more of the plurality of sections of the third section comprises corner areas that are rounded or chamfered.

9. A semiconductor module comprising: a substrate according to any preceding claim; one or more semiconductor devices attached to a surface of the substrate; and a heatsink or baseplate attached to an opposite surface of the substrate. 17 12729437-1M&C Folio: PC932609WO 10. The semiconductor module of claim 9, wherein the heatsink or baseplate is attached to the third layer of the substrate.

11. The semiconductor module of claim 10, wherein the heatsink or baseplate is attached to the at least one of the plurality of sections of the third layer by sintering.

12. The semiconductor module of any of any one of claims 9 to 11, comprising a second substrate, wherein the one or more semiconductor devices are attached to the second substrate such that the one or more semiconductor devices are positioned between the substrate and the second substrate.

13. The semiconductor module of claim 12, wherein the second substrate is a substrate according to any one of claims 1 to 8, and wherein the one or more semiconductor devices are attached to the first layer of the second substrate.

14. The semiconductor module of claim 12 or 13, wherein the second substrate is attached to a second heatsink or baseplate.

15. The semiconductor module of any one of claims 9 to 14, wherein the third layer of the substrate comprises one or more first channels in a first direction and one or more second channels in a second direction, and wherein the one or more semiconductor devices are attached to the first layer and positioned such that they do not overlap with the one or more first channels.

16. The semiconductor module of claim 15, wherein the one or more semiconductor devices are positioned such that they do not overlap with the one or more second channels.

17. The semiconductor module of any one of claims 9 to 16, wherein the one or more semiconductor devices comprise a plurality of semiconductor devices, and wherein a first at least two of the semiconductor devices are separated by a first distance and a second at least two of the semiconductor devices are separated by a second distance, wherein the first and second distances are not equal.

18. The semiconductor module of any one of claims 9 to 17, wherein the semiconductor module is a power semiconductor module.

19. A method of forming a substrate for a semiconductor module, the method comprising: 18 12729437-1M&C Folio: PC932609WO forming a first layer; forming a second layer, wherein the second layer comprises a first surface and an opposing second surface, and wherein the first layer is attached to the first surface; and forming a third layer comprising a plurality of sections separated by one or more channels, each section attached to the second surface.

20. A method of assembling a semiconductor module, the method comprising: providing a substrate comprising: a first layer; a second layer, wherein the second layer comprises a first surface and an opposing second surface, and wherein the first layer is attached to the first surface; and a third layer comprising a plurality of sections separated by one or more channels, each section attached to the second surface; attaching one or more semiconductor devices to a surface of the substrate; and attaching a heatsink or baseplate to an opposite surface of the substrate.

21. The method according to claim 20, wherein providing the substrate comprises forming the substrate according to the method of claim 19.

22. The method of claim 20 or claim 21, wherein attaching the heatsink or baseplate comprises attaching the heatsink or baseplate to at least one of the plurality of sections of the third layer by sintering. 19 12729437-1

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