Method for manufacturing a plate comprising two zones having a wettability contrast greater than 90° and plate thus manufactured

Abstract

The invention relates mainly to the field of 3D interconnection technologies for microelectronics, but also relates to any application requiring a strong wettability contrast on the micrometric scale. The proposed method makes it possible to manufacture a plate 1 comprising a main surface 10 having a solid area 101 and a micro- or nano-structured area 102 having, between them, a wettability contrast greater than 90°, and preferably greater than 120°, each structured area 102 extending around a solid area 101, the plate comprising a substrate 11 that comprises a first level 111 based on a semiconductor material and a second level 112 based on a dielectric material, the solid area and each structured area being formed in the second level of the substrate and each structured area having a plurality of pads based on the dielectric material 131, the plate being such that the pads have faceted ends.

Description

[0001] “Method for manufacturing a plate comprising two zones having a wettability contrast greater than 90° and plate thus manufactured”

[0002] TECHNICAL FIELD OF THE INVENTION

[0003] The present invention mainly relates to the field of 3D interconnection technologies for microelectronics, but can be concerned with any type of applications requiring a strong wettability contrast at the micrometric scale.

[0004] The present invention relates more particularly to the technique of self-assembly of chips by hybrid bonding in plate chips (or Die-To-Wafer (DTW) according to the English terminology).

[0005] The present invention finds a particularly advantageous application in the self-assembly of microelectronic components for their 3D integration. In the case of self-assembly, the invention may relate to the self-assembly of other types of chips than microelectronic chips, and in particular the self-assembly of microsystems, biological chips, fluidic devices, optical devices, etc.

[0006] STATE OF THE ART

[0007] 3D interconnect technologies have been developed to increase the number of features per unit area. Die-to-wafer (DTW) techniques are particularly attractive for heterogeneous 3D integration, which offers the advantage of assembling different technologies on the same host circuit or, equivalently, on the same functionalized host plate.

[0008] Current DTW processes are divided into two categories: a. Pick & Place processes: chips are picked up by a robot and aligned one by one on a wafer (hereinafter also called a target plate). However, in these processes, alignment accuracy is inversely proportional to the transfer rate; and b. Self-assembly processes: chips are transferred and roughly pre-aligned by Pick & Place equipment to the host plate. Fine alignment is achieved by the capillary forces of a liquid at the interface between the chip and a chip transfer area on the host plate.

[0009] More specifically, self-assembly involves depositing a drop of water on a hydrophilic transfer area of ​​a chip and then bringing the chip closer to achieve self-alignment using capillary forces between the two surfaces present on either side of the drop. This technique can improve both alignment accuracy and transfer rate. Chip transfer can also be performed individually or collectively.

[0010] Self-assembly therefore requires adaptations of the usual chip-to-wafer (DTW) integration, including the definition of hydrophilic and hydrophobic zones on the target wafer, preferably with a strong surface energy contrast between the two.

[0011] It should be noted here that the hydrophilic, hydrophobic and super-hydrophobic characteristics of the surfaces are characterized by their drop angle values ​​which are respectively less than 90°, between 90 and 120°, and greater than 120°.

[0012] With reference to Figure 1, one of the ways of creating this wettability contrast (difference between the drop angle a of the transfer zone 101 of a chip and the drop angle P of the zone 102 surrounding the transfer zone 101) is to generate: a. a step (or "mesa" according to English terminology) 15, generally several micrometers thick, on the surface 10 of the receiving plate 1, so that the upper surface of the step 15 constitutes a receiving zone 101 of a chip, and / or b. a step, generally several micrometers thick, on the surface of each chip to be transferred, and / or c. a chemical contrast, between each reception area 101 on the surface of the reception plate 1 and the inter-chip area 102 which surrounds each reception area 101, or even between the reception area 101 on the surface of the reception plate 1 and the rest of the surface of the reception plate 1, by means of a hydrophilic layer 1000 on the upper surface of each step, and / or d.a chemical contrast, between the reception zones 101 on the surface of the reception plate 1 and the inter-chip zones 102, by means of a hydrophobic layer 1001 which covers at least the inter-chip zones 102 and where appropriate the periphery of each step 15.

[0013] Wettability contrasts of the order of 90° can thus be obtained.

[0014] To generate, on the surface of the host plate, a wettability contrast between the areas hosting the chips to be transferred and the areas surrounding these hosting areas, it is still possible to generate, at least at the level of the areas surrounding the hosting areas, a micro- or nano-structured surface, that is to say a surface having a micro- or nano-roughness, in particular creating the conditions for observing a lotus effect. In particular when such a surface structuring is also associated with the presence of a chemically hydrophobic coating, it is possible to achieve wettability contrasts greater than 120°. Super-hydrophobicity is then achieved which allows for better alignment precision.

[0015] It is thus known from the article entitled “Surface-Tension-Driven Self-Alignment of Microchips on Black-Silicon-Based Hybrid Template in Ambient Air” by Ali Shah et al. and published in JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 22, NO. 3, JUNE 2013, 739, a process for manufacturing hydrophilic receptor sites surrounded by their super-hydrophobic surface by means of dry etching of Si obtained by deep reactive ion etching (or “Deep Reactive Ion Etching” according to the English terminology) which makes it possible to obtain black silicon (or “Black Silicon” according to the English terminology), that is to say a very rough silicon surface made of small needles.

[0016] However, achieving such a superhydrophobic surface reproducibly by deep reactive ion etching is not easy. In addition, black silicon can generate a significant amount of silicon debris that detaches, in the form of particles, from the surface because the generated microneedles are very irregular and in places fragile. This is therefore a significant disadvantage for the hybrid bonding technique which requires a surface that is as clean as possible and free of particles.

[0017] Additionally, the method described in the aforementioned article requires access to the substrate silicon in the inter-chip areas, which may involve removing all materials deposited on the target wafer during circuit fabrication. This can be complicated and costly depending on the complexity of the material stacks, particularly in the upper levels of the host wafer that are usually functionalized for use as interconnect levels between the target wafer and the chips.

[0018] An object of the present invention is therefore to propose a method for manufacturing a plate, comprising a main surface having at least one solid zone and a micro- or nano-structured zone having, between them, a wettability contrast greater than 90°, and preferably greater than 120°, each micro- or nano-structured zone extending around a solid zone, which makes it possible to overcome at least one of the drawbacks of the prior art.

[0019] An object of the present invention is more particularly to propose such a method resulting in the manufacture of a plate suitable for the self-assembly of chips by hybrid bonding of the chip-to-plate type.

[0020] Other objects, features, and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated.

[0021] SUMMARY OF THE INVENTION

[0022] To achieve this objective, according to one embodiment, a method is provided for manufacturing a plate comprising a main surface having at least one solid zone and a micro- or nano-structured zone having, between them, a wettability contrast greater than 90°, and preferably greater than 120°, each micro- or nano-structured zone extending around a solid zone, the method comprising the following steps: a. Providing a substrate comprising a first level based on a semiconductor material and a second level based on a dielectric material, the second level extending over the first level, b.Forming, on an exposed surface of the second level of the provided substrate, a layer based on a sacrificial material, such as a resin, having at least a first zone on which extends a solid layer based on said sacrificial material and a second zone having a surface structured by a plurality of micrometric or nanometric pads based on said sacrificial material, each first zone being surrounded by a second zone and each first zone extending over a surface, of at least one order of magnitude, greater than a micrometric or nanometric surface on which extends each pad based on said sacrificial material, then c.Etching a portion of the layer based on said previously formed sacrificial material and a portion of the second level of the substrate, so as to form, in the second level of the substrate, said at least one solid zone at each first zone and each micro- or nano-structured zone at each second zone, each micro- or nano-structured zone having a plurality of pads based on said dielectric material which corresponds to the plurality of pads based on said sacrificial material.

[0023] Among the advantages that arise from the manufacturing process as introduced above, we can cite the following: a. The shape, size and density of the pads made of a dielectric material are perfectly controlled and adjustable since they are determined by the pattern drawn by the layer based on said sacrificial material. In the same way, the distance between the solid zone and the micro- or nano-structured zone is also perfectly controlled and adjustable since it is defined by the pattern drawn by the layer based on said sacrificial material; and / or b. This avoids generating a solid zone, or step, having a very significant thickness on the surface of the plate, this step being nevertheless obtained in such a way as to contribute to achieving a strong wettability contrast between the solid zone (or step) and the micro- or nano-structured zone.

[0024] Optionally, the first aspect of the invention may further have at least any one of the following features which may be taken separately or in combination:

[0025] According to one example, the etching can be continued, by over-etching, until the pads based on said sacrificial material are completely removed. The difference in size (of an order of magnitude) between each solid layer based on said sacrificial material and each pad based on said sacrificial material explains why the sacrificial material constituting the pads based on said sacrificial material is consumed more quickly by the etching than the sacrificial material constituting each first zone by a “faceting” phenomenon which consists of a lateral consumption of the sacrificial material which is added to its consumption from above. This gives pads based on dielectric material with faceted ends, and for example in the shape of needles.Compared to a drop angle obtained with flat stud heads, this angle being substantially equal to 130°, the faceted head of the studs obtained following over-etching makes it possible to advantageously achieve a drop angle substantially equal to 160°. A better hydrophobic effect is therefore obtained.

[0026] According to another example, the formation of the layer based on said sacrificial material may comprise a photolithography step. It then appears that it is sufficient to apply, on the substrate provided, a single level of photolithography to enable the production of a plate having at least two zones having, between them, a wettability contrast greater than 90°, and preferably greater than 120°. In addition, the etching step making it possible to generate the microroughness then falls under a standard and perfectly mastered technique of microelectronics, which generates neither defects nor particles. It is very easy to integrate into a manufacturing process of a host plate intended for the transfer of chips by hybrid bonding of the chips and implements the same types of equipment as the manufacturing techniques of the substrate provided.

[0027] According to another example, the etching may be stopped before obtaining complete removal of the layer based on said sacrificial material at each first zone, the layer based on said sacrificial material remaining at each first zone preferably having a thickness of between 100 nm and 5 μm. Preferably, the etching comprises exposure to an etching plasma or to ion etching.

[0028] According to another example, the manufacturing method according to the first aspect of the invention may further comprise, following the etching, the deposition of a layer, preferably conformal, based on a hydrophobic material, hereinafter referred to as "hydrophobic layer". For example, the hydrophobic material based on which the hydrophobic layer is made is preferably based on at least one polymer. It comprises, for example, a fluorosilane polymer at 0.1% by mass in a hydrofluoroether carrier solvent. For example, the deposition of the hydrophobic layer comprises a spin coating step or a plasma deposition step.

[0029] According to another example, the manufacturing method according to the first aspect of the invention may further comprise a step of removing a portion of the layer based on said sacrificial material which remains in line with the first zone after etching, so as to expose a surface of the second level of the substrate which is located in line with each first zone.

[0030] According to an example related to the two previous examples, the deposition of the hydrophobic layer can be implemented before the complete removal of the part of the layer based on said sacrificial material which remains at the right of the first zone after the etching. Thus, the complete removal (or "lift-off" according to the English terminology) of the part of the layer based on said sacrificial material which remains at the right of the first zone results in the removal of the layer based on a hydrophobic material at the right of the solid zone. Therefore, provided that the material based on which the second level of the substrate is made is hydrophilic, the wettability contrast between the solid zone (or step) and the micro- or nano-structured zone is advantageously significantly increased.

[0031] According to another example, the plate may constitute a receiving plate intended for the attachment of microelectronic components, such as microelectronic chips, by hybrid bonding, each solid zone being intended to accommodate a microelectronic component and each micro- or nano-structured zone being intended to constitute at least part of a zone between microelectronic components.

[0032] According to the previous example, the second level of the substrate comprising at least one level of electrical interconnections extending at least in line with each solid area and extending where appropriate from a solid area to an adjacent micro- or nano-structured area, the etching can be stopped before reaching said at least one level of electrical interconnections. The method thus makes it possible to preserve the integrity of the insulating and metallic materials which can be very numerous in the interchip areas and which would be difficult to remove by etching given their variety.

[0033] A second aspect of the invention relates to a plate comprising a main surface having at least one solid zone and one micro- or nano-structured zone having, between them, a wettability contrast greater than 90°, and preferably greater than 120°, each micro- or nano-structured zone extending around a solid zone, the plate comprising a substrate which comprises a first level based on a semiconductor material and a second level based on a dielectric material, the second level extending over the first level, said at least one solid zone and each micro- or nano-structured zone being formed in the second level of the substrate and each micro- or nano-structured zone having a plurality of pads based on said dielectric material, the plate being essentially such that the pads based on said dielectric material have faceted ends.

[0034] The plate according to the second aspect of the invention makes it possible to obtain an even greater wettability contrast relative to that offered by a plate supporting pads each taking the form of a pillar whose section remains substantially constant from the base to the top.

[0035] A third aspect of the invention relates to a method for self-assembling microelectronic components using a wafer according to the second aspect of the invention. For example, a plurality of microelectronic components, such as microelectronic chips, are self-assembled on the wafer by hybrid chip-to-wafer bonding.

[0036] A fourth aspect of the invention relates to an assembly comprising a plate according to the second aspect of the invention and a plurality of microelectronic components, such as microelectronic chips, assembled on the plate by hybrid bonding.

[0037] BRIEF DESCRIPTION OF THE FIGURES

[0038] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0039] Figure 1 schematically represents a sectional view of a part of an embodiment of a reception plate according to the prior art.

[0040] Figure 2 schematically represents a sectional view of a part of an embodiment of a host plate according to the invention and a microelectronic chip located opposite the surface of the host plate via which the microelectronic chip is intended to be assembled by hybrid bonding to the host plate.

[0041] Figures 3A to 3E schematically illustrate the different steps of an embodiment of the method for manufacturing the docking plate illustrated in Figure 2.

[0042] Figure 4A schematically illustrates a top view of an embodiment of a reception plate according to the invention.

[0043] Figure 4B illustrates an enlargement on four pads made of a dielectric material of the embodiment of the receiving plate according to the invention which is illustrated in Figure 4A.

[0044] Figures 5A and 5B represent perspective photos of pads made of a dielectric material obtained by implementing an embodiment of the manufacturing method according to the first aspect of the invention, respectively without over-etching and with over-etching.

[0045] Figure 6A represents a perspective photo of a portion of a receiving plate according to the invention comprising pads made of a dielectric material and covered with a layer of a hydrophobic material which were obtained by implementing an embodiment of the manufacturing method according to the first aspect of the invention.

[0046] Figure 6B represents a perspective photo of a portion of a reception plate according to the invention comprising a reception step obtained by implementing an embodiment of the manufacturing method according to the first aspect of the invention, the hydrophobic layer covering the sides of the step and the bottom of the main surface of the substrate, but not the upper surface of the step.

[0047] Figure 7 schematically represents a sectional view of a part of an embodiment of a docking plate according to the invention and of a microelectronic chip located opposite the surface of the docking plate via which the microelectronic chip is intended to be assembled by hybrid bonding to the docking plate. Figure 7 corresponds substantially to Figure 2, except that it also represents the electrical interconnection levels of the docking plate and the microelectronic chip.

[0048] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily to the scale of practical applications. In particular, the thicknesses of the different layers illustrated in the figures are not representative of reality.

[0049] DETAILED DESCRIPTION OF THE INVENTION

[0050] Before commencing a detailed review of embodiments of the invention, optional features which may optionally be used in combination or alternatively are set out below:

[0051] According to one example, the dielectric material from which the second level of the provided substrate is made is an oxide of the material from which the first level of the substrate is made.

[0052] As an alternative or in addition to the previous example, the material from which the first level of the substrate and / or the second level of the substrate is made is chosen from: silicon, germanium, sapphire, etc.

[0053] According to an example of the first aspect of the invention, the photolithography step comprises the following substeps: a. Depositing a layer based on said sacrificial material, for example based on a photosensitive resin, solid on the exposed surface of the second level of the substrate provided, b. Exposing the layer based on said sacrificial material to light radiation through a photolithography mask structured so as to define a negative or a positive of a micro-structuring of said layer based on said sacrificial material, then c. Chemically etching the layer based on said sacrificial material so as to obtain the micro-structuring of said layer based on said sacrificial material.

[0054] As an alternative to the previous example, the formation of the layer based on said sacrificial material comprises a screen printing step or an electron beam photolithography step.

[0055] According to another example of the first aspect of the invention, the deposition of the hydrophobic layer can be configured so that the hydrophobic layer covers each pad based on said dielectric material and each space between the pads based on said dielectric material of the same plurality, or even where appropriate the lateral edges of each solid zone.

[0056] According to another example of the first aspect of the invention, the layer based on said sacrificial material can be formed so as to have a substantially constant thickness of between 200 nm and 5 pm, preferably between 500 nm and 1.5 pm, and even more preferably substantially equal to 800 nm.

[0057] According to another example of the first aspect of the invention, the layer based on said sacrificial material can be formed so that each solid zone has at least one transverse dimension of between 100 pm and 20,000 pm, preferably between 500 pm and 5,000 pm, and even more preferably substantially equal to 2,000 pm.

[0058] According to another example of the first aspect of the invention, the layer based on said sacrificial material can be formed so that two adjacent pads of the same plurality are spaced apart by a distance of between 100 nm and 1 pm, preferably between 200 nm and 800 nm, and even more preferably substantially equal to 500 nm.

[0059] According to another example of the first aspect of the invention, the etching is configured so that each pad based on said dielectric material has a height of between 100 nm and 5 pm, preferably between 400 nm and 2.5 pm, and even more preferably substantially equal to 1 pm.

[0060] According to one example, the pads based on said dielectric material of each plurality may be distributed in a matrix manner over the micro- or nano-structured area concerned and / or may have octagonal-shaped sections of characteristic size substantially equal to 500 nm and / or are spaced apart by a minimum distance substantially between 300 nm and 1 pm.

[0061] According to an example of the second aspect of the invention, the plate may further comprise a hydrophobic layer covering each pad based on said dielectric material and each space between the pads based on said dielectric material of the same plurality, or even where appropriate the lateral edges of each solid zone, and not covering said at least one solid zone.

[0062] According to another example of the second aspect of the invention: a. each pad based on said dielectric material may have a height of between 100 nm and 5 pm, preferably between 400 nm and 2.5 pm, and even more preferably substantially equal to 1 pm, and / or b. each pad based on said dielectric material may have at least one transverse dimension of between 100 nm and 2 pm, preferably between 200 nm and 1 pm, and even more preferably substantially equal to 500 nm, and / or c. two pads based on said dielectric material adjacent to each other of the same plurality may be spaced apart by a distance of between 100 nm and 1 pm, preferably between 200 nm and 800 nm, and even more preferably substantially equal to 500 nm.

[0063] According to another example of the second aspect of the invention, the plate can constitute a receiving plate intended for the transfer of microelectronic components, such as microelectronic chips, by hybrid bonding, each solid zone being intended to receive a microelectronic component and each micro- or nano-structured zone being intended to constitute at least part of a zone between microelectronic components.

[0064] According to another example of the second aspect of the invention, the second level of the substrate may comprise at least one level of electrical interconnections extending at least in line with each solid zone and extending where appropriate from a solid zone to an adjacent micro- or nano-structured zone, the electrical interconnections being flush with the second level of the substrate from an exposed surface of each solid zone and extending from each solid zone at least to the adjacent micro- or nano-structured zone, and extending more particularly below the plurality of pads based on said dielectric material of said adjacent micro- or nano-structured zone, being encapsulated in the dielectric material based on which the second level of the substrate is made.

[0065] Hybrid bonding refers to bonding between hybrid surfaces, i.e., surfaces composed of several materials. In the case of 3D interconnections, these materials can be Cu (for electrical contacts) and SiO2 (to insulate the contacts from each other). Hybrid bonding can be performed in wafer-to-wafer mode or in die-to-wafer mode.

[0066] A "plot with a faceted end" means a plot whose cross-section decreases from its base or from a non-zero distance to its base, and to its end opposite its base. For example, the plot may have an end in the shape of an ogive or a pinhead. A "micro- or nano-structured area" means an area with micro-structuring, that is, elements that are distinguished by their characteristic micro- or nano-metric size. This essentially refers to an area with a micro- or nano-structured surface.

[0067] A "solid area" means an area defined in contrast to a micro- or nano-structured area, as an area having a smooth (or flat) surface in the sense that its roughness is much lower, for example by at least one order of magnitude, than the roughness related to the micro-structuring of the surface of the micro- or nano-structured area. For example, the solid area has a surface roughness of less than 0.3 nm.

[0068] A film based on a material A means a film comprising this material A and possibly other materials.

[0069] A parameter that is "substantially equal to / greater than / less than" a given value means that this parameter is equal to / greater than / less than the given value, within plus or minus 20% or even 10% of this value. A parameter that is "substantially between" two given values ​​means that this parameter is at least equal to the smallest given value, within plus or minus 20% or even 10% of this value, and at most equal to the largest given value, within plus or minus 20% or even 10% of this value.

[0070] In its broadest acceptance, and with reference to Figure 2, the first aspect of the invention relates to a method for manufacturing a plate 1 comprising a main surface 10 having at least one solid zone 101 and a micro- or nano-structured zone 102, hereinafter “structured zone 102”. These zones have between them a wettability contrast, which is defined as the difference between the drop angle a associated with the solid zone 101 and the drop angle p associated with the structured zone 102, greater than 90°, and preferably greater than 120°. Furthermore, each structured zone 102 extends around a solid zone 101.

[0071] This acceptance makes it possible to define a plate and its manufacturing process intended not only to accommodate by transfer microelectronic components 2, such as microelectronic chips, for their hybrid bonding on the plate, but also any other type of application, and in particular any type of application requiring a strong wettability contrast at the micrometric scale.

[0072] Thus, if subsequently, the invention is described in the context of its main application, that is to say in the context of an application to the self-assembly of microelectronic components 2 on the plate 1 by hybrid bonding of the chip-to-plate type, the invention is not limited to this application.

[0073] An embodiment of the manufacturing method according to the first aspect of the invention is described below with reference to Figures 3A to 3E.

[0074] The first step of this method consists in providing a substrate 11 comprising a first level 111 based on a semiconductor material and a second level 112 based on a dielectric material, the second level 112 extending over the first level 111, so as to have an exposed surface 1121. In the illustrated example, the semiconductor material from which the first level 111 is made is silicon and the dielectric material from which the second level 112 is made is silicon oxide. However, the dielectric material from which the second level of the provided substrate is made is not necessarily an oxide of the material from which the first level of the substrate is made.Furthermore, other semiconductor materials than silicon are envisaged, provided, for example, that they can be structured by photolithography and dry etching techniques potentially involved in the implementation of the method according to the first aspect of the invention; this will typically be the case for germanium, sapphire, etc. Note here that the second level 112 of the substrate 11 has a thickness e less than 10 μm; this thickness e will also be greater than the height of the pads 131 based on the dielectric material that the method makes it possible to manufacture on the surface of the substrate 11; it will even, where appropriate, be greater than the height of the pads 131 and the height of a level of electrical interconnections 110 buried in the dielectric material of the second level 112 (see figure 7).The dielectric pads 131 may in fact be intended to be formed in an upper layer of the second level 112 of the substrate 11 which is free of any electrical interconnection, so that their formation makes it possible to preserve the integrity of said electrical interconnections when they exist.

[0075] With reference to Figure 3B, the method according to the first aspect of the invention further comprises the formation, on the exposed surface 1121 of the second level 112 of the substrate 11, of a layer based on a sacrificial material 12, hereinafter “sacrificial layer 12”. The sacrificial material may be a resin, and more particularly a photosensitive or thermosetting or electrosensitive resin (in the case of electronic photolithography). The sacrificial layer 12 is formed so as to have a first zone 1201 on which extends a solid layer 121 based on said sacrificial material and a second zone 1202 on which extends a plurality of micrometric or nanometric pads 122 based on said sacrificial material, hereinafter “sacrificial pads 122”.In Figure 3B, a second zone 1202 has been shown on either side of the first zone 1201, but Figure 3B illustrates a sectional view, and each first zone 1201 is in fact surrounded by a second zone 1202. Figure 4A offers a top view of an embodiment of a plate 1 according to the second aspect of the invention in which it appears that each solid zone 101 is actually surrounded by a structured zone 102, which assumes a corresponding distribution of each first zone 1201 and of the second zone 1202 which surrounds it.Let us note here that figure 4A also makes it possible to illustrate that a receiving surface of a microelectronic component 2 is not necessarily circular or square, but can accommodate variations in shape, it being understood that it is foreseeable that the more significant the shape ratio of this receiving surface, the greater the risk of obtaining an imprecise alignment of the microelectronic component 2 on the receiving surface.

[0076] Furthermore, each first zone 1201 extends over a surface area greater than a micrometric or nanometric surface area over which each sacrificial pad 122 extends. Preferably, the surface area of ​​each first zone 1201 is at least one order of magnitude greater than the surface area over which each sacrificial pad 122 extends. Note here that, if, in the illustration provided in FIG. 3B, all the sacrificial pads 122 have the same dimensions and are regularly spaced, any variation of this matrix arrangement is conceivable, provided that it allows the manufacture of a plate 1 according to the second aspect of the invention. It is in particular conceivable that the sacrificial layer 12 obeys a design making it possible to have ultimately density gradients of dielectric pads 131 on the surface of a structured zone 102, which would make it possible to have wettability gradients between joint surfaces.

[0077] As we will see below, the surface over which each first zone 1201 extends is intended to form a surface for receiving a microelectronic component 2; its dimensions are therefore essentially constrained by the dimensions of said microelectronic component 2, or by those of a step formed on the surface of the microelectronic component 2 defining a surface for transferring said component to the plate 1. In this sense, the sacrificial layer 12 can be formed so that each solid zone 1201 has at least one transverse dimension of between 100 pm and 20,000 pm, preferably between 500 pm and 5,000 pm, and even more preferably substantially equal to 2,000 pm.

[0078] The dimensions of the sacrificial pads 122 are constrained by the desired objective achieved in terms of wettability contrast between the solid zone 101 and the structured zone 102 of the main surface 10 of the plate 1. The sacrificial pads 122 have dimensions which predetermine those of the pads made of a dielectric material 131, hereinafter “dielectric pads 131”, which we describe below, and the dimensions of the spaces which separate these dielectric pads 131 from each other; these dimensions, defining the drop angle p at the surface of the micro-structuring produced by the dielectric pads 131, therefore influence the wettability contrast that the manufactured plate 1 will present.

[0079] The dimensions of the dielectric pads 131 and of the spaces which separate these pads from each other are preferably such that: a. each sacrificial pad 122 has at least one transverse dimension of between 100 nm and 2 pm, preferably between 200 nm and 1 pm, and even more preferably substantially equal to 500 nm, and / or b. two sacrificial pads 122 adjacent to each other of the same plurality are spaced apart by a distance of between 100 nm and 1 pm, preferably between 200 nm and 800 nm, and even more preferably substantially equal to 500 nm.

[0080] Furthermore, the sacrificial layer 12 is preferably formed so as to have a substantially constant thickness of between 200 nm and 5 pm, preferably between 500 nm and 1.5 pm, and even more preferably substantially equal to 800 nm. As we will see below, the thickness of the sacrificial layer 12 determines, together with its nature and the etching method implemented, the height of the dielectric pads 131, and therefore influences the wettability contrast that will be obtained.

[0081] Although it is preferable for the sacrificial layer 12 to have a substantially constant thickness between the different solid 101 or structured 102 zones, the manufacturing method according to the first aspect of the invention is not limited thereto. For example, the sacrificial layer 12 could be formed so that the thickness of the sacrificial layer 12 on each solid 101 zone is greater than the height of the sacrificial pads 122, so as, for example, to be able to push the over-etching described below further, without consuming all the sacrificial material present, before the over-etching, on each solid 101 zone.

[0082] According to a preferred embodiment of the manufacturing method according to the first aspect of the invention, the formation of the sacrificial layer 12 comprises a photolithography step, that is to say a standard, controlled and largely modular step of microelectronics. Let us nevertheless specify that such a photolithography step can comprise the following substeps: a. Depositing a solid layer based on said sacrificial material on the exposed surface 1121 of the second level 112 of the substrate 11 provided, b. Exposing the layer based on said sacrificial material to light radiation through a photolithography mask structured so as to define a negative or a positive of the desired micro-structuring of the layer based on said sacrificial material, then c. Chemically etching the layer based on said sacrificial material so as to obtain the desired micro-structuring.

[0083] Alternatively, the formation of the layer based on said sacrificial material comprises at least one screen printing step.

[0084] With reference to Figure 30, the method according to the first aspect of the invention further comprises the etching of a portion of the previously formed sacrificial layer 12 and a portion of the second level 112 of the substrate 11. The etching is more particularly such that a solid zone 100 is formed in the second level 112 of the substrate 12 at each first zone 1201 and a structured zone 102 at each second zone 1202, each structured zone 102 having a plurality of dielectric pads 131 which corresponds, as announced above, to the plurality of sacrificial pads 122, and each dielectric pad 131 having a section whose dimensions and shape correspond to those of the sacrificial pad 122.For example, with reference to Figures 4A and 4B, if the sacrificial pads 122 have an octagonal section of characteristic size A equal to 500 nm between two opposite edges and are spaced apart by a minimum distance B of between 300 nm and 1 pm, the corresponding dielectric pads 131 will have the same octagonal section and will be spaced apart by the same minimum distance. Other shapes are obviously possible (round, square, etc.).

[0085] The plurality of dielectric pads 131 extending from each structured area 102 gives the exposed surface of the structured area 102 its superhydrophobic character, creating the conditions for observing a lotus effect. However, the superhydrophobic character that the plurality of dielectric pads gives to the exposed surface of each structured area 102 will be more or less pronounced depending on how the etching is carried out.

[0086] In the field of microelectronics, the standard implementation of such etching, whether related to exposure to an etching plasma or to ion etching, would aim at the formation of pillars such as illustrated in FIG. 5A. These pillars, which each have a substantially constant section from their base to their top, can be identified with the dielectric pads 131. However, it is preferable, in order to increase the wettability contrast between a solid zone 101 and the structured zone 102 which surrounds it, that the dielectric pads 131 have a cross-section which decreases from its base or from a non-zero distance to its base, and up to its top. For example, it is preferable that each dielectric pad 131 has an end in the shape of an ogive or a pinhead, as illustrated in FIG. 5B.To obtain this advantageous shape of the dielectric pads 131, the etching can simply be continued, beyond what is done in a standard manner, until a complete removal of the sacrificial pads 122 is obtained; one can then speak of over-etching, as already mentioned above. Thus, an etching step pushed sufficiently far, and more particularly pushed beyond the standard (which only provides for a partial consumption of the sacrificial material), so that the sacrificial material constituting the sacrificial pads 122 is completely consumed by the etching alone, makes it possible to obtain dielectric pads 131 with a pointed head such as illustrated in FIG. 5B conferring, on the structured zone 102, a superhydrophobic character, with a drop angle substantially equal to 160°, advantageously increased relative to that which would confer, on the structured zone 102, dielectric pads with a flat head such as illustrated in FIG. 5A.

[0087] The difference, of at least one order of magnitude, between the transverse dimensions of the solid layer 121 and those of each sacrificial pad 122 makes it possible to achieve this result. Indeed, it is observed that then the sacrificial material is more quickly consumed, during etching, on the narrow patterns that constitute the sacrificial pads 122, than is the sacrificial material of the largest pattern that constitutes the solid layer 121. Thus, at the end of the over-etching, there remains, as illustrated in FIG. 3C, a solid layer 121' of thickness less than the solid layer 121 at the level of the solid zone 101. This observation can be explained as being due to a faceting phenomenon.This phenomenon reflects the fact that, during etching, in addition to the consumption from above of the sacrificial material and the dielectric material from which the second level 112 of the substrate 11 is made, there is a lateral consumption of these materials; however, the lateral consumption is increased on small patterns relative to larger patterns, when the same etching is applied to them. Note that in FIG. 3C, the consequences of the faceting phenomenon on the shape of the dielectric pads 131 formed are roughly diagrammed by illustrating each pad in the form of a cone section.

[0088] However, the extension of the engraving, beyond the standard, is preferably limited above, and this, at least for the two reasons given below.

[0089] The first of these two reasons is that it is indeed advantageous for the etching to be stopped before obtaining complete removal of the sacrificial material at the level of each first zone 1201. In this way, at the end of etching, and more particularly at the end of over-etching, a thickness of the sacrificial material remains at the level of each first zone 1201, this thickness preferably being between 100 nm and 5 pm.

[0090] The second of the two reasons for not extending the etching, beyond obtaining complete removal of the sacrificial material 12 at the level of each second zone 1202, is that the dielectric pads 131 would be reduced in size, and in particular in height; however, it is preferable for the etching to be configured so that each dielectric pad 131 has a height of between 100 nm and 5 pm, preferably between 400 nm and 2.5 pm, and even more preferably substantially equal to 1 pm.

[0091] With reference to Figure 3D, the method according to the first aspect of the invention may further comprise, following the etching, the deposition of a layer, preferably conformal, based on a hydrophobic material 14, hereinafter “hydrophobic layer 14”. For example, the hydrophobic material, based on which the hydrophobic layer 14 is made, is preferably based on at least one polymer. It comprises for example a fluorosilane polymer at 0.1% by mass in a hydrofluoroether carrier solvent. For example, it may be the coating known under the commercial name: Ultra Fine Electronic Grade Novec™ 1720 from 3M™. Any material known for its hydrophobic properties in the context of the present invention is conceivable, and the examples given above are not limiting of the invention. For example, the deposition of the hydrophobic layer includes a spin coating step or a plasma deposition step.Of course, the hydrophobic layer 14 advantageously helps to increase the wettability contrast between the solid zone 101 and the structured zone 102.

[0092] Preferably, and as illustrated in FIGS. 6A and 6B, the deposition of the hydrophobic layer 14 is configured so that the hydrophobic layer 14 covers each dielectric pad 131 and each space 132 between the dielectric pads 131 or between the dielectric pads and the step 15 that constitutes the solid zone, or even where appropriate the lateral edges 1011 of said step 15. Note that it appears here that if it is advantageous to push the etching until consuming all the sacrificial material at the right of the second zones 1202 to obtain faceted dielectric pads 131, such over-etching is also advantageous in that it allows the deposition of the hydrophobic layer 14 on and between the dielectric pads 131, without requiring a step of removing the sacrificial material that would otherwise remain at the right of the second zones 1202.Furthermore, it being preferred that the etching does not concern all of the sacrificial material formed in line with the first zone 1201, the deposition of the hydrophobic layer 14 also results, in this case, in the covering of the sacrificial material remaining in line with the first zone 1201, at least on its upper face and potentially on its sides; this situation is that illustrated in figure 3D.

[0093] With reference to Figure 3E, the method according to the first aspect of the invention may further comprise, preferably following the deposition of the hydrophobic layer 14, a step of removing what may remain of the sacrificial layer 12, and more particularly of the part of the sacrificial layer 12 which has been preserved at the right of the first zone 1201 following the etching. This removal makes it possible to expose a surface 1000 of the second level 112 of the substrate 11 which is located at the right of each first zone 1201. Note here that this surface 1000 is also illustrated in FIGS. 2 and 7. It is therefore understood in view of FIGS. 3D and 3E that proceeding with the deposition of the hydrophobic layer 14 before the removal of what remains of the sacrificial layer 12 following the etching allows, at the same time, the removal of the hydrophobic layer 14 which covers what remains of the sacrificial layer 12, in particular at the level of the solid zone 101, following the etching.Therefore, provided that the material from which the second level 112 of the substrate 11 is made is hydrophilic, which is notably the case for silicon oxide, the wettability contrast between the solid zone 101 and the structured zone 102 is advantageously significantly increased. Note that the drop angle α of water on such a hydrophilic surface, based on silicon oxide, is typically less than 10°.

[0094] It will be noted that the plate as illustrated in Figure 3E corresponds to the plate as illustrated in Figure 2. In other words, at the end of the step of the process shown in Figure 3E, a plate 1 has been manufactured which is suitable for the self-assembly of components of the microelectronics 2 on the plate 1 by hybrid bonding of the chip-to-plate type.

[0095] Figure 7 illustrates a more specific case, and yet not excluded from the above considerations, in which the second level 112 of the substrate 11 comprises at least one level of electrical interconnections 110 extending from a solid area 101 to a structured area 102. More particularly, the electrical interconnections are buried, or equivalently encapsulated, in the dielectric material from which the second level 112 of the substrate 11 is made. The electrical interconnections are flush with the second level 112 of the substrate 11 from the exposed surface 1000 of each solid area 101, to allow electrical contact to be resumed with a microelectronic component 2 intended to be carried onto the solid area 101. On the contrary, the electrical interconnections are buried, or equivalently encapsulated, in the dielectric material from which the second level 112 of the substrate 11 is made, at the level of each structured zone 102.The depth to which these interconnections are buried determines the thickness of the second level 112 of the substrate 11 which can be dedicated to the formation of the dielectric pads 131, if it is desired that the etching does not alter the integrity of the buried interconnections. It is thus shown that the manufacturing method according to the first aspect of the invention is compatible with a self-assembly method resulting in the transfer of microelectronic components electrically connected to each other in a functional manner via the receiving plate 1, the level of electrical interconnections extending from a solid area 101 to an adjacent structured area 102, or even beyond. Preserving the integrity of the electrical interconnections in fact presupposes that the etching is stopped before the electrical interconnections are reached by it.It is therefore possible to provide, during the manufacture of the substrate 11 as supplied, that the level of electrical interconnections at the level of what is intended to form a structured zone 102 is covered with a sufficiently thick layer of dielectric material so that the dielectric pads 131 of the desired geometry can be etched in this layer, and does not require etching the electrical interconnections. Furthermore, it will be noted that the height of the dielectric pads 131 obtained by implementing the method according to the first aspect of the invention is substantially equal to the height of the step 15 obtained by this same implementation.Relative to the receiving plates known from the prior art, and for example relative to a plate conforming to the example given in FIG. 1, the step 15 obtained by implementing the method according to the first aspect of the invention is advantageously reduced, and if this reduction does not increase the wettability contrast between the solid zone 100 and the structured zone 102 which surrounds it: a. it facilitates industrial integration of the method according to the first aspect of the invention, and b. the micro-roughness which the micro-structuring obtained by implementing the method according to the first aspect of the invention confers on the structured zone 102 makes it possible to largely compensate for any reduction in performance in terms of self-alignment which would result therefrom.

[0096] The manufacturing method according to the first aspect of the invention therefore allows the manufacturing of a plate 1 according to the second aspect of the invention, and more particularly a receiving plate 1 intended for the transfer of components of the microelectronics 2 by hybrid bonding, each solid zone 101 being intended to accommodate a component of the microelectronics 2 and each structured zone 102 being intended to constitute at least part of a zone between components of the microelectronics 2.

[0097] More particularly, such a plate 1 essentially comprises a main surface 10 having at least one solid zone 101 and one structured zone 102 having, between them, a wettability contrast greater than 90°, and preferably greater than 120°, each micro- or nano-structured zone 102 extending around a solid zone 101, the plate comprising a substrate 11 which comprises a first level 111 based on a semiconductor material and a second level 112 based on a dielectric material, the second level 112 extending over the first level 111, said at least one solid zone 101 and each structured zone 102 being formed in the second level 112 of the substrate 11 and each micro- or nano-structured zone 102 having a plurality of pads based on said dielectric material 131.

[0098] And, when the etching is an over-etching consuming all the sacrificial material formed at the right of each second zone 1202, the dielectric pads 131 of the plate 1 have faceted ends 1311, for example as illustrated in FIG. 5B, so as to obtain an even greater wettability contrast, and easily brought to a value greater than 120°, or even greater than 140°.

[0099] More particularly, the plate 1 according to the second aspect of the invention may be such that: a. each dielectric pad 131 has a height of between 100 nm and 5 pm, preferably between 400 nm and 2.5 pm, and even more preferably substantially equal to 1 pm, and / or b. each dielectric pad 131 has at least one transverse dimension of between 100 nm and 2 pm, preferably between 200 nm and 1 pm, and even more preferably substantially equal to 500 nm, and / or c. two adjacent dielectric pads 131 of the same plurality are spaced apart by a distance of between 100 nm and 1 pm, preferably between 200 nm and 800 nm, and even more preferably substantially equal to 500 nm, so as to give the surface of the structured zone 102 a superhydrophobic character, whether or not the dielectric pads 131, or even the space 132 between these pads, are covered with a hydrophobic coating 14.

[0100] The invention also relates, according to a third aspect, to the self-assembly method implementing the receiving plate 1 according to the second aspect of the invention and the assembly 0 obtained by implementing the self-assembly method according to the third aspect of the invention.

[0101] It will be appreciated that, thanks to the present invention: a. it may be sufficient to add a single level of photolithography applied to the substrate 11 as provided to make it better suited to self-assembly; and / or b. the etching step for generating microroughness is a standard and perfectly controlled step in microelectronics, which does not generate defects or particles. It is very easy to integrate into a chip production process and uses the same types of equipment as the previous steps of said production process; and / or c. the shape, size and density of the generated dielectric pads 131 are perfectly controllable since they correspond to patterns drawn on the added level of photolithography.In the same way, the distance between the receiving zone of the chip 2 (hydrophilic zone) and the inter-chip zone (super-hydrophobic zone) is also adjustable since it is defined by the design of the sacrificial layer 12, which is not the case with the black silicon that can be obtained in the scientific article cited in the introduction; and / or d. it is not necessary to remove all the insulating and metallic materials, constituting the electrical interconnections 110, which can be very numerous in the inter-chip zones and difficult to remove by etching given their variety; and / or e. one avoids generating a very large step 15 on the surface of the chips and the receiving plate 1, this step being nevertheless obtained in such a way as to contribute to achieving a strong wettability contrast between the solid zone 101 and the structured zone 102.

[0102] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the claims.

Claims

CLAIMS 1. Method for manufacturing a plate (1) comprising a main surface (10) having at least one solid zone (101) and a micro- or nano-structured zone (102) having, between them, a wettability contrast greater than 90°, and preferably greater than 120°, each micro- or nano-structured zone (102) extending around a solid zone (101), the method comprising the following steps: • Providing a substrate (11) comprising a first level (111) based on a semiconductor material and a second level (112) based on a dielectric material, the second level (112) extending over the first level (111), • Forming, on an exposed surface (1121) of the second level (112) of the substrate (11) provided, a layer based on a sacrificial material (12), such as a resin, having at least a first zone (1201) on which extends a solid layer (121) based on said sacrificial material and a second zone (1202) on which extends a plurality of micrometric or nanometric pads based on said sacrificial material (122), each first zone (1201) being surrounded by a second zone (1202) and each first zone (1201) extending over a surface, of at least one order of magnitude, greater than a micrometric or nanometric surface on which extends each pad based on said sacrificial material (122), then • Etching a portion of the layer based on said sacrificial material (12) previously formed and a portion of the second level (112) of the substrate (11), so as to form, in the second level (112) of the substrate (12), said at least one solid zone (101) at the level of each first zone (1201) and each micro- or nano-structured zone (102) at the level of each second zone (1202), each micro- or nano-structured zone (102) having a plurality of pads based on said dielectric material (131) which corresponds to the plurality of pads based on said sacrificial material (122).

2. Method according to the preceding claim, in which the etching comprises over-etching of the pads (122) resulting in complete removal of the pads based on said sacrificial material (122).

3. Method according to any one of the preceding claims, in which the formation of the layer based on said sacrificial material (12) comprises a photolithography step.

4. Method according to any one of the preceding claims, in which the etching is stopped before obtaining complete removal of the layer based on said sacrificial material (12) at each first zone (1201), the layer based on said sacrificial material (12) remaining at each first zone (1201) preferably having a thickness of between 100 nm and 5 pm.

5. Method according to any one of the preceding claims, further comprising, following the etching, the deposition of a layer, preferably conformal, based on a hydrophobic material (14).

6. Method according to the preceding claim, in which the deposition of the hydrophobic layer (14) is configured so that the hydrophobic layer (14) covers each pad based on said dielectric material (131) and each space (132) between the pads based on said dielectric material (131) of the same plurality, or even where appropriate the lateral edges (1011) of each solid zone (101).

7. Method according to any one of the preceding claims, further comprising a step of removing a portion of the layer based on said sacrificial material (12) which remains at the level of the first zone (1201) after etching, so as to expose a surface (1000) of the second level (112) of the substrate (11) which is located at the level of each first zone (1201).

8. Method according to any one of claims 5 and 6 and according to claim 7, in which the deposition of the hydrophobic layer (14) is implemented before the complete removal of the part of the layer based on said sacrificial material (12) which remains at the right of the first zone (1201) after the etching.

9. Method according to any one of the preceding claims, in which the plate (1) constitutes a receiving plate intended for the transfer of components of the microelectronics (2), such as microelectronic chips, by hybrid bonding, each solid zone (101) being intended to receive a component of the microelectronics (2) and each micro- or nano-structured zone (102) being intended to constitute at least part of a zone between components of the microelectronics (2).

10. Method according to any one of the preceding claims, in which the layer based on said sacrificial material (12) is formed so that each pad (122, 131) has at least one transverse dimension between 100 nm and 2 pm, preferably between 200 nm and 1 pm, and even more preferably substantially equal to 500 nm.

11. Method according to any one of the preceding claims, in which the layer based on said sacrificial material (12) is formed so that two pads (122, 131) adjacent to each other of the same plurality are spaced apart by a distance of between 100 nm and 1 pm, preferably between 200 nm and 800 nm, and even more preferably substantially equal to 500 nm.

12. Method according to any one of the preceding claims, in which the etching is configured so that each pad based on said dielectric material (131) has a height of between 100 nm and 5 pm, preferably between 400 nm and 2.5 pm, and even more preferably substantially equal to 1 pm.

13. Plate (1) comprising a main surface (10) having at least one solid zone (101) and one micro- or nano-structured zone (102) having, between them, a wettability contrast greater than 90°, and preferably greater than 120°, each micro- or nano-structured zone (102) extending around a solid zone (101), the plate comprising a substrate (11) which comprises a first level (111) based on a semiconductor material and a second level (112) based on a dielectric material, the second level (112) extending over the first level (111), said at least one solid zone (101) and each micro- or nano-structured zone (102) being formed in the second level (112) of the substrate (11) and each micro- or nano-structured zone (102) having a plurality of pads based on said dielectric material (131), the plate being characterized in that the pads based on said dielectric material (131) have faceted ends (1311).

14. Plate (1) according to the preceding claim, further comprising a hydrophobic layer (14) covering each pad based on said dielectric material (131) and each space (132) between the pads based on said dielectric material (131) of the same plurality, or even where appropriate the lateral edges (1011) of each solid zone (1201), and not covering said at least one solid zone (1201).

15. Plate (1) according to any one of claims 13 to 14, in which: • each pad based on said dielectric material (131) has a height of between 100 nm and 5 pm, preferably between 400 nm and 2.5 pm, and even more preferably substantially equal to 1 pm, and / or • each pad based on said dielectric material (131) has at least one transverse dimension of between 100 nm and 2 pm, preferably between 200 nm and 1 pm, and even more preferably substantially equal to 500 nm, and / or • two pads based on said dielectric material (131) adjacent to each other of the same plurality are spaced apart by a distance between 100 nm and 1 m, preferably between 200 nm and 800 nm, and even more preferably substantially equal to 500 nm.

16. Plate (1) according to any one of claims 13 to 15, constituting a receiving plate intended for the transfer of microelectronic components (2), such as microelectronic chips, by hybrid bonding, each solid zone (101) being intended to receive a microelectronic component (2) and each micro- or nano-structured zone (102) being intended to constitute at least part of a zone between microelectronic components (2).

17. Plate (1) according to the preceding claim, in which the second level (112) of the substrate (11) comprises at least one level of electrical interconnections (110) extending at least in line with each solid zone (101) and extending where appropriate from a solid zone (101) to an adjacent micro- or nano-structured zone (102), the electrical interconnections (110) being flush with the second level (112) of the substrate (11) from an exposed surface (1000) of each solid zone (101) and extending from each solid zone (101) at least as far as the adjacent micro- or nano-structured zone (102), and extending more particularly below the plurality of pads based on said dielectric material (131) of said adjacent micro- or nano-structured zone (102), being encapsulated in the dielectric material based on which the second level (112) of the substrate (11) is constituted.

18. Method for self-assembly of microelectronic components using a plate (1) according to any one of claims 13 to 17.

19. Self-assembly method according to the preceding claim, in which a plurality of microelectronic components (2), such as microelectronic chips, are self-assembled on the plate (1) by hybrid chip-to-plate bonding.

20. Assembly (0) comprising a plate (1) according to any one of claims 13 to 17 and a plurality of microelectronic components (2), such as microelectronic chips, assembled on the plate (1) by hybrid bonding.

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