Process for manufacturing a multilayer structure comprising a porous silicon layer

Abstract

The invention relates to a process for manufacturing a multilayer structure, comprising the following steps: - providing a carrier substrate (40) comprising a carrier layer (41) and a porous silicon layer (42); - providing a donor substrate (50) comprising a buried fragile plane (50B) and a surface layer (51); - assembling (S3) the carrier substrate (40) and the donor substrate (50) by bonding, the surface layer (51) of the donor substrate being placed in contact with the carrier substrate; - separating the surface layer (51) from the donor substrate (50) via fracture along the buried fragile plane (50B); at least one of the carrier and donor substrates (40, 50), called the degraded substrate, comprises a degraded portion (60) so as to prevent it from bonding to the other of the carrier and donor substrates (50, 40) in the assembly step, the degraded portion (60) having an annular or substantially annular shape and being located less than 25 mm from the edge of said degraded substrate.

Description

DESCRIPTION TITLE: METHOD FOR MANUFACTURING A MULTILAYER STRUCTURE COMPRISING A POROUS SILICON LAYER TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of semiconductor materials for microelectronic components. The invention relates more particularly to a multilayer structure suitable for high-performance radiofrequency applications and comprising a buried porous silicon layer. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Radiofrequency (RF) integrated circuits are widely used in the telecommunications sector (cellular telephony, Wi-Fi, Bluetooth, etc.). These circuits are developed on substrates (also called wafers), which primarily serve as a support for their manufacture. The increasing degree of integration and performance of RF circuits leads to an increasingly strong coupling between their performance and the characteristics of the substrate on which they are formed.

[0003] As an example of circuit-substrate coupling, electromagnetic fields from high-frequency signals propagating in RF circuits penetrate into the depth of the substrate and interact with the charge carriers there. This results in problems of non-linear distortion (harmonics) of the signal, unnecessary consumption of part of the signal energy due to insertion loss and possible influences between circuits.

[0004] Radio frequency (RF) circuits, such as RF signal transceiver modules (so-called "front-end" modules), antenna switches and adapters, and power amplifiers, can be developed on different types of substrates.

[0005] Figure 1 shows a multilayer structure 10, derived from the silicon-on-insulator (SOI) multilayer structure and commonly used for the manufacture of RF integrated circuits.

[0006] This multilayer structure 10, called “TR-SOI”, successively comprises a support layer 11 made of high resistivity silicon (> 1 kQ.cm), a charge trapping layer 12 (also called a trap-rich layer), a buried oxide layer 13 and an active layer 14 made of monocrystalline silicon. The trapping layer 12 prevents the phenomenon of parasitic conduction at the interface between the support layer 11 and the buried oxide layer 13, this phenomenon usually being caused by free electrons which accumulate at the interface under the effect of the fixed positive charges contained in the buried oxide layer 13. Thanks to the trapping layer 12, the electrons are trapped and can no longer circulate. The effective resistivity of the support layer 11 is thus increased compared to a multilayer structure without a trapping layer (structure called “HR-SOI”). The trapping layer 12 can be made of polycrystalline silicon. The traps are located at the grain boundaries of polycrystalline silicon.

[0007] The combination of a high resistivity support layer 11 and a trapping layer 12 makes it possible to reduce the circuit-substrate coupling cited as an example and therefore to greatly improve the RF performance of the integrated circuits manufactured from the multilayer structure 10, particularly in terms of linearity and crosstalk. The passive elements (inductances, capacitors, etc.) formed above the active layer 14 benefit from a better quality factor.

[0008] However, a substrate with a polycrystalline silicon trapping layer exhibits RF performance that degrades as the operating temperature increases. Indeed, polycrystalline silicon has the disadvantage of undergoing partial recrystallization during high-temperature heat treatment steps, which contributes to reducing the density of traps in the layer.

[0009] Figure 2 schematically represents another multilayer structure 20 suitable for radiofrequency applications and described in document W02021 / 001066A1.

[0010] The multilayer structure 20 comprises a support layer 21 made of silicon (resistivity between 0.5 Q.cm-4 Q.cm), a porous silicon layer 22 arranged on the support layer 21, a dielectric layer 23 (for example made of silicon oxide) arranged on the porous silicon layer 22 and an active layer 24 (for example made of silicon), also called the surface layer and arranged on the dielectric layer 23.

[0011] The method for manufacturing this multilayer structure 20 comprises in particular: a step of providing a silicon support substrate; a step of porosifying a portion of the support substrate to form the porous silicon layer 22; a step of depositing the dielectric layer 23 on the porous silicon layer 22; a step of providing a donor substrate comprising a buried fragile plane delimiting the surface layer 24; a step of assembling the donor substrate on the dielectric layer, by placing the surface layer 24 in contact with the dielectric layer 23; a step of separating along the buried fragile plane to transfer the surface layer 24 onto the dielectric layer 23; and one or more heat treatment steps aimed at improving the crystalline quality of the surface layer 24 or its surface condition (roughness, defectivity).

[0012] However, it happens that the surface layer 24 cracks during the separation step and / or that the substrate finally obtained, formed by the multilayer structure 20, bends excessively after the separation step, and in particular during the heat treatment steps. Such defects make the substrate unusable for the manufacture of RF circuits. SUMMARY OF THE INVENTION

[0013] The aim of the invention is to reduce the risk of cracks during the transfer of a surface layer from a donor substrate to a support substrate comprising a porous silicon layer and to limit the phenomenon of curvature of the multilayer structure thus obtained.

[0014] According to the invention, this goal is achieved by providing a method for manufacturing a multilayer structure, comprising the following steps: providing a support substrate comprising a support layer and a porous silicon layer disposed on the support layer; providing a donor substrate comprising a first face, a buried fragile plane and a surface layer delimited by the first face and the buried fragile plane; assembling the support substrate and the donor substrate by bonding, the surface layer of the donor substrate being disposed in contact with the support substrate; and separating the surface layer of the donor substrate by fracture along the buried fragile plane. This manufacturing method is remarkable in that at least one of the support and donor substrates, called the degraded substrate, comprises a degraded portion so as to prevent it from sticking to the other of the support and donor substrates during the assembly step, the degraded portion having an annular or substantially annular shape and being located less than 25 mm from the side of said degraded substrate, preferably less than 5 mm from the side of said degraded substrate.

[0015] In certain embodiments of the manufacturing method, the support substrate further comprises a peripheral portion of non-porous silicon arranged around the porous silicon layer and the degraded portion is located, in the assembly of the support substrate and the donor substrate, vertically above an interface between the peripheral portion of non-porous silicon and the porous silicon layer.

[0016] In another embodiment, the porous silicon layer comprises a central portion having a first substantially constant thickness and a peripheral portion having a second thickness increasing towards the flank of the support substrate and the degraded portion is located, in the assembly of the support substrate and the donor substrate, vertically above a transition between the central portion and the peripheral portion of the porous silicon layer.

[0017] In another embodiment, the support substrate further comprises a peripheral portion of non-porous silicon arranged around the porous silicon layer and the degraded portion is constituted by a cavity extending into the porous silicon layer and located at a distance of less than 2 mm from an interface between the peripheral portion of non-porous silicon and the porous silicon layer. The cavity is advantageously filled with a material having a Young's modulus lower than that of porous silicon.

[0018] In addition to the characteristics which have just been mentioned in the preceding paragraphs, the manufacturing method according to the invention may have one or more additional characteristics among the following, considered individually or according to all technically possible combinations: the degraded portion further extends to the side of said degraded substrate; the degraded portion is spaced from the side of said degraded substrate and has a width of between 10 μm and 4 mm; the degraded portion is constituted by a recessed portion; the recessed portion belongs to the donor substrate; the step of providing the donor substrate comprises a step of implanting light ions in a first substrate at an implantation depth to form the buried fragile plane, the recessed portion being obtained by forming a cavity of a depth greater than the implantation depth.the recessed portion belongs to the support substrate; the degraded portion is constituted by a textured portion having a surface roughness greater than or equal to 1 nm; the degraded portion is constituted by a chamfered portion; the support substrate further comprises a dielectric layer arranged on the porous silicon layer; and the degraded portion is substantially annular and the degraded substrate comprises a so-called non-degraded portion located in the extension of the degraded portion, said non-degraded portion being bonded to the other of the support and donor substrates during the assembly step. BRIEF DESCRIPTION OF THE FIGURES

[0019] Other characteristics and advantages of the invention will emerge clearly from the description given below, for information purposes only and in no way limiting, with reference to the appended figures, among which: Figure 1, previously described, represents a multilayer structure according to the prior art, which can be used as a starting substrate for the manufacture of radiofrequency integrated circuits; Figure 2, previously described, represents another multilayer structure according to the prior art, also suitable for the manufacture of radiofrequency circuits; Figures 3A to 3C represent a first embodiment of the method for manufacturing a multilayer structure according to the invention; Figures 4A to 4C represent a second embodiment of the method for manufacturing a multilayer structure; Figures 5A to 5C represent a third embodiment of the method for manufacturing a multilayer structure; Figures 6A to 6C represent a fourth embodiment of the method for manufacturing a multilayer structure; Figures 7A to 7C represent a fifth embodiment of the method for manufacturing a multilayer structure;Figures 8A to 8C represent a sixth embodiment of the method for manufacturing a multilayer structure; Figures 9A to 9C represent a seventh embodiment of the method for manufacturing a multilayer structure; Figures 10A to 10C represent an embodiment of the step of providing the support substrate comprising the porous silicon layer; and Figure 11 represents a main face of a substrate comprising a degraded zone of substantially annular shape.;

[0020] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION

[0021] Figures 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C and 9A-9C illustrate different modes of implementing a method for manufacturing a multilayer structure 30. The multilayer structure 30 is intended to serve as a support for the manufacturing of microelectronic components, in particular radiofrequency (RF) integrated circuits. It thus constitutes a wafer.

[0022] These figures represent in sectional view only a part of the multilayer structure 30 and the substrates 40, 50 necessary for its manufacture. The multilayer structure 30 and the substrates 40, 50 each comprise two main faces (commonly called front faces and rear faces), for example in the form of a disc, which extend perpendicular to the sectional plane of the figures. In addition, the multilayer structure 30 and the substrates 40, 50 advantageously have a plane of symmetry, symbolized by a dot-and-dash line (and passing through the center of the two main faces).

[0023] In a manner common to all the implementation modes, the method of manufacturing the multilayer structure 30 comprises the following steps S1 to S4: 51: providing a support substrate 40 comprising a support layer 41 and a porous silicon layer 42 disposed on the support layer 41 (see [Fig. 3A], [Fig. 4A], [Fig. 5A], [Fig. 6A], [Fig. 7A], [Fig. 8A] and [Fig. 9A]); 52: providing a donor substrate 50 comprising a first face 50A, a buried fragile plane 50B and a surface layer 51 delimited by the first face 50A and the buried fragile plane 50B (cf. [Fig. 3A], [Fig. 4A], [Fig. 5A], [Fig. 6A], [Fig. 7A], [Fig. 8A] and [Fig. 9A]); 53: assembling the support substrate 40 and the donor substrate 50 by bonding, the surface layer 51 of the donor substrate 50 being arranged in contact with the support substrate 40 (see [Fig. 3B], [Fig. 4B], [Fig. 5B], [Fig. 6B], [Fig. 7B], [Fig. 8B] and [Fig. 9B]); and 54: separate the surface layer 51 from the donor substrate 50 by fracture along the buried fragile plane 50B (see [Fig. 3C], [Fig. 4C], [Fig. 5C], [Fig. 6C], [Fig. 7C], [Fig. 8C] and [Fig. 9C]).

[0024] The multilayer structure 30 comprising the porous silicon layer 42 is suitable for radiofrequency applications aiming for: low insertion losses (low signal attenuation) and good linearity (low signal distortion causing harmonics); stability of these performances in temperature, in particular in the range of use of RF integrated circuits [-40 °C; 150 °C], or even up to 225 °C; low capacitive coupling between the RF integrated circuits and the support layer 41, typically thanks to a dielectric permittivity lower than that of silicon.

[0025] The support layer 41 of the support substrate 40 is intended to ensure the mechanical strength of the multilayer structure 30, in particular so that it can be handled during the manufacturing steps of the microelectronic components. Its thickness may be between 500 μm and 1 mm. The support layer 41 is preferably made of silicon. Advantageously, the silicon of the support layer 41 has an electrical resistivity of between 5 mΩ.cm and 20 Ω.cm, preferably between 0.5 Ω.cm and 4 Ω.cm.

[0026] The porous silicon layer 42 comprises hollow pores whose diameter is preferably between 2 nm and 50 nm. Hollow pores are understood to mean pores which are not entirely filled with a solid material. The internal walls of the pores are advantageously lined with oxide, for example silicon dioxide (SiO2). The fact that the internal walls of the pores are lined with oxide reflects a stabilized state of the porous silicon layer 42, in which dangling bonds of the Si-Hx type have been mainly replaced by much more stable Si-O-Si bonds. The mechanical stability of the porous silicon layer 42 is improved.

[0027] Advantageously, the porosity rate of the porous silicon layer 42 is between 40% and 70%. This porosity rate ensures a good balance between the mechanical properties and electrical properties of the porous silicon layer 42.

[0028] The porous silicon layer 42 advantageously has a resistivity greater than 20 kΩ.cm.

[0029] The thickness of the porous silicon layer 42 is preferably between 5 μm and 50 μm. The thickness of the porous silicon layer 42, combined with its morphology (pore diameter, porosity rate), defines the mechanical strength of the porous silicon layer 42.

[0030] With reference to Figures 3A, 4A, 5A, 6A, 7A, 8A and 9A, the step S1 of providing the support substrate 40 may comprise a sub-step of porosifying a surface portion of a first silicon substrate. By surface portion (or layer) is meant a portion (layer) which extends from a (main) face of the first substrate. The porosified portion of the first substrate constitutes the porous silicon layer 42, while the remaining portion of the first substrate, not porosified, constitutes the support layer 41.

[0031] The porosification sub-step is generally accomplished electrochemically or photoelectrochemically. It is based on an anodic dissolution phenomenon in an acidic medium, from the silicon of the first substrate. For example, the first substrate is immersed in a hydrofluoric acid (HF) solution. The first substrate is in contact with an anode and a cathode is placed opposite the face of the first substrate to be porosified.

[0032] There are different configurations of porosification equipment. The most common configurations are called "single cell" and "double cell". In the first case, only one side of the first substrate is in contact with the acidic medium. In the second, both sides of the first substrate are in contact with the acidic medium, this acidic medium comprising either the same solution for both sides or two different solutions.

[0033] In an alternative implementation, only the surface portion (to be porosified) of the first substrate is made of silicon. The remaining portion of the first substrate, intended to form the support layer 41, may be made of another material (semiconductor or not).

[0034] After the porosification sub-step, the step S1 of providing the support substrate 40 advantageously comprises a sub-step of annealing the porous silicon layer 42 under an oxidizing atmosphere at a temperature between 300°C and 400°C, so as to stabilize the porous silicon layer 42. Preferably, the duration of the annealing under an oxidizing atmosphere is between 5 min and 200 min.

[0035] This annealing makes it possible to replace the majority of hanging Si-Hx type bonds, particularly present on the internal walls of the pores, with much more stable Si-O-Si bonds.

[0036] Advantageously, annealing in an oxidizing atmosphere is followed by annealing in a neutral atmosphere, for example under nitrogen, at a temperature between 400°C and 450°C, for example at 420°C. Annealing in a neutral atmosphere typically lasts between 2 and 16 hours, for example 10 hours.

[0037] Annealing in a neutral atmosphere in particular prevents degassing during heat treatments subsequently applied to the multilayer structure 30, this degassing being likely to degrade the quality of said structure. In addition, annealing in a neutral atmosphere tends to stabilize the curvature of the support substrate 40 provided with the porous silicon layer 42, limiting the phenomenon of curvature of the multilayer structure 30 after these heat treatments.

[0038] Finally, step S1 of providing the support substrate 40 may comprise a sub-step of forming a dielectric layer 43 on the porous silicon layer 42. The dielectric layer 43 is an electrically insulating layer. It may consist of a nitride, for example silicon nitride (SiN4), or an oxide such as silicon dioxide (SiC) or aluminum oxide (AI2O3). Its thickness may be between 200 nm and 2 pm.

[0039] The dielectric layer 43 may be formed by a chemical vapor deposition technique, for example by low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDP-CVD).

[0040] Still with reference to Figures 3A, 4A, 5A, 6A, 7A, 8A and 9A, at least one so-called "active" part of the surface layer 51 of the donor substrate 50 is formed of a material chosen from silicon, germanium, silicon carbide, piezoelectric materials (for example LiNbOs, LiTaOs, etc.) and binary, ternary or quaternary alloys of type IV-IV (e.g. SiGe), III-V or II-VI semiconductor materials. The surface layer 51 is intended to be transferred onto the support substrate 40 and its active part is intended to receive active components, such as transistors, during the manufacture of microelectronic components from the multilayer structure 30. The thickness of the active part is preferably between 50 nm and 1.5 μm.

[0041] The surface layer 51 can be formed by a thin film (50 nm - 1.5 pm) of piezoelectric material or semiconductor material (silicon, germanium, silicon carbide, type IV-IV, III-V or III-VI alloys, etc.), intrinsic or doped (see Figs. 3A, 4A, 5A, 6A and 9A). It is then entirely intended to receive the active components. In this case, we also speak of an active layer.

[0042] Alternatively, the surface layer 51 may be formed from a stack of several sub-layers (see Figs. 7A and 8A), for example a stack comprising an active sub-layer 511 made of piezoelectric or semi-conductor material (the thickness of which may be between 50 nm and 1.5 μm) and a dielectric sub-layer 512 arranged on the active sub-layer 511 (and the thickness of which may be between 50 nm and 500 nm).

[0043] The step S2 of providing the donor substrate 50 preferably comprises a sub-step of forming the buried fragile plane 50B in a second substrate. Preferably, the second substrate is made of a material chosen from silicon, germanium, silicon carbide, piezoelectric materials (for example LiNbOs, LiTaOs, etc.) and binary, ternary or quaternary alloys of type IV-IV semiconductor materials (for example SiGe), III-V or II-VI.

[0044] The buried fragile plane 50B is advantageously formed by implanting light ions through a first face of the second substrate. The ions are implanted into the second substrate at a given implantation depth, measured from the first face of the second substrate. The implantation depth may be between 50 nm and 1.5 pm, for example 400 nm. Light ions herein designate ions of chemical species having an atomic number less than or equal to 5. The light ions are preferably hydrogen or helium ions, because these ions are favorable to the formation of microcavities around the implantation depth, giving rise to the buried fragile plane 50B, as described in the SOI substrate manufacturing process known as Smart Cut™ (registered trademark).

[0045] Before or after the implantation sub-step, the step S2 of providing the donor substrate 50 may also comprise the deposition of a dielectric sub-layer 512 (see Figs. 7A and 8A) on the first face of the second substrate (this dielectric sub-layer 512 forming a part of the surface layer 51).

[0046] Steps S3 and S4 described below relate to the transfer of the surface layer 51 of the donor substrate 50 onto the support substrate 40.

[0047] Step S3 of assembling the support substrate 40 and the donor substrate 50 consists of bonding the donor substrate 50 on the side of its first face 50A onto the support substrate 40. This assembly step S3 is also called the step of transferring the donor substrate 50 onto the support substrate 40.

[0048] In a preferred embodiment of the assembly step S3 illustrated by FIGS. 3B, 4B, 5B, 6B and 9B, the surface layer 51 of the donor substrate 50 is brought into contact with the dielectric layer 43 of the support substrate 40.

[0049] In an alternative implementation illustrated by FIG. 7B, the surface layer 51 comprises on the surface a dielectric sub-layer 512 which is brought into contact with the dielectric layer 43 of the support substrate 40. The dielectric sub-layer 512 of the donor substrate 50 and the dielectric layer 43 of the support substrate 40 are advantageously formed from the same dielectric material, preferably an oxide (e.g. SiC).

[0050] Finally, in an alternative implementation represented by FIG. 8B, the support substrate 40 is devoid of a dielectric layer 43 and the surface layer 51 comprises on the surface a dielectric sub-layer 512 which is brought into contact with the porous silicon layer 42 of the support substrate 40.

[0051] The assembly of the support and donor substrates 40, 50 can be accomplished by any known bonding technique, preferably by direct bonding by molecular adhesion. This technique will not be described in detail here. It is nevertheless recalled that, prior to bonding, the support substrate 40 and the donor substrate 50 have preferably undergone cleaning and / or surface activation sequences, in order to guarantee the quality of the bonding interface in terms of defectivity and bonding energy. In addition, the support substrate 40 and the donor substrate 50 have preferably undergone a polishing step (for example by chemical-mechanical planarization or CMP) of their bonding surface so as to obtain a surface roughness strictly less than 0.7 nm. This roughness value, as well as all those given subsequently, are expressed as a root mean square value.The root mean square roughness (denoted Rq) is determined by a statistical analysis of an atomic force microscope image, taking as a sample a surface of 1x1 pm. 2

[0052] Step S4 of separating the surface layer 51 by fracture along the buried fragile plane 50B makes it possible to detach the surface layer 51 from the donor substrate 50 and thus obtain the multilayer structure 30 on the one hand, and the remainder of the donor substrate 50 on the other hand. The remainder of the donor substrate 50 can be reused to transfer other surface layers, during new iterations of the manufacturing process.

[0053] Preferably, step S4 of separating the surface layer 51 comprises a heat treatment. For a surface layer 51 (or an active sub-layer 511) made of silicon, this heat treatment is carried out at a temperature between 200°C and 500°C, preferably between 350°C and 450°C. Such a heat treatment is capable of increasing the level of embrittlement of the buried fragile plane 50B, a phenomenon at the basis of the Smart Cut™ process.

[0054] A temperature of the order of 400°C is advantageous in that the assembly undergoes fewer mechanical stresses linked to the different expansion coefficients of the materials constituting the support substrate 40 and the donor substrate 50. Indeed, excessively high stresses are likely to affect the integrity of the porous silicon layer 42.

[0055] After the separation step S4, the method for manufacturing the multilayer structure 30 may comprise one or more heat treatment steps to improve the crystalline quality and / or the surface condition (roughness, defectivity) of the surface layer 51 (so-called finishing annealing of the surface layer 51) or to consolidate the bonding interface (so-called consolidation annealing of the interface).

[0056] In the embodiments of Figures 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C and 8A-8C, the support substrate 40 further comprises a peripheral portion of non-porous silicon 44 (or bulk silicon) arranged around the porous silicon layer 42. In other words, the porous silicon layer 42 does not extend to the side of the support substrate 40. This is the case in particular when porosification equipment of the “double cell” type has been used to form the porous silicon layer 42 (a peripheral seal bears on the face of the first substrate in contact with the acid medium). The peripheral portion of non-porous silicon 44 has a width L1 which varies between 1 mm and 5 mm (for example depending on the equipment used). The width of a portion of a substrate here designates the dimension of this portion measured along a radius of said substrate. The thickness of the peripheral portion 44 is equal to the thickness of the porous silicon layer 42.

[0057] The peripheral portion of non-porous silicon 44 tends to reduce the curvature of the multilayer structure 30 during the subsequent heat treatment steps (steps of finishing the surface layer 51 or of manufacturing the components). On the other hand, it is responsible for arc-shaped cracks which may appear in the surface layer 51 during the separation step S4.

[0058] The separation of the surface layer 51 is the result of the propagation of at least one fracture wave in the buried brittle plane 50B. The fracture wave originates at a location of the buried brittle plane 50B, generally on the edge (typically circular), and propagates in all directions of the buried brittle plane 50B, in the case presented here at different speeds due to the heterogeneous composition of the underlying support substrate 40. More particularly, the fracture wave propagates much faster above the non-porous silicon than above the porous silicon, which absorbs more of the fracture energy. This is the origin of the cracks observed.

[0059] In order to drastically reduce the risk of cracks in the surface layer 51 during the separation step S4, at least one of the support and donor substrates 40, 50 comprises a degraded portion 60, configured not to be bonded to the other of the support and donor substrates 40, 50 during the assembly step S3. Thus, the bonding of the support and donor substrates 40, 50 is only partial (i.e. it occurs outside the degraded portion(s) 60). The substrate comprising the degraded portion 60 is hereinafter referred to as the degraded substrate.

[0060] It results from this local absence of bonding between the support substrate 40 and the donor substrate 50 that cracking cannot be obtained (in the buried fragile plane 50B) opposite the degraded portion 60 due to the lack of stiffener. Consequently, the surface layer 51 of the donor substrate 50 is not transferred onto the support substrate 40 opposite the degraded portion 60.

[0061] The degraded portion 60 has an annular or substantially annular shape. The expression “substantially annular” refers to a segment of a ring, this segment having a circumference (or outer perimeter) greater than or equal to 90% of the circumference of the (entire) ring. It can also be reference to several segments of the same ring whose total circumference is greater than or equal to 90% of the circumference of the ring.

[0062] In the first embodiment represented by Figures 3A-3C, the degraded substrate is the donor substrate 50. In other words, the degraded portion 60 belongs to the donor substrate 50. It is located, in the assembly of the substrates 40 and 50, vertically above the interface between the porous silicon layer 42 and the peripheral portion of non-porous silicon 44 (in other words, the vertical projection of the interface crosses the degraded portion 60). Furthermore, it extends to the side of the degraded substrate (here the donor substrate 50).

[0063] The degraded portion 60 of Figures 3A-3C is formed by a recessed portion relative to the first face 50A of the donor substrate 50. This recessed portion, also called a hollowed-out portion, can be obtained by forming a cavity (annular or substantially annular) in the donor substrate 50 from the first face 50A (see Fig.SA). The depth P of this cavity, measured from the first face 50A, is greater than the topology of the edge of the support substrate 40 (to avoid the risk of sticking to the support substrate). In addition, it is advantageously greater than the implantation depth of the light ions to form the buried fragile plane 50B. It is preferably between 200 nm and 10 pm, for example 6 pm. The cavity can be obtained by etching or micromilling.

[0064] An advantage of this first embodiment is that the surface layer 51 transferred onto the support substrate 40 then has a clear outline (see Fig. SC). Furthermore, when the depth P of the cavity is greater than or equal to twice the implantation depth, the donor substrate 50 can be reused without needing to form the cavity again.

[0065] In the second embodiment represented by figures 4A-4C, the degraded substrate is on the contrary the support substrate 40. In other words, the degraded portion 60 belongs to the support substrate 40. As previously, it extends from the side of the degraded substrate (here the support substrate 40) until it reaches or exceeds the vertical projection of the interface between the porous silicon layer 42 and the peripheral portion 44.

[0066] The degraded portion 60 of Figures 4A-4C is constituted by a textured portion of the dielectric layer 43, this portion being textured so as to have a surface roughness greater than or equal to 1 nm. Indeed, too much roughness prevents the bonding of the support substrate 40 and the donor substrate 50. Apart from the degraded portion 60, the surface roughness of the support and donor substrates 40, 50 is therefore strictly less than 1 nm.

[0067] The textured portion may be obtained by etching the dielectric layer 43, by chemical treatment, by plasma treatment, by ion beam bombardment, by nanosecond laser annealing or by applying (punching) a textured ring to create defects.

[0068] In a first implementation variant (not shown in the figures), the degraded portion 60 is a textured portion (Rq > 1 nm) belonging to the donor substrate 50, and more particularly to the surface layer 51.

[0069] In a second implementation variant (also not shown in the figures), the degraded portion 60 is a recessed portion belonging to the support substrate 40, and more particularly to the dielectric layer 43. The depth of the corresponding cavity is preferably strictly less than the thickness of the dielectric layer 43.

[0070] Thus, in these first two embodiments and their variants, the degraded portion 60 is arranged so as to obtain a fracture wave which propagates above a homogeneous medium comprising the porous silicon layer 42. There are then no cracks. The width L2 of the degraded portion 60 is strictly greater than the width L1 of the peripheral portion 44, and preferably between 2 mm and 6 mm.

[0071] In the third embodiment shown in Figures 5A-5C, the degraded portion 60 belongs to the support substrate 40. It is also located (in the assembly of the substrates 40 and 50) vertically above the interface between the porous silicon layer 42 and the peripheral portion 44. On the other hand, and unlike the second embodiment (Figs. 4A-4C), it does not extend to the side of the support substrate 40. In other words, it is spaced from the side of the support substrate 40. It is located at a distance d of less than 5 mm from the side of the support substrate 40.

[0072] The degraded portion 60 may be formed by a recessed portion of the dielectric layer 43, as shown in FIGS. 5A-5C (and as in the second implementation variant), or by a textured portion of high roughness of the dielectric layer 43 (as in the embodiment of Figures 4A-4C).

[0073] In the fourth embodiment shown in FIGS. 6A-6C, the degraded portion 60 belongs to the donor substrate 50. It is also located vertically above the interface between the porous silicon layer 42 and the peripheral portion 44. On the other hand, and unlike the first embodiment (FIGS. 3A-3C), it does not extend to the side of the donor substrate 50. It is nevertheless located at a distance d of less than 5 mm from the side of the donor substrate 50. The degraded portion 60 may be formed by a portion set back from the first face 50A of the donor substrate 50, as shown in FIGS. 6A-6C (and as in the embodiment of FIGS. 3A-3C), or by a textured portion of high roughness of the surface layer 51 (as in the first implementation variant).

[0074] In these third and fourth embodiments, the degraded portion 60 is arranged so as to obtain two fracture waves each propagating in a specific region (peripheral or central) of the buried fragile plane 50B, above a homogeneous medium (comprising either the porous silicon layer 42 or the peripheral portion 44). There are therefore only two fracture fronts which do not have the possibility of joining, given that the fracture waves do not propagate opposite the degraded portion 60 (absence of bonding of the surface layer 51). The width L3 of the degraded portion 60 is preferably between 10 μm and 4 mm.

[0075] The third and fourth embodiments of the manufacturing method also make it possible to obtain a portion (annular) of active layer at the periphery of the multilayer structure 30 (unlike the previous embodiments), which may prove useful for the integration of microelectronic components.

[0076] In the fifth embodiment represented by figures 7A-7C, the degraded portion 60 is constituted by a cavity (annular or substantially annular) which extends (from the bonding face of the support substrate 40) in the porous silicon layer 42, at a distance d less than 7 mm from the side of the support substrate 40 and at a distance d less than 2 mm from the interface between the silicon layer porous 42 and the peripheral portion 44. The cavity 60 can be formed by etching, micromilling or nanosecond laser annealing. Its width L4 is preferably between 10 μm and 1 mm.

[0077] Advantageously, the cavity 60 extends over the entire thickness of the porous silicon layer 42.

[0078] This cavity 60 allows the porous silicon layer 42 to deform (or rearrange) at least partly by the flank rather than vertically, thus avoiding protrusions or inhomogeneities which can harm the quality of the bonding (and consequently create non-transferred areas).

[0079] A dielectric material, typically that forming the dielectric layer 43, may cover the bottom and the side walls of the cavity 60, without however filling it entirely. Furthermore, the cavity 60 may be (with or without dielectric coating on the bottom and the side walls) partially or totally filled with a material absorbing the fracture wave, thus forming a box of absorbent material. The absorbent material has a Young's modulus lower than that of porous silicon (i.e. less than 20 GPa).

[0080] Again, the cavity 60 or the absorbing box makes it possible to distinguish two distinct zones of propagation of the fracture waves, above a homogeneous or practically homogeneous medium, which prevents the appearance of cracks.

[0081] In the sixth embodiment represented by FIGS. 8A-8C, the degraded portion 60 is produced on one and / or the other of the substrates 40-50 (on both in the example of FIGS. 8A-8C) by optimizing the wafer edge chamfers. This optimization is for example carried out by lateral etching (“edgegrinding”) so that the chamfered wafer edge part (constituting the degraded portion 60) extends to the porous silicon layer 42 (before assembly when it belongs to the support substrate 40 and after assembly when it belongs to the donor substrate 50) so that there can be no bonding beyond the porous silicon layer 42.

[0082] In the seventh embodiment represented by figures 9A-9C, the porous silicon layer 42 comprises a central portion 421 having a substantially constant thickness e1 and a peripheral portion 422 of increasing thickness e2 in the direction of the flank of the support substrate 40. By substantially constant, it is understood that the thickness e1 of the central portion 421 does not vary by more than 5%. On the other hand, the thickness e2 of the peripheral portion 422 can vary by more than 30% between the interface with the central portion 421 and the flank of the support substrate 40.

[0083] Such a porous silicon layer 42 is notably obtained when a “single cell” type porosification equipment is used (for the record, an entire face of the first substrate is exposed to the acid medium). The peripheral portion 422 of increasing thickness has a width LT which can vary between 2 mm and 25 mm.

[0084] In this case, the multilayer structure 30 is practically not affected by the crack phenomenon, because the fracture wave propagates above a generally homogeneous medium (of composition). On the other hand, the thickness inhomogeneity of the porous silicon at the edge of the wafer is responsible for an increase in the curvature of the multilayer structure 30 during annealing, in particular during the consolidation annealing of the bonding interface which can reach 1000 °C (the multilayer structure 30 can have a deflection of 600 pm after annealing).

[0085] To limit or cancel the effect of the thickness gradient, and therefore reduce the curvature of the multilayer structure 30, a degraded portion 60 is arranged in at least one of the support and donor substrates 40, 50. The degraded portion 60 is located, in the assembly of the support substrate 40 and the donor substrate 50, vertically above the transition between the central portion 421 and the peripheral portion 422 of the porous silicon layer 42.

[0086] The degraded portion 60 may be a recessed portion, a textured portion (with a roughness greater than or equal to 1 nm; see Figs. 9A-9C), a cavity (filled or not with absorbent material), a chamfered portion of the plate edge, as described previously. It may extend to the side of the degraded substrate (L2 > LT). Its width L2 is then advantageously between 3 mm and 26 mm.

[0087] The recessed portion in the dielectric layer 43 is the most favorable solution, since the dielectric layer 43 also plays a role in the curvature of the multilayer structure 30.

[0088] More generally, the degraded portion 60 is located less than 25 mm from the side of the degraded substrate, and preferably less than 7 mm in the embodiment of FIGS. 7A-7C and less than 5 mm in the embodiments of FIGS. work of figures 3A-3C, 4A-4C, 5A-5C, 6A-6C and 8A-8C. Thus, the risks of cracks in the surface layer 51 and / or excessive curvature of the multilayer structure 30 caused by inhomogeneities at the edge of the assembly can be reduced.

[0089] Figures 10A-10C represent an embodiment of the step of providing the support substrate 40, making it possible to recreate the structure comprising a peripheral portion of non-porous silicon 44 (see Figs. 3A-3C, 4A-4C, 5A-5C, 6A-6C, 7A-7C, 8A-8C), even though porosification equipment of the “single cell” type is used to form the porous silicon layer 42.

[0090] During a first sub-step S11 illustrated by FIG. 10A, a first silicon substrate 90 is removed (for example by etching) so as to form a central cavity 91 delimited laterally by a ring 92 (made of silicon). The ring 92 constitutes a peripheral portion of the first substrate 90.

[0091] The thickness e3 of this ring 92 (equal to the etching depth) is greater than or equal to the maximum thickness (e2) of the porous silicon layer to be formed (i.e. the thickness at the flank). Thus, during the second sub-step S12 of porosification using “single cell” type porosification equipment (see FIG. 10B), the porous silicon layer 42' formed does not extend to the entire ring 92. A buried portion 921 of the ring 92 is left intact. Preferably, the width L5 of the ring 92 is such that the peripheral portion of increasing thickness of the porous silicon layer 42' is located entirely in the ring 92.

[0092] Finally, during a third sub-step S23 (see FIG. 10C), the ring 92 is completely removed so as to obtain a flat surface with the central portion (of substantially constant thickness e1) of the porous silicon layer 42'.

[0093] The delimitation of a ring 92 at the periphery of the first substrate 90 during the first sub-step S11 therefore makes it possible to protect an underlying silicon portion from the porosification process (forming said peripheral portion 44 of the support substrate 40), this silicon portion being arranged around the porous silicon portion finally preserved (forming said porous silicon layer 42 of the support substrate 40).

[0094] This particular mode of implementation of step S1 of providing the support substrate 40 also prevents the porous silicon from extending onto the side of the multilayer structure 30, which can be a source of fragility or contamination (e.g. infiltration of etching solutions, cleaning solutions, etc. used during the manufacture of the components).

[0095] As previously indicated, the degraded portion 60 of the support substrate 40 or the donor substrate 50 may have a shape that is not completely annular (“substantially annular”). In other words, a portion of the support substrate 40 or the donor substrate 50 may be left intact in order to create a fracture initiation zone at the edge.

[0096] Figure 11 represents, by way of example, the bonding face of the support substrate 40 of Figure 4A. The dotted circle represents the interface between the porous silicon layer 42, at the center of the substrate, and the peripheral portion of non-porous silicon 44. A non-degraded portion 70 (here of the dielectric layer 43) is located in the extension of the degraded portion 60 in a ring segment, so that it completes the ring. By "non-degraded portion", we mean a portion which is bonded to the other of the substrates during the assembly step S3.

[0097] The non-degraded portion 70 is advantageously arranged so as to include a notch 80 (commonly called a “notch”) of the support substrate 40 (or of the donor substrate 50), as shown in FIG. 11.

[0098] With reference to Figures 3C, 4C, 5C, 6C, 7C, 8C and 9C, the multilayer structure 30 thus comprises the support layer 41, the porous silicon layer 42 arranged on the support layer 41, a dielectric layer 43, 512 (dielectric layer 43 and / or dielectric sub-layer 512) arranged on the porous silicon layer 42 and an active layer 51, 511 (surface / active layer 51 or active sub-layer 511) arranged on the dielectric layer 43, 512.

[0099] In the case of an oxide, the dielectric layer 43, 512 can also be called the buried oxide layer or BOX (for “buried oxide layer” in English).

[0100] A particular feature of the multilayer structure 30 is that the active layer 51, 511 comprises a recess 510 of annular or substantially annular shape. The recess 510 extends as far as the dielectric layer 43, in other words over the entire the thickness of the active layer 51, 511. Thus, the active layer 51, 511 does not completely cover the support layer 41.

[0101] Such a recess in the active layer 51, 511 near the sidewall of the multilayer structure 30 is much less detrimental than excessive curvature or cracks for the manufacture of microelectronic components (these cracks generally extending much further towards the center of the wafer).

Claims

CLAIMS

1. A method of manufacturing a multi-layer structure (30), comprising the following steps: - providing (S1) a support substrate (40) comprising a support layer (41) and a porous silicon layer (42) arranged on the support layer; - providing (S2) a donor substrate (50) comprising a first face (50A), a buried fragile plane (50B) and a surface layer (51) delimited by the first face and the buried fragile plane; - assembling (S3) the support substrate (40) and the donor substrate (50) by gluing, the surface layer (51) of the donor substrate being arranged in contact with the support substrate; - separating (S4) the surface layer (51) from the donor substrate (50) by fracture along the buried fragile plane (50B); method characterized in that at least one of the support and donor substrates (40, 50), called the degraded substrate, comprises a degraded portion (60) so as to prevent it from sticking to the other of the support and donor substrates (50, 40) during the assembly step, the degraded portion (60) having an annular or substantially annular shape and being located less than 25 mm from the side of said degraded substrate.

2. The method of claim 1, wherein the support substrate (40) further comprises a peripheral portion of non-porous silicon (44) disposed around the porous silicon layer (42) and wherein the degraded portion (60) is located, in the assembly of the support substrate (40) and the donor substrate (50), vertically above an interface between the peripheral portion of non-porous silicon (44) and the porous silicon layer (42).

3. Method according to claim 1, in which the porous silicon layer (42) comprises a central portion (421) having a first thickness (e1) which is substantially constant and a peripheral portion (422) having a second thickness (e2) which increases towards the flank of the support substrate (40) and in which the degraded portion (60) is located, in the assembly of the support substrate (40) and the donor substrate (50), vertically above a transition between the central portion (421) and the peripheral portion (422) of the porous silicon layer (42).

4. A method according to any one of claims 1 to 3, wherein the degraded portion (60) further extends to the sidewall of said degraded substrate.

5. A method according to any one of claims 1 to 3, wherein the degraded portion (60) is spaced from the side of said degraded substrate and has a width (L3) of between 10 pm and 4 mm.

6. A method according to any one of claims 1 to 5, wherein the degraded portion (60) is constituted by a recessed portion.

7. The method of claim 6, wherein the recessed portion belongs to the donor substrate (50).

8. The method of claim 7, wherein the step (S2) of providing the donor substrate (50) comprises a sub-step of implanting light ions into a first substrate at an implantation depth to form the buried fragile plane (50B), the recessed portion being obtained by forming a cavity of a depth (P) greater than the implantation depth.

9. A method according to any one of claims 1 to 5, wherein the degraded portion (60) consists of a textured portion having a surface roughness greater than or equal to 1 nm.

10. The method of claim 1, wherein the support substrate (40) further comprises a non-porous silicon peripheral portion (44) disposed around the porous silicon layer (42) and wherein the degraded portion (60) is constituted by a cavity extending into the porous silicon layer (42) and located at a distance (d') less than 2 mm from an interface between the non-porous silicon peripheral portion (44) and the porous silicon layer (42).

11. The method of claim 10, wherein the cavity is filled with a material having a Young's modulus lower than that of porous silicon.

12. The method of any one of claims 1 to 11, wherein the support substrate (40) further comprises a dielectric layer (43) disposed on the porous silicon layer (42).

13. Method according to any one of claims 1 to 12, in which the degraded portion (60) is substantially annular and in which said degraded substrate comprises a so-called non-degraded portion (70) located in the extension of the degraded portion (60), said non-degraded portion (70) being bonded to the other of the support and donor substrates (50, 40) during the assembly step (S3).

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