Method for transferring a semiconductor layer

Abstract

One aspect of the invention relates to a method for transferring a semiconductor layer (40) from a donor substrate (10) to a receiver substrate (20), the method comprising the following successive steps: - first implantation (S120) of first light ions (3a) into the donor substrate (10) at a predetermined implantation depth (30) so as to form therein a buried fragile plane (300), - epitaxy (S130) on the donor substrate (10) of the semiconductor layer (40) to be transferred, - second implantation (S140) of second light ions (3b) into the donor substrate (10) through the semiconductor layer (40) to be transferred level with the fragile plane (300), - assembly (S150) by bonding of the receiver substrate (20) and of the donor substrate (10) covered with the semiconductor layer (40) to be transferred, the semiconductor layer (40) to be transferred being placed between the receiver substrate (20) and donor substrate (10), and - fracturing (S160) by annealing, referred to as the fracturing annealing (S160), the donor substrate (10) along the buried fragile plane (300), the first ions (3a) being chosen and implanted with a first dose (D1) so that, during the epitaxy (S130), there is no fracturing at the predetermined implantation depth (30), and the second ions (3b) being chosen and implanted with a second dose (D2) such that, during the fracturing annealing (S160), the donor substrate (10) fractures.

Description

DESCRIPTION TITLE: SEMICONDUCTOR LAYER TRANSFER PROCESS TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of methods for transferring semiconductor layers.

[0002] The present invention relates more particularly to a method of transferring a semiconductor layer by ion implantation, assembly and fracturing in which the semiconductor layer is reduced in defects before the assembly step. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] To increase the integration density of integrated circuits, a new technique called 3D monolithic integration involves stacking layers of electronic devices on top of each other.

[0004] Electronic devices are typically transistors. Each layer or level of transistors is formed in a semiconductor layer called an active layer. The first level of transistors is formed on the surface of an initial substrate, also called a wafer. The second level of transistors is fabricated from a semiconductor layer formed on the first level of transistors, in other words, above the surface of the initial substrate.

[0005] To obtain such a semiconductor layer, it is possible to transfer onto the initial substrate, called the receiving substrate, a semiconductor layer from another substrate, called the donor substrate. A known transfer technique called Smart Cut™ is based on the combination of implantation of light ions in the donor substrate, assembly by molecular adhesion of the donor and receiving substrates and fracturing annealing of the donor substrate.

[0006] This process involves 1) providing a donor substrate, typically a silicon wafer, 2) implanting ions, most commonly light ions such as hydrogen, through the surface of the donor substrate to create nanocavities buried within the donor substrate at a depth determined by the implantation depth, and delimit the semiconductor layer to be transferred, 3) the assembly of the donor substrate on a recipient substrate, then 4) a final annealing (heating) of the assembly which activates the formation of dihydrogen (H2). This gas feeds the nano-cavities and makes them grow. Due to the mechanical stress created by the interface between the assembled donor and recipient substrates, the nano-cavities widen and group laterally at the depth determined by the implantation, creating microcracks and a final fracture which quickly extends to the entire wafer. The separation of the semiconductor layer from the donor substrate and its transfer to the recipient substrate is then carried out.

[0007] This process offers many advantages and is well mastered. However, some problems remain, including a particular problem inherent to the light ion implantation step. Indeed, the implantation of light ions induces defects in the semiconductor layer that alter its electrical performance, and therefore its quality. These defects are linked to the fact that the ions induce defects of different natures (vacancies, interstitials, hydrogenated complexes, nano-cavities) not only around the determined implantation depth, but also along their path in the donor substrate. Thus, defects are present in the semiconductor layer, due to the implantation of light ions, with a density proportional to the dose at which the implantation is carried out. They affect the mobility of the charge carriers, and therefore the electrical characteristics of the semiconductor layer.It should be noted that the heating that takes place during fracturing annealing does not effectively heal the defects formed by implantation and may even lead to the growth / formation of new defects or cavities.

[0008] It is essential to reduce this number of defects in the semiconductor layer in order to guarantee satisfactory electrical performance for the electronic components that will be manufactured there, while maintaining an implantation dose adapted to the transfer of said semiconductor layer.

[0009] To achieve this, a conventionally used solution consists of reducing the number of defects after the transfer step, by subjecting the receiving substrate (which includes the transferred semiconductor layer) to high temperatures, i.e. temperatures above 900°C or 1000°C, applied for long periods of time, for example several hours. However, such temperatures should be avoided when the semiconductor layer has been transferred onto a receiving substrate. comprising a layer of previously formed electronic devices. Indeed, they cause a degradation of the performance, particularly electrical, of the electronic devices in this underlying layer. It is therefore out of the question to reduce in this way the defects created by the implantation of light ions.

[0010] In the context of a semiconductor layer transfer process based on light ion implantation, there is therefore a need to reduce the number of defects in the semiconductor layer other than by annealing carried out at high temperature after fracturing. SUMMARY OF THE INVENTION

[0011] The invention provides a solution to the problems mentioned above, by providing for replacing the single implantation step with two implantation steps and by carrying out an epitaxy step of the semiconductor layer between the two implantation steps. Furthermore, the implantation conditions of each of the implantation steps, in particular the implanted ions and the chosen implantation dose(s), are adapted according to the epitaxy and the fracturing annealing to induce fracturing only during the fracturing annealing.

[0012] One aspect of the invention thus relates to a method for transferring a semiconductor layer from a donor substrate to a receiving substrate, the method comprising the following successive steps: first implantation of first light ions in the donor substrate at a predetermined implantation depth so as to form a fragile plane buried at the predetermined implantation depth, epitaxy on the donor substrate of the semiconductor layer to be transferred, second implantation of second light ions in the donor substrate through the semiconductor layer to be transferred at the fragile plane, assembly by bonding of the receiving substrate and the donor substrate covered with the semiconductor layer to be transferred, the semiconductor layer to be transferred being arranged between the receiving and donor substrates, and fracturing by annealing, called fracturing annealing, of the donor substrate along the buried fragile plane, a process in which: the first ions are chosen and implanted at a first dose so that, during epitaxy, there is no fracturing at the predetermined implantation depth, the second ions are chosen and implanted at a second dose so that, during fracturing annealing, fracturing of the donor substrate takes place.

[0013] Thus, the implantation of the first light ions, that is to say ions whose atomic mass is less than or equal to 11, is carried out with a dose such that the first ions do not induce, during the epitaxy of the semiconductor layer to be transferred, a fracturing at the predetermined implantation depth.

[0014] Under these conditions, the thermal budget (defined by the temperature and the duration of application of this temperature) used during the epitaxy step does not lead to the growth and grouping of nano-cavities of the buried fragile plane, i.e. nano-cavities formed at the implantation depth predetermined by the first implantation. There are several reasons for this, among them the fact that the density of nano-cavities and / or the quantity of gas produced is not sufficient.

[0015] It should be noted that if a single implantation were performed before epitaxy, then the implanted ions would necessarily be chosen so that at the implanted dose there would be fracturing after assembly of the donor and recipient substrates. The implanted dose would therefore be high enough for the heat treatment inherent in epitaxy to lead to fracturing of the donor substrate. To avoid this, the epitaxy temperature would have to be limited to a maximum of 400°C. However, it is not currently possible to form a semiconductor layer at such a temperature.

[0016] The first implantation therefore makes it possible to carry out epitaxy without fracturing the donor substrate or without creating defects in the semiconductor layer.

[0017] Furthermore, the epitaxy of the semiconductor layer is followed by the second implantation. This second implantation is carried out substantially at the same depth as the first implantation (taking into account the epitaxial thickness) so that, during the fracture annealing, the fracturing of the donor substrate is obtained due to the accumulation of ions implanted during the first and second implantations. The implantation depth is mainly a function of the implantation energy of the ions. Software (such as SRIM for "Stopping and Range of Ions in Matter") can be used to simulate the required implantation energies. The two implantations take place in approximately the same plane. A difference of a few nanometers is possible, as the implanted ions can reach the nano-cavities of the fragile plane during the fracture annealing.

[0018] The semiconductor layer formed is thus advantageously crossed only by the ions implanted during the second implantation in a much smaller quantity than the light ions required when a single implantation is conventionally carried out.

[0019] The number of defects in the semiconductor layer is thus reduced before transfer and without resorting to a high-temperature annealing step.

[0020] According to a first embodiment variant, the method comprises, between the first implantation of light ions and the step of epitaxy of the semiconductor layer to be transferred, an additional step of surface preparation comprising the following successive sub-steps: deoxidation of a free surface of the donor substrate, annealing of the donor substrate under an atmosphere comprising hydrogen at a temperature greater than or equal to 400°C (and advantageously greater than or equal to 500°C) for a duration of between 5 seconds and 10 minutes.

[0021] The higher the thermal budget of this annealing including hydrogen, called H2 annealing, the lower the residual contamination of oxygen atoms at the interface between the substrate and the epitaxial semiconductor layer, and the better the quality of the transferred semiconductor layer. The impact of H2 annealing conditions on the quality of deposited films can be better understood by referring to Hartmann et al., “A benchmark of 300mm RP-CVD chambers for the low temperature epitaxy of Si and SiGe”, ECS Transactions, 86 (7) 219-231 (2018).

[0022] Thus, the surface of the donor substrate is prepared for epitaxy of the semiconductor layer to be transferred. This contributes to the formation of a semiconductor layer with a reduced number of defects.

[0023] According to a second embodiment variant, the method comprises the additional steps of: before the first implantation, a step of depositing a sacrificial layer on a free surface of the donor substrate, after the first implantation and before the step of epitaxy of the semiconductor layer to be transferred, a step of removing the sacrificial layer.

[0024] The combination of deposition and removal of the sacrificial layer aims to prepare the surface for epitaxy of the semiconductor layer to be transferred.

[0025] According to a first development of this second embodiment variant, the sacrificial layer is a dielectric layer.

[0026] The dielectric layer is, for example, a layer of silicon oxide. It acts as a protective layer, protecting the surface of the donor substrate from contamination or impurities. Since epitaxy is carried out on this surface, the semiconductor layer to be transferred will be formed under better conditions, and its quality will be improved.

[0027] According to a second development of this second variant embodiment, the sacrificial layer comprises a stack of a first sub-layer of silicon and germanium alloy, called the first etching stop layer, and a second sub-layer of dielectric material arranged on the first sub-layer, and the step of removing the sacrificial layer comprises removing the second dielectric sub-layer selectively with respect to the first etching stop layer and then removing the first etching stop layer.

[0028] The first etching stop layer, like the dielectric layer, protects the surface on which the epitaxy will be carried out from impurities likely to degrade the semiconductor layer.

[0029] Removing the first etch stop layer improves surface preparation by achieving lower surface roughness.

[0030] According to an alternative embodiment of the second previous development, the step of epitaxy of the semiconductor layer to be transferred is carried out less than 30 minutes after the step of removal of the first stop layer.

[0031] Preferably, the step of epitaxy of the semiconductor layer to be transferred is carried out less than 10 minutes after the step of removal of the first stop layer.

[0032] This short time limit limits the risk of contamination of the surface on which the epitaxy of the semiconductor layer to be transferred will be carried out.

[0033] According to another alternative embodiment of the second development, the step of removing the first etching stop layer and the step of epitaxy of the semiconductor layer to be transferred are carried out in the same equipment.

[0034] This reduces the risk of surface contamination and simplifies the process.

[0035] Advantageously, the method comprises, after the step of removing the first etching stop layer and before the step of epitaxy of the semiconductor layer to be transferred, an additional step of annealing the donor substrate carried out in the same equipment as the step of removing the first stop layer and the step of epitaxy of the semiconductor layer to be transferred.

[0036] This step of annealing the donor substrate carried out in situ in the epitaxy equipment makes it possible to complete the step of removing the first etching stop layer and to improve the quality of the surface on which the semiconductor layer to be transferred will be formed.

[0037] Advantageously, the additional step of annealing the donor substrate is carried out at the following temperature, pressure and time conditions: 500°C, 2666 Pa (or 20 Torr), 2 minutes.

[0038] With such a thermal budget, the properties of the layer (or fragile plane) damaged by the first implantation are still compatible with a layer transfer after the second implantation.

[0039] In addition to the characteristics which have just been mentioned in the preceding paragraphs, the method according to one aspect of the invention may have one or more additional characteristics among the following, compatible with all previous embodiment variants and considered individually or in all technically possible combinations.

[0040] The first light ions are helium ions, hydrogen ions, boron ions, a mixture of helium ions and hydrogen ions, or a mixture of hydrogen ions and boron ions.

[0041] The second light ions are helium ions, hydrogen ions, or a mixture of helium ions and hydrogen ions.

[0042] It should be noted that it is particularly advantageous to use hydrogen ions for the second implantation, rather than helium ions, because these induce fewer defects, even if the implantation dose is higher.

[0043] The semiconductor layer to be transferred is a layer of silicon (or Si), germanium (or Ge), an alloy of silicon and germanium (or SiGe), an alloy of silicon, germanium and carbon (or SiGeC), an alloy of germanium and tin (or GeSn) or an alloy of silicon, germanium and tin (SiGeSn), or a stack of a sub-layer of silicon and a sub-layer of an alloy of silicon and germanium (Si / SiGe).

[0044] Alternatively, the semiconductor layer to be transferred comprises a first so-called active sub-layer of silicon (or Si), germanium (or Ge), an alloy of silicon and germanium (or SiGe), an alloy of silicon, germanium and carbon (or SiGeC), an alloy of germanium and tin (or GeSn) or an alloy of silicon, germanium and tin (SiGeSn), and a second so-called etch stop sub-layer such as an etch stop sub-layer of silicon and germanium alloy, arranged under the first active sub-layer, and the receiving substrate has, after the fracturing step, a residual layer originating from the donor substrate, the method then comprising the following successive steps: Removal of the residual layer from the donor substrate by selective etching of said residual layer relative to the second etching stop sub-layer, Removing the second etch stop sub-layer.

[0045] Thanks to the etch stop underlayer and the selective etching step of the residual layer after the transfer, no chemical-mechanical polishing is required. necessary to remove the residual layer from the donor substrate. In addition, the surface roughness of the transferred layer is reduced and its thickness controlled to achieve thinner thicknesses. The quality of the transferred layer is thus further improved.

[0046] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0047] The figures are presented for information purposes only and in no way limit the invention. Figures 1A to 1G schematically represent steps of the transfer method according to the invention, Figure 2 represents several variants of the epitaxy step of the transfer method of Figures 1 A to 1 G, Figure 3 shows the final multilayer structure obtained with the transfer process of Figures 1 A to 1 G, Figures 4A to 4K schematically represent a first particular embodiment of the method of Figures 1A to 1G, making it possible to improve the quality of the semiconductor layer, Figures 5A to 5M schematically represent a second particular embodiment of the method of Figures 1A to 1G, also making it possible to improve the quality of the semiconductor layer, Figure 6 schematically represents a first test substrate allowing the first implantation dose to be determined, Figure 7 is a block diagram showing the sequence of steps for determining the first maximum dose of the first implantation step of Figure 1 B, Figure 8 schematically represents a second test substrate allowing the second implantation dose to be determined, Figure 9 is a block diagram showing the sequence of steps for determining the second minimum dose of the second implantation step of Figure 1 D, Figure 10 represents the density of defects generated in a silicon substrate by an implantation of hydrogen ions, and by an implantation of a mixture of helium and hydrogen ions, Figure 11 represents the etching rate of a SiGe layer, as a function of the etching partial pressure and as a function of the percentage of Ge in the SiGe alloy, Figure 12 is a block diagram showing the sequence of steps for implementing an additional surface preparation step, this step being between the second step and the third step of the process shown in Figures 1A to 1G.

[0048] Unless otherwise specified, the same element appearing in different figures has a single reference. DETAILED DESCRIPTION

[0049] Figures 1A to 1G represent a schematic sectional view of steps S110 to S160 of a method for transferring a semiconductor layer 40 from a donor substrate 10 to a recipient substrate 20, which makes it possible to obtain a semiconductor layer 40 reduced in defects.

[0050] By "defects" we mean nano-cavities, gaps, interstitials, hydrogen complexes, bubbles, exfoliations present in the semiconductor layer or on its surface, and causing a degradation of its electrical performance.

[0051] This transfer process includes, like the Smart Cut™ process of the prior art, the implantation of light ions, the assembly of two substrates by bonding and a fracturing anneal.

[0052] The transfer method according to the invention is remarkable in that it comprises, before the actual transfer carried out by the bonding steps S150 and fracturing S160 (figure 1 E and figure 1 F), two implantation steps S120 and S140 (Figure 1 B and Figure 1 D) of light ions and an epitaxy step S130 (Figure 1 C) interposed between these two implantation steps S120 and S140.

[0053] With reference to FIG. 1A, the transfer method begins at the first step S110 with the provision of a donor substrate 10. The donor substrate 10 designates a support substrate, preferably a semiconductor substrate, for example made of silicon. Generally, the term “substrate” refers to a wafer or slice.

[0054] The donor substrate 10 has an upper face 11, called the free surface, which is substantially flat.

[0055] With reference to Figure 1B, the first step S110 is followed by a step S120 of implanting first light ions 3a in the donor substrate 10, through the free surface 11, at a predetermined depth 30, called the implantation depth. This first implantation S120 makes it possible to create defects in the donor substrate 10 in a so-called fragile plane 300 located at the implantation depth 30. The plane 300 is said to be fragile because the defects created weaken the donor substrate 10.

[0056] The implantation depth 30 is for example between 100 nm and 1000 nm. It is measured from the free surface 11 and perpendicular to this same surface. For example, the implantation S120 of the first ions is carried out at an energy such that the maximum of the profile of the implanted ions is found at a depth of approximately 300 nm.

[0057] This implantation energy depends on the ion species or ion species chosen. If the first species implanted is helium, it is of the order of 35 keV to obtain an implantation depth of 300 nm.

[0058] Light ions are species defined by an atomic mass less than or equal to 11. The first 3a ions are preferentially chosen from hydrogen (or H), helium (or He), boron (or B), a mixture of helium and hydrogen (or "He+H") or a mixture of hydrogen and boron (or "H+B"). It is indeed known that these species make it possible to create a buried fragile plane likely to lead to a transfer by Smart Cut™.

[0059] In the Smart Cut™ process, the light ion implantation step is typically combined with an annealing step performed at an annealing temperature generally between 350°C and 600°C to fracture the donor substrate and transfer the semiconductor layer.

[0060] In the method according to the invention, step S120 of implantation of the first ions 3a is not followed by a “conventional” annealing step, but is followed by an epitaxy step S130, illustrated in FIG. 1 C, aimed at forming the semiconductor layer 40.

[0061] Figure 2 shows several variants of embodiment of this epitaxy step S130.

[0062] At the end of this step S130, the semiconductor layer 40 may be a semiconductor layer 410, preferably thin, i.e. with a thickness of between 5 nm and 30 nm, and formed from one of the following materials: silicon (or Si), germanium (or Ge), silicon and germanium alloy (or SiGe), silicon, germanium and carbon alloy (or SiGeC), germanium and tin alloy (or GeSn) or silicon, germanium and tin alloy (SiGeSn).

[0063] The semiconductor layer 40 may, alternatively, be a stack of semiconductor sub-layers, for example a stack of a silicon sub-layer and a silicon and germanium alloy (Si / SiGe) sub-layer or, preferably, a stack of a first so-called active sub-layer 430 and a second so-called etch stop sub-layer 420 such as an etch stop sub-layer of silicon and germanium alloy (SiGe). The etch stop sub-layer 420 is arranged under the active sub-layer 430.

[0064] The active sub-layer 430 is then similar to the semiconductor layer 410, that is to say it is formed from one of the following materials: silicon (or Si), silicon and germanium alloy (or SiGe), silicon, germanium and carbon alloy (SiGeC), germanium and tin alloy (or GeSn) or silicon, germanium and tin alloy (SiGeSn) and its thickness is between 2 nm and 30 nm. The etch stop sub-layer 420 is preferably made of a SiGe alloy with a germanium concentration of between 20% and 50%. The etch stop sub-layer 420 may also have a thickness of between 5 nm and 150 nm.

[0065] More generally, the stack of semiconductor sub-layers may comprise several active sub-layers and etch stop sub-layers arranged alternately (not shown in Figure 2). The thickness of the active and etch stop sub-layers may vary depending on their position in the stack, as may the Si / Ge ratio forming the etch stop sub-layer.

[0066] This epitaxy step S130 is carried out in epitaxy equipment, and consists of growing in an oriented manner, from the free surface 11 of the donor substrate 10 implanted with the first ions, a crystal corresponding to the desired crystal for the semiconductor monocrystalline layer 40. The epitaxy step may comprise the formation of a crystalline sub-layer, called a germination layer (not shown), on the free surface 11. The semiconductor layer 40 is then epitaxially grown following this sub-layer. The semiconductor layer 40 may be formed by chemical vapor deposition (or CVD, acronym for Chemical Vapor Deposition), such as reduced pressure chemical deposition (RP-CVD, for Reduced Pressure - Chemical Vapor Deposition) or plasma-enhanced chemical vapor deposition (PECVD, for Plasma-Enhanced Chemical Vapor Deposition).Techniques such as molecular beam epitaxy (MBE) can also be used. In RP-CVD, the operating points described in Hartmann et al., “Potentialities of disilane for the low temperature epitaxy of intrinsic and boron-doped SiGe”, Thin Solid Films 557, 19 (2014), Aubin et al., “Epitaxial growth of Si and SiGe at temperatures lower than 500 °C with disilane and germane”, Thin Solid Films 602, 36 (2016) or Hartmann et al., “A benchmark of germane and digermane for the low temperature growth of intrinsic and heavily in-situ boron-doped SiGe”, ECS Transactions 75 (8), 281 (2016) can be used to deposit Si or SiGe layers at low temperatures (500 °C and below).

[0067] To deposit pure Ge layers at temperatures lower than or equal to 500°C, one could use epitaxy conditions similar to those described in Aubin et al., “Very low temperature epitaxy of Ge and Ge rich SiGe alloys with Ge2Hô in a Reduced Pressure - Chemical Vapour Deposition tool”, Journal of Crystal Growth 445, 65 (2016).

[0068] Finally, growth conditions allowing epitaxy at temperatures lower than or equal to 350°C of GeSn or SiGeSn layers can be found in Aubin and Hartmann, “GeSn growth kinetics in reduced pressure chemical vapor deposition from Ge2H6 and SnCI4”, Journal of Crystal Growth 482, 30 (2018) and Khazaka et al., “Growth and characterization of SiGeSn pseudomorphic layers on 200mm Ge virtual substrates”, Semiconductor Science and Technology 33, 124011 (2018).

[0069] These techniques require applying a temperature T ep , called epitaxy temperature Tep , which can vary between 300°C and 600°C for a period of ep , called epitaxy duration d ep ranging from 1 min to 120 min. The epitaxy temperature T ep is for example 500°C and the epitaxy duration of ep of 10 minutes.

[0070] It should be noted that the temperatures involved in this epitaxy step S130 can produce the same effects as a fracturing anneal on the first implanted 3a ions. For this reason, the first implantation (and in particular the first implanted 3a ions and the first implantation dose(s) chosen) is determined according to the temperature and duration conditions of the epitaxy step S130, to avoid (and not obtain) a fracturing of the donor substrate 10 during the epitaxy step S130. Indeed, in the opposite case, in the absence of particular mechanical constraint (or stiffener) in the donor substrate 10 (the latter not yet being assembled to the receiving substrate 20), the nano-cavities supplied with gas are free to extend both laterally and vertically, which causes the appearance of bubbles, blisters, exfoliations on the surface and in the semiconductor layer 40 being formed which will therefore be defective.

[0071] For this, we can choose as first ions 3a light ions that do not generate bubbling with the thermal budget of the S130 epitaxy. This will be the case for example if we implant boron or helium. The heavier the implanted atom (He, B), the more it is beneficial to implant it before the S130 epitaxy to limit damage to the transferred semiconductor layer 40.

[0072] Preferably, the first light ions 3a are helium ions.

[0073] If the first implantation S120 is carried out with hydrogen, a first dose D1 will be used which is lower than a first threshold S1 from which the first light ions 3a induce, during epitaxy S130, a fracturing at the predetermined implantation depth 30.

[0074] The first threshold S1 can be predetermined experimentally using a first test substrate 6 as shown in FIG. 6. The first test substrate 6 comprises several test areas, for example four test areas Q11, Q12, Q13 and Q14. Each test area is subjected to an implantation of the first ions with a test dose, and to a heat treatment at the temperature T ep of the S130 epitaxy, during the duration of ep of epitaxy.

[0075] The first threshold S1 is then determined by visual inspection and search for the presence of surface exfoliations which indicates that fracturing and therefore a layer transfer would take place if a mechanically constraining interface (such as the interface between the donor 10 and recipient 20 substrates when they are assembled) were present.

[0076] Preferably, the first threshold S1 is determined by following the sequence of steps S710 to S730 of figure 7.

[0077] These steps are as follows: implantation S710 of the first light ions 3a on a first test area Q11 of the test substrate 6, at the implantation energy of the first light ions 3a, and with a low first test dose DT1 i, for example 1 e 16 / cm 2 . S720 heat treatment of test substrate 6 at epitaxy temperature Tep for epitaxy duration d ep , control S730 of the free surface 66 of the test substrate 6, preferably visual control on images of the test area acquired by optical microscopy, If the free surface 66 is damaged (output “D” of step S730), the first threshold S1 is equal to the first test dose DT1 i, If the free surface is not damaged (output “ND” of step S730), the first test dose DTI2 is increased (DTI2 > DT1 i) and the implantation steps S710, heat treatment S720 and control S730 are repeated on the following test area QI2, this by applying to the implantation step S710 the increased test dose DI 2.

[0078] By "damaged free surface" is meant the presence of blisters or exfoliations on the free surface 66. This damage corresponds to dark points on optical microscopy images and is easily detectable (see points P in image IMG1 of figure 7).

[0079] By "undamaged free surface 66" is meant the absence of blisters or exfoliation on the free surface 66. On the images acquired by optical microscopy, no dark points are detected (see IMG2 of figure 7).

[0080] For this first S120 implantation, it will also be possible to combine several 3a ions, including helium and / or boron with hydrogen. The more species implanted during this first implantation, the fewer will be needed during the second implantation and therefore the less damage will be done to the epitaxial layer.

[0081] After the epitaxy step S130 described previously, a second light ion implantation step, called implantation step S140 of second light ions 3b, is carried out. This step S140 is illustrated in FIG. 1 D and is associated with the subsequent step S160, illustrated in FIG. 1 E, consisting of a fracturing annealing step S150 carried out at a fracturing annealing temperature TRF and for a fracturing annealing time dRF.

[0082] The second 3b ions are light species such as helium He, hydrogen H, or a mixture of helium and hydrogen ("H+He"). The second 3b ions can be the same as the first 3a ions.

[0083] Preferably, the second light 3b ions comprise or are hydrogen ions.

[0084] The depth of this second implantation S140 is the implantation depth 30 determined during the first implantation S120 of the first ions 3a to which is added the thickness of the epitaxially grown semiconductor layer 40. The energy at which the second implantation S140 is carried out is such that the maximum of the implantation profile is superimposed on that of the first implantation S120.

[0085] Referring to Figure 1D, the second implantation S140 is performed in the donor substrate 10, through the semiconductor layer 40 to be transferred, so that the second ions 3b reach the buried fragile plane 300.

[0086] The fragile plane 300 is then a plane in which the density of nano-cavities and the overall content of light ions, that is to say the cumulative content of first light ions 3a and second light ions 3b, make it possible, during the fracturing annealing step S160, to trigger the formation of gaseous complexes leading to the fracturing of the donor substrate 10.

[0087] For this, the second implantation S140 is accomplished with ions 3b implanted at one or more doses such that, during the fracturing annealing S160, the accumulation of the first ions 3a and the second ions 3b induces a fracturing of the donor substrate 10, following the buried fragile plane 300.

[0088] If the second implantation S140 comprises hydrogen ions implanted at a second dose D2, this dose is preferably predetermined experimentally, based, in a similar manner to the determination of the first threshold S1, on the presence / absence of exfoliations on the surface of a second test substrate such as the second test substrate 8 illustrated in figure 8.

[0089] Similar to the first test substrate 6, the second test substrate 8 can be divided into several test areas, for example four areas Q21, Q22, Q23 and Q24.

[0090] Steps S910 to S950 (see Figure 9) are carried out there. They consist of: the implantation S910 of the first ions 3a on a first zone Q21, at the implantation energy of the first ions. For example, Helium ions are implanted with an energy of 35 keV (so as to create a fragile plane at a depth of 300 nm relative to the surface) and a dose D1 of 2 e 16 / cm 2), the S920 epitaxy of the second test substrate 8 at the epitaxy temperature Tep and during the epitaxy duration d ep , to create an epitaxial layer for example of 30 nm the S930 implantation of the second ions 3b with an implantation energy so that these ions reach the buried fragile plane. If the implanted ions are hydrogen, they will be implanted with an energy of 24 keV to reach the fragile plane located at 330 nm from the surface. These ions will be implanted with a second low DT2i test dose, for example equal to 1 E16 / cm 2 , S940 heat treatment of the second test substrate 8 at the fracturing annealing temperature TRF and for the duration of the fracturing annealing dRF, S950 control of the quality of the free surface 88 of the second test substrate 8, if the surface quality is deteriorated (output "D" of the control step S950), the second dose D2 is equal to or greater than the second test dose DT21, if the surface quality is not deteriorated (output "ND" of the control step S950), the test dose DT2i is increased and the test steps S910 to S930 are repeated on another test area Q22, the implantation step S930 of the second ions 3b being accomplished with the increased second test dose DT22.

[0091] By applying these steps, we obtain, for example, the fracturing conditions given in Table 1 or the fracturing conditions given in Table 2. By "fracturing conditions" we mean all the parameters linked to the S120 implantation of the first ions, to the S130 epitaxy, to the S140 implantation of the second ions, and to the S160 fracturing annealing.

[0092] [table 1]

[0093] [table 2]

[0094] It should be noted that using an epitaxy temperature T ep higher (500°C, see table 2 compared to 400°C, see table 1) leads to a higher first dose D1 (2 e 16 / cm 2 compared to 1.3 e 16 / cm 2 ) and a second, larger dose of D2 (2 e 16 / cm 2 compared to 9 e 15 / cm 2 ).

[0095] It should also be noted that then the overall dose (He 36keV 2 e 16 / cm 2 and H 24 keV 2 e 16 / cm 2) is higher than the dose applied in a standard way in the case of a single implantation of light ions. However, the defects created are fewer in number, in particular because the helium ions do not cross the transferred semiconductor layer 40. As illustrated in Figure 10, the density of displaced atoms is in fact lower when hydrogen ions are implanted, compared to helium ions, even for a hydrogen ion implantation dose greater than twice the helium ion implantation dose.

[0096] With reference to Figure 1 E, the method then comprises a step S150 of assembling by bonding the receiver substrate 20 and the donor substrate 10 covered with the semiconductor layer 40 to be transferred. The donor substrate 10 having been previously turned over, the semiconductor layer 40 to be transferred is arranged between the receiver substrates 20 and donor 10, in the assembly 1 formed.

[0097] The receiving substrate 20 is a substrate preferably comprising one or more layers of electronic devices 210.

[0098] This assembly step S150 is carried out using a conventional bonding process, preferably a molecular adhesion bonding process, also called direct bonding.

[0099] The assembly step S150 is followed by a step S160 of fracturing by annealing, also called fracturing annealing step S160, of the donor substrate 10 along the buried fragile plane 300. The temperature of the fracturing annealing is in a range from 400°C to 600°C, and preferably less than or equal to 500°C. The duration of the fracturing annealing is preferably between 30 minutes and 180 minutes.

[0100] At the end of this annealing fracturing step S160, a portion 10b of the donor substrate 10 is separated from the receiving substrate 20 on which the transferred semiconductor layer 40 is arranged, as well as a residual layer 10a from the donor substrate 10. The transfer of the semiconductor layer 40 is thus carried out.

[0101] With reference to Figure 1 G, the fracturing step S160 can be followed by an optional step S170 of removing the residual layer 10a from the donor substrate 10 until reaching the semiconductor layer 40. At the end of this step S170 of removing the residual layer 10a, the final semiconductor structure 3, illustrated in Figure 3, is obtained.

[0102] Figures 4A to 4K schematically represent a first particular embodiment of the transfer method which has just been described in general.

[0103] Figures 5A to 5M schematically represent a second particular embodiment of the transfer method.

[0104] The steps of providing S110 the donor substrate 10, of first implantation S120, and of second implantation S140, illustrated respectively in FIG. 4A and FIG. 5A, in FIG. 4C and FIG. 5D, and in FIG. 4G and FIG. 5I, are as described previously, respectively in relation to FIG. 1A, FIG. 1B, and FIG. 1D.

[0105]

[0106] In a manner common to these two particular embodiments, the epitaxy step S130 comprises two sub-steps S130A and S130B to form a semiconductor layer 40 comprising the active sub-layer 430 and the etching stop sub-layer 420 illustrated in FIG. 2, as well as two additional steps S170 (see FIG. 4J and FIG. 5L) and S180 (see FIG. 4K and FIG. 5M) carried out after the assembly steps S150 (see FIG. 4H and FIG. 5J) and fracturing S160 (see FIG. 4I and FIG. 5K) and aimed at releasing the active sub-layer 430.

[0107] With reference to Figure 4E (first embodiment) and Figure 5G (second embodiment), step S130A consists of the epitaxial growth of the so-called etching stop sub-layer 420 from the free surface 11 of the donor substrate 10. The epitaxial temperature is for example 500°C.

[0108] With reference to Figure 4F (first embodiment) and Figure 5H (second embodiment), step S130B consists of the epitaxial growth of the so-called active sub-layer 430 from the etching stop sub-layer 420. This epitaxy S130B is preferably carried out at the same epitaxy temperature as the epitaxy S130A of the etching stop sub-layer, i.e. here 500°C.

[0109] With reference to Figure 4J (first embodiment) and Figure 5L (second embodiment), the receiving substrate 20 has, after the fracturing step S160, a residual layer 10a originating from the donor substrate 10 on the surface of the etching stop sub-layer 420. Step S170 is then a step of removing S170 the residual layer 10a originating from the donor substrate 10, by etching said residual layer 10a selectively with respect to the second etching stop sub-layer 420. This selective etching is preferably a wet etching.

[0110] Step S180, which follows step S170, is a step of removing by selective etching (preferably wet) the etching stop sub-layer 420 with respect to the active sub-layer 430.

[0111] At the end of step S180 of removing the etching stop sub-layer 430, the active sub-layer 430 is released and advantageously has a smooth surface and a reduced thickness.

[0112] Also in common to the first embodiment and the second embodiment, the transfer method further comprises one or more steps aimed at preparing the free surface 11 of the donor substrate 10 for the epitaxy S130 of the semiconductor layer 40.

[0113] In the first embodiment, the preparation of the surface for epitaxy S130 comprises the additional steps S115 and S125 illustrated respectively in Figure 4B and Figure 4D.

[0114] In the second embodiment, the preparation of the surface for epitaxy S130 comprises the additional steps S115A, S115B and S125A and S125B, illustrated respectively in Figure 5B, Figure 5C and Figure 5E and Figure 5F.

[0115] The surface preparation as performed in the first embodiment is described first below.

[0116] Step S115 (figure 4B) takes place before the implantation S120 of the first ions 3a, and consists of the formation of a sacrificial layer 50 on the free surface 11 of the donor substrate 10. Preferably, the sacrificial layer 50 is a dielectric layer 500, for example a layer of silicon oxide (or SiCh).

[0117] The dielectric layer 500 is obtained by oxide growth or by deposition of the dielectric from the free surface 11 of the donor substrate 10.

[0118] At the end of step S115, the donor substrate 10 therefore comprises a so-called sacrificial dielectric layer which advantageously protects the free surface from defects and impurities (for example carbon or oxygen atoms). In the implantation step S120 of the first ions 3a, the first ions 3a will be implanted through the sacrificial dielectric layer 50,520.

[0119] Step S125 (FIG. 4D) takes place after the implantation S120 of the first ions and before step S130 of epitaxy of the semiconductor layer 40 to be transferred. Step S125 consists of removing the sacrificial layer 50, 510 formed in step S115.

[0120] This removal is carried out, for example, by wet etching using a hydrofluoric acid-based solution.

[0121] At the end of step S125, the free surface 11 of the donor substrate 10 advantageously has a clean surface, i.e. one free of impurities or contaminants.

[0122] In the second embodiment (see FIG. 4C), the sacrificial layer 50 comprises a stack of a first sub-layer 510, called the first etch stop layer 510, and a second dielectric sub-layer 520 arranged on the first sub-layer 510.

[0123] Thus, step S115A is a step of forming the first etch stop layer 510 and step S115B is a step of forming the second dielectric sub-layer 520.

[0124] The dielectric is preferably silicon oxide.

[0125] The first etch stop layer 510 is for example a layer of silicon and germanium alloy (SiGe) with the following proportions 25% (Si) and 50% (Ge).

[0126] In step S115A, the formation of the first etching stop layer 510 is preferably carried out by epitaxial growth from the free surface 11 of the donor substrate 10. The thickness of the first etching stop layer 510 thus obtained is between 10 and 50 nm. The epitaxy of the first etching stop layer 510 may further be preceded by a surface preparation step carried out according to state-of-the-art methods, preferably at temperatures above 650°C, more preferably at temperatures above 850°C.

[0127] In step S115B, the second dielectric sub-layer 520 is obtained by growing oxide from the surface of the first etching stop layer 510, or by depositing the dielectric on the surface of the first etching stop layer 510, in order to obtain a second dielectric sub-layer 520 with a thickness of between 5 and 50 nm.

[0128] Removal step S125A (Figure 5E) is a removal step S125A of the second dielectric sub-layer 520.

[0129] The removal of the second dielectric sub-layer 520 is for example carried out using wet etching based on a solution comprising hydrogen fluoride.

[0130] The removal step S125B (FIG. 5F) of the first etching stop layer 510 can be carried out outside the epitaxy equipment or in the epitaxy equipment (this is then referred to as in-situ removal).

[0131] In the first case (apart from the epitaxy equipment), step S125B consists of carrying out a selective wet etching with respect to the SiGe, for example using a wet etching based on a solution comprising acetic acid, hydrogen fluoride, and hydrogen peroxide (or H2O2), then carrying out the epitaxy step S130 in a time interval preferably between 10 minutes and 30 minutes.

[0132] In other words, the time interval between the removal step S125B by wet etching of the first etching stop layer 510 and the epitaxy step S130 of the semiconductor layer 40 to be transferred is then preferably between 10 minutes and 30 minutes.

[0133] In the second case, the step S125B of removing the first etching stop layer 510 is carried out in the epitaxy equipment. In other words, the step S125B of removing the first etching stop layer 510 and the epitaxy step S130 are carried out in the same epitaxy equipment.

[0134] The S125B removal is then carried out by wet etching based on a solution comprising hydrochloric acid (or HCl) and at a temperature preferably below 500°C. Advantageously, the etching is selective with respect to the silicon of the donor substrate 10. With reference to FIG. 11, a partial pressure of HCl of 23998 Pa to 47996 Pa (i.e. 180 or 360 Torr) can be used. At a temperature of 500°C, the etching rates (or ER for Etching Rate in English), represented on the y-axis, are such that the etching of the SiGe is selective with respect to the silicon of the donor substrate 10. Advantageously, the etching selectivity, i.e. the ratio between the etching rate of a SiGe layer and that of the Si, is of the order of 13 for a Ge concentration in the etching stop layer 510 of 20%, of the order of 50 for a Ge concentration of 30% and of the order of 186 for a Ge concentration of 40%.

[0135] The removal S125B is then followed by the epitaxy step S130 described previously, which can then, in addition, be followed by an additional step S132 (not shown) of annealing after epitaxy of the donor substrate 10, carried out in the same epitaxy equipment as the removal step S125B of the first stop layer 510 and the epitaxy step S130 of the semiconductor layer 40 to be transferred.

[0136] The first and second embodiments represent two ways of preparing the free surface 11 of the donor substrate 10 for epitaxy S 130.

[0137] A third way of preparing the free surface 11 is shown in Figure 12 with step S122. This step S122 consists of carrying out, between the implantation S120 of the first light ions and the epitaxy step S130 of the semiconductor layer 40 to be transferred, the following successive sub-steps: deoxidation S122A of the free surface 11 of the donor substrate 10, S122B annealing of the donor substrate 10, under an atmosphere comprising hydrogen at a temperature above 400°C, for a period of between 5 seconds and 10 minutes, typically.

[0138] The deoxidation step S122A is for example carried out chemically, under hydrogen fluoride (or HF), and is followed by surface cleaning by an SC1 ™ process (i.e. exposure of the surface to a chemical solution NH4OH:H2O2:H2O, leading to the formation of a silicon oxide) then a SICONI ™ process (i.e. (i) conversion, using a remote plasma based on NH3 and NF3, of the silicon oxide formed by the SC1 ™ process into an oxide salt, followed by sublimation of this salt under neutral gas at a temperature below 200°C). The temperatures used are then preferably less than or equal to 500°C.

[0139] The annealing step S122B following the deoxidation step S122A- is preferably performed in the epitaxy equipment. The annealing temperature may be lower than 500°C. To achieve optimal surface preparation, the temperature may be higher, for example the temperature may be higher than 500°C, 650°C, or even higher than 800°C. In this case, the annealing time is preferably as short as possible, in a range of 5 seconds to 10 minutes.

[0140] At the end of this additional step S122, the free surface 11 of the donor substrate 10 is, before the epitaxy S130, advantageously reduced in contaminants (carbon, fluorine, oxygen, etc.).

[0141] The method may further comprise, after the epitaxy S130 and before the implantation S140 of the second ions 3b, an additional step S135 (not shown) of forming an oxide layer produced by epitaxial growth from the semiconductor layer 40 formed at the end of step S130 (or S130B). This step S135 is preferably carried out under oxidation plasma at a temperature below 500°C or below 400°C. It may also be carried out by plasma-assisted chemical vapor deposition.

[0142] By using two implantation steps (first implantation S120 and second implantation S140) carried out respectively with the first ions 3a and the first dose(s) and with the second ions 3b and the second dose(s), and by intercalating the epitaxy of the semiconductor layer 40 between these two implantation steps, the transfer method makes it possible to limit the negative impact of implantation, that is to say to limit the damage or defects induced by the implanted species, along their path in the donor substrate 10. The method therefore makes it possible to obtain a semiconductor layer 40 reduced in defects, this before the transfer step S150-S160.

[0143] There are several explanations for this: first, the first ions 3a and the first dose(s) are adapted so that, during epitaxy, the first ions 3a do not induce the growth of the nano-cavities towards the free surface 11 and in the semiconductor layer 40 being formed; then, the semiconductor layer 40 is only crossed by the second ions 3b, at a second dose reduced compared to a dose corresponding to a single implantation.

[0144] Fracture annealing temperatures of 500°C or less can be employed, as described previously, making the transfer process compatible with 3D monolithic integration.

Claims

Tl CLAIMS

1. A method of transferring a semiconductor layer (40) from a donor substrate (10) to a recipient substrate (20), the method comprising the following successive steps: - first implantation (S120) of first light ions (3a) in the donor substrate (10) at a predetermined implantation depth (30) so as to form a buried fragile plane (300) at the predetermined implantation depth (30), - epitaxy (S130) on the donor substrate (10) of the semiconductor layer (40) to be transferred, - second implantation (S140) of second light ions (3b) in the donor substrate (10) through the semiconductor layer (40) to be transferred at the fragile plane (300), - assembly (S150) by bonding the receiver substrate (20) and the donor substrate (10) covered with the semiconductor layer (40) to be transferred, the semiconductor layer (40) to be transferred being arranged between the receiver substrate (20) and donor substrate (10), and - fracturing (S160) by annealing, called fracturing annealing (S160), of the donor substrate (10) along the buried fragile plane (300), a process in which: - the first ions (3a) are chosen and implanted at a first dose (D1) so that, during epitaxy (S130), there is no fracturing at the predetermined implantation depth (30), - the second ions (3b) are chosen and implanted at a second dose (D2) so that, during the fracturing annealing (S 160), the fracturing of the donor substrate (10) takes place.

2. A method according to claim 1 wherein: - the first light ions (3a) are helium ions, hydrogen ions, boron ions, a mixture of helium ions and hydrogen ions or a mixture of hydrogen ions and boron ions, and the second light ions (3b) are helium ions, hydrogen ions or a mixture of helium ions and hydrogen ions.

3. Method according to one of claims 1 to 2 comprising, between the first implantation (S120) and the epitaxy step (S130) of the semiconductor layer (40) to be transferred, an additional surface preparation step (S122) comprising the following successive sub-steps: - deoxidation (S122A) of a free surface (11) of the donor substrate (10), - annealing (S122B) of the donor substrate (10) under an atmosphere comprising hydrogen at a temperature greater than or equal to 400°C, for a duration of between 5 seconds and 10 minutes.

4. A method according to any one of claims 1 to 2, comprising the additional steps of: - before the first implantation (S120), a step of depositing (S115) a sacrificial layer (50) on a free surface (11) of the donor substrate (10), - after the first implantation (S120) and before the epitaxy step (S130) of the semiconductor layer (40) to be transferred, a removal step (S125) of the sacrificial layer (50).

5. The method of claim 4 wherein the sacrificial layer (50) is a dielectric layer (500).

6. Method according to claim 4 in which the sacrificial layer (50) comprises a stack of a first sub-layer of silicon and germanium alloy (510), called first etch stop layer (510), and a second sub-layer (520) of dielectric material arranged on the first sub-layer (510), and the step of removing (S125) the sacrificial layer (50) comprises removing (S125A) the second sub-layer (520) of dielectric material then removing (S125B) the first etch stop layer (510).

7. The method of claim 6 wherein the step of epitaxy (S130) of the semiconductor layer (40) to be transferred is carried out less than 30 minutes after the step of removal (S125B) of the first barrier layer.

8. The method of claim 6, wherein the step of removing (S125B) the first etching stop layer (510) and the step of epitaxy (S130) the semiconductor layer (40) to be transferred are carried out in the same equipment.

9. Method according to claim 8 comprising, after the step of removing (S125B) the first stop layer and before the step of epitaxy (S130) of the semiconductor layer (40) to be transferred, an additional step (S132) of annealing the donor substrate (10) carried out in the same equipment as the step of removing (S1225B) the first etching stop layer (510) and the step of epitaxy (S130) of the semiconductor layer (40) to be transferred.

10. The method of claim 9 wherein the annealing (S132) of the donor substrate (10) is carried out at the following temperature, pressure and time conditions: 500°C, 2666 Pa, 2 minutes.

11. Method according to one of claims 1 to 10 in which the semiconductor layer (40) to be transferred is a layer (410) of silicon (or Si), germanium (or Ge), an alloy of silicon and germanium (or SiGe), an alloy of silicon, germanium and carbon (or SiGeC), an alloy of germanium and tin (or GeSn) or an alloy of silicon, germanium and tin (SiGeSn), or a stack of a sub-layer of silicon and a sub-layer of an alloy of silicon and germanium (Si / SiGe).

12. Method according to one of claims 1 to 11 in which the semiconductor layer (40) to be transferred comprises a first so-called active sub-layer (430) of silicon (or Si), germanium (or Ge), an alloy of silicon and germanium (or SiGe), an alloy of silicon, germanium and carbon (or SiGeC), an alloy of germanium and tin (or GeSn) or an alloy of silicon, germanium and tin (SiGeSn), and a second so-called etch stop sub-layer (420) such as an etch stop sub-layer of silicon and germanium alloy, arranged under the first active sub-layer (430), and the receiving substrate (20) has, after the fracturing step (S160), a residual layer (10a) originating from the donor substrate (10), the method then comprising the following successive steps: - Removal (S170) of the residual layer (10a) from the donor substrate (10) by selective etching of said residual layer (10a) with respect to the second etch stop sub-layer (420), with a selectivity greater than 10, - Removal (S180) of the second etch stop sub-layer (420).

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