Process for manufacturing an electronic device

Abstract

The present description relates to a process for manufacturing an electronic device (34), involving manufacturing a plate (30) that comprises several copies of the electronic device (34), forming weakened areas (24) in a support (5) by means of a laser, attaching the plate (30) to the support (5) after forming the weakened areas (24), etching the plate in the extension of the weakened areas (24), and breaking the support (5) in the weakened areas (24) to separate the electronic devices (34).

Description

DESCRIPTION TITLE: METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE This patent application claims priority from French patent application FR22 / 14577, which will be considered as forming an integral part of this description. technical field

[0001] This description relates in general to the manufacturing processes of electronic devices, in particular optoelectronic devices including light-emitting diodes. Previous technique

[0002] An example of a manufacturing process for an electronic device involves forming a wafer containing multiple copies of the electronic device on a substrate, followed by separating the electronic devices. The separation of the electronic devices can be achieved by cutting the wafer and the substrate, particularly by sawing. A drawback of such a separation process is that the cut lines are wider than 100 µm. For some applications, it is desirable for the cut lines to be narrower, particularly to reduce material waste.

[0003] A method for separating electronic devices to obtain narrow cutting lines involves locally embrittling the substrate using laser treatment, which allows the substrate to break through mechanical action to separate the electronic devices. A drawback is that the laser treatment can damage the components of the electronic devices near the cutting lines. This drawback can be particularly pronounced when the electronic devices each comprise a plurality of elements. three-dimensional semiconductors of nanometer or micrometer size, separated by an electrically insulating material. Indeed, the size of the three-dimensional semiconductor elements and the distance separating the three-dimensional semiconductor elements being reduced, the thermal dissipation of the heat brought about by the laser treatment can lead to damage to the three-dimensional semiconductor elements near the cutting lines. Summary of the invention

[0004] One embodiment overcomes all or part of the drawbacks of known electronic device manufacturing processes.

[0005] An object of an embodiment is that the width of the cutting lines, in the plate comprising several copies of the electronic device, is less than 100 pm.

[0006] An object of an embodiment is that the components of electronic devices near the cutting lines are not damaged.

[0007] One embodiment provides a method for manufacturing an electronic device, comprising the fabrication of a board containing several copies of the electronic device, the board being fixed to a substrate, the formation of weakened areas in a substrate using a laser, the fixing of the board to the substrate after the formation of the weakened areas, the removal of the substrate after the board has been fixed to the substrate, the etching of the board extending from the weakened areas after the removal of the substrate, and the breaking of the substrate at the weakened areas to separate the electronic devices. The laser processing step of the substrate to form The weakened areas in the support are prepared before the step of fixing the support to the board containing the electronic devices; this advantageously prevents the laser treatment from damaging electronic components of the electronic devices on the board.

[0008] In one embodiment, the plate is fixed to the substrate by bonding. This can be achieved using a layer of adhesive, which advantageously allows for simple and cost-effective implementation. Alternatively, it can be achieved using molecular bonding, which advantageously eliminates the need for an adhesive layer between the substrate and the plate.

[0009] In one embodiment, the process includes, after fixing the plate to the support and before breaking the support at weakened areas, a step of thinning the support. This advantageously facilitates the breaking of the support at weakened areas.

[0010] In one embodiment, the engraving of the plate extending from the weakened areas is either dry or wet engraving. This advantageously allows for the creation of shallower trenches in the plate.

[0011] In one embodiment, the substrate is laser-transparent at least in the weakened areas. This advantageously allows for the creation of localized weakened areas.

[0012] According to one embodiment, the step of fixing the plate to the support after the formation of the weakened areas includes a step of positioning first marks on the support relative to second marks on the plate, so that each electronic device is separated is positioned between two weakened areas among the weakened areas.

[0013] In one embodiment, the substrate is at least partly made of glass, quartz, or sapphire. This advantageously allows the use of substrates commonly used in laser treatments.

[0014] In one embodiment, the electronic device comprises light-emitting diodes (LEDs). Advantageously, the formation of weakened areas does not lead to deterioration of the LEDs adjacent to the desired cutting lines. In one embodiment, each LED comprises a three-dimensional semiconductor element of nanometer or micrometer size, corresponding to a microwire, a nanowire, or a pyramidal structure of nanometer or micrometer size, and an active layer covering the three-dimensional semiconductor element. Brief description of the drawings

[0015] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which:

[0016] Figure IA, Figure IB, Figure IC, Figure 1D, Figure 1E, Figure 1F, and Figure IG are each a partial and schematic cross-sectional view of the structure obtained at a stage of an embodiment of a manufacturing process for an electronic device;

[0017] Figure 2 is a partial and schematic cross-sectional view of one embodiment of a support;

[0018] Figure 3A, Figure 3B, Figure 3C, Figure 3D, figure 3E, figure 3F, figure 3G, figure 3H, Figure 31, Figure 3J, Figure 3K, Figure 3L, Figure 3M, and Figure 3N are each a partial, schematic cross-sectional view of the structure obtained at one stage of an embodiment of a manufacturing process for an optoelectronic device comprising light-emitting diodes; and

[0019] Figure 4, Figure 5, and Figure 6 are each a partial, schematic cross-sectional view of an embodiment of a light-emitting diode. Description of the implementation methods

[0020] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0021] For the sake of clarity, only the steps and elements useful for understanding the implementation methods described have been represented and are detailed.

[0022] In the description that follows, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, reference is made to the orientation of the figures or to a probe in a normal operating position.

[0023] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to the nearest 10%, preferably to the nearest 5%. In the case of angles, the expressions "approximately", "roughly", "Approximately" and "on the order of" mean to the nearest 10°, preferably to the nearest 5°. Furthermore, here the terms "insulator" and "conductor" are taken to mean "electrically insulating" and "electrically conductive," respectively.

[0024] Optoelectronic devices are devices adapted to perform the conversion of an electrical signal into electromagnetic radiation or vice versa, and in particular devices dedicated to the detection, measurement or emission of electromagnetic radiation.

[0025] The transmittance of a layer is the ratio of the intensity of radiation exiting the layer through an exit face to the intensity of radiation entering the layer through an entrance face opposite the exit face. In the following description, a layer or film is said to be opaque to radiation when the transmittance of the radiation through the layer or film is less than 10%. In the following description, a layer or film is said to be transparent to radiation when the transmittance of the radiation through the layer or film is greater than 10%.

[0026] According to the present invention, the laser treatment step of the substrate to create weakened areas within the substrate is performed before the step of attaching the board containing several copies of the electronic device to the substrate. This advantageously prevents the laser treatment from damaging the electronic components of the electronic devices on the board.

[0027] Figure IA, Figure IB, Figure IC, Figure 1D, Figure 1E, Figure 1F, and Figure IG are each a partial, schematic cross-sectional view of the structure obtained at one stage of an embodiment of a manufacturing process for an electronic device.

[0028] Figure IA is a partial, schematic cross-sectional view illustrating a local embrittlement step of a support 5 by a laser treatment system 10.

[0029] The processing system 10 comprises a laser source 12 and a focusing optical device 14 having an optical axis D. The source 12 is adapted to provide an incident laser beam 16 to the focusing optical device 14, which provides a converging laser beam 18. The focusing optical device 14 may comprise one, two, or more optical components, with one optical component corresponding, for example, to a lens. Preferably, the incident laser beam 16 is substantially collimated along the optical axis D of the focusing optical device 14.

[0030] The support 5 comprises two opposing faces 20 and 22, with the laser beam 18 entering the support 5 through face 20. In one embodiment, faces 20 and 22 are parallel. In another embodiment, faces 20 and 22 are flat. In one embodiment, the thickness of the support 5 is between 50 µm and 3 mm. In one embodiment, the support 5 has a single-layer structure and is composed of a single first material, for example, glass, quartz, silicon, or sapphire. The support 5 is then laser-transparent. In another embodiment, the support 5 has a multi-layer structure, the top layer of which is made of the first material. At least the top layer is then laser-transparent.

[0031] The laser treatment consists of weakening areas 24 of the support 5, according to a laser stealth cutting process, notably using a low-energy laser; as an example, three weakened areas 24 are represented by dashed lines in Figure IA. According to one embodiment, the weakened areas 24 extend into the support 5 from face 20 of the support 5, over a thickness of between 5 µm and 100 µm. According to one embodiment, each weakened zone 24 has a width of between 0.5 µm and 5 µm. Each weakened zone 24 corresponds to a local melting of the support 5 without material shrinkage.

[0032] In one embodiment, the wavelength of the laser beam 18 provided by the processing system 10 is between 100 nm and 3000 nm, depending on the material to be embrittled. In another embodiment, the laser beam 18 is emitted by the processing system 10 in the form of a single pulse, two pulses, or more than two pulses, each pulse having a duration between 0.1 ps and 1000 ps. The energy of the laser beam for each pulse is between 1 pJ and 100 pJ.

[0033] Figure IB is a partial, schematic cross-sectional view of the structure obtained after the fabrication of a wafer 30 on a substrate 32. The wafer 30 comprises several copies of an electronic device 34, two copies of the electronic device 34 being shown as examples in Figure IB. The wafer 30 has an upper face 36 and a lower face 38, opposite the upper face 36. The lower face 38 is in contact with the substrate 32. The upper face 38 is preferably flat. In one embodiment, the thickness of the wafer 30 is between 1 µm and 100 µm. The electronic device 34 comprises electronic components 40, 42, 44, three electronic components 40, 42, 44 being shown as examples for each electronic device 34 in Figure IB. In one embodiment, the electronic device 34 is an optoelectronic device.Electronic components 40, 42, 44 may then include light sources, in particular light-emitting diodes.

[0034] Figure IC is a partial, schematic cross-sectional view of the structure obtained after the structure shown in Figure IB is attached to face 20 of the support 5 shown in Figure IA. The plate 30 is attached to the support 5 on the side of face 36. In one embodiment, the plate 30 is attached to the support 5 by bonding with a layer of adhesive 50. In another embodiment, not shown, the plate 30 is attached to the support 5 by molecular bonding. Face 36 of the plate 30 is then in direct physical contact with face 20 of the support 5.

[0035] The weakened areas 24 are located along the extensions of the desired separation lines between the electronic devices 34. The separation lines correspond to the parts of the plate 30 to be removed to achieve the separation of the electronic devices 34. The desired separation lines between the electronic devices and the weakened areas 24 are superimposed, with the desired separation lines covering the weakened areas 24. The correct positioning of the plate 30 relative to the support 5 is achieved by using, for example, marks on the plate 30 and marks on the support 5 (the marks are not shown).

[0036] Figure 1D is a partial, schematic cross-sectional view of the structure obtained after a substrate removal step 32, for example by dry etching, particularly plasma etching, or by wet etching, or by chemical-mechanical polishing, also known as CMP. Further steps can then be planned to continue the fabrication of the electronic devices 34 of the wafer 30, in particular the formation of conductive pads.

[0037] Figure IE is a partial, schematic cross-sectional view of the structure obtained after etching trenches 52 into the plate 30 at the desired separation lines of the electronic devices 34. The etching is, for example, by dry etching, in particular plasma etching. The trenches 52 may extend into the adhesive layer 50 until they reach the face 20 of the substrate 5 at the weakened areas 24. In one embodiment, the trenches 52 do not extend into the substrate 5. The trenches 52 may be obtained by chemical etching. In one embodiment, the width of each trench 52 is between 1 µm and 20 µm.

[0038] Figure 1F is a partial, schematic cross-sectional view of the structure obtained after a thinning step of the support 5 from face 22. Depending on the nature of the material or materials composing the support 5, the thinning step can be carried out by grinding and / or CMP. The CMP step may include, simultaneously or successively, mechanical polishing and chemical etching steps. At the end of the thinning step, the thickness of the support 5 is between 50 µm and 200 µm. In one embodiment, the thickness of the plate 10 is less, in particular by a factor of at least 2, than the thickness of the support 5 after thinning.

[0039] Figure IG is a partial, schematic cross-sectional view of the structure obtained after a mechanical rupture step of the support 5 at the weakened areas 24. Separate electronic devices 34 are thus obtained. According to an embodiment not shown, the rupture step comprises attaching a mechanically stretchable adhesive film to the support 5, on the side of the support 5 opposite the electronic devices 34, extending the adhesive film in the plane of the adhesive film, and the electronic devices 34 being then separated but still attached to the adhesive film, and the detachment of the electronic devices from the adhesive film.

[0040] The process may include subsequent steps, notably a step of removing portions of the support 5 and the layer of adhesive 50 present under each electronic device 34. In the case where the support 5 is retained for future use of the electronic device 34, the support 5 may advantageously be transparent to the light emitted by the electronic device 34.

[0041] The manufacturing process implementation advantageously ensures that the laser treatment of the support 5 to form the weakened areas 24 does not damage the electronic components 40, 42, 44 of the plate 30 since the laser treatment of the support 5 is carried out before the plate 30 is fixed to the support 5.

[0042] Figure 2 is a cross-sectional view of an embodiment of the support 5. In one embodiment, the support 5 has a multilayer structure and comprises a layer 56 of the first material covering a substrate 58 made of a second material different from the first. The weakened zones 24 are formed in the layer 56. The substrate 58 may be laser-transparent. In one embodiment, the second material is a semiconductor material. The semiconductor material may be silicon, germanium, or a mixture of at least two of these compounds. Preferably, the substrate 58 is made of silicon, more preferably monocrystalline silicon. Alternatively, the substrate 58 may be, at least in part, made of a non-semiconductor material, for example, an electrically insulating material or an electrically conductive material.The thickness of layer 56 is between 50 pm and 200 pm. Advantageously, the second material composing the substrate 58 is chosen to facilitate the thinning step. described previously in relation to Figure 1F. In particular, determining the end of the thinning step is facilitated since it corresponds to the complete removal of the substrate 58.

[0043] A more detailed embodiment will now be described in the case where the electronic device 34 is an optoelectronic device and the electronic components 40, 42, 44 comprise light-emitting diodes (LEDs) with three-dimensional semiconductor elements of nanometer or micrometer size, in particular microwires or nanowires, or pyramidal structures coated with active layers. Indeed, for such optoelectronic devices 34, separating the electronic devices 34 by creating weakened areas in a substrate through laser treatment while the plate containing the electronic devices 34 is fixed to the substrate results in significant damage to the LEDs near the desired cutting lines.

[0044] The term "microwire" or "nanofil" refers to a three-dimensional structure elongated along a preferred direction, at least two dimensions of which, called minor dimensions, are between 5 nm and 5 pm, preferably between 100 nm and 2 pm, more preferably between 200 nm and 1.5 pm, the third dimension, called major dimension or height, being greater than or equal to 1, preferably greater than or equal to 3, and even more preferably greater than or equal to 5 times, the largest of the minor dimensions. In some embodiments, the height of each microwire or nanowire may be greater than or equal to 500 nm, preferably between 1 pm and 50 pm. In the remainder of this description, the term "wire" is used to mean "microwire or nanowire".

[0045] The cross-section of wires can have various shapes, for example, oval, circular, or polygonal, including triangular, rectangular, square, or hexagonal. It should be understood that the term "average diameter" used in relation to a cross-section of a wire refers to a quantity associated with the area of ​​the wire in that cross-section, corresponding, for example, to the diameter of the disk having the same area as the cross-section of the wire.

[0046] In the following description, the term pyramid refers to a three-dimensional structure, part of which is pyramidal or elongated conical in shape. This pyramidal structure may be truncated, meaning that the apex of the cone is omitted, leaving a flat surface. The base of the pyramid is inscribed within a square with side lengths ranging from 100 nm to 10 pm, preferably between 0.2 pm and 2 pm. The polygon forming the base of the pyramid may be a hexagon. The height of the pyramid, from its base to its apex or summit flat surface, varies from 100 nm to 20 pm, preferably between 200 nm and 2 pm.

[0047] In the following description, embodiments will be described for an optoelectronic device with light-emitting diodes (LEDs) comprising microwires or nanowires. However, it is clear that these embodiments can also be applied to an optoelectronic device with LEDs comprising pyramids of micrometer or nanometer size.

[0048] The wires comprise predominantly, preferably more than 60% by mass, and more preferably more than 80% by mass, at least one semiconductor material. The semiconductor material may be silicon, germanium, silicon carbide, a III-V compound, a II-VI compound, or a combination of at least two of these compounds.

[0049] Examples of group III elements include gallium (Ga)₂, indium (In), and aluminum (Al). Examples of III-N compounds are GaN, AIN, InN, InGaN, AlGaN, and AlInGaN. Other group V elements can also be used, for example, phosphorus and arsenic. Generally, the elements in the III-V compound can be combined in different mole fractions. Examples of group II elements include group IIA elements, notably beryllium (Be) and magnesium (Mg), and group IIB elements, notably zinc (Zn), cadmium (Cd), and mercury (Hg). Examples of group VI elements include group VIA elements, notably oxygen (O) and tellurium (Te). Examples of II-VI compounds are ZnO, ZnMgO, CdZnO, CdZnMgO, CdHgTe, CdTe, and HgTe. Generally, the elements in II-VI compounds can be combined in different mole fractions.The semiconductor material of the wires may include a dopant, for example silicon providing N-type doping of a III-N compound, or magnesium providing P-type doping of a III-N compound.

[0050] Figure 3A, Figure 3B, Figure 3C, Figure Figures 3D, 3E, 3F, 3G, 3H, 31, 3J, 3K, 3L, 3M, and 3N are each a partial and schematic cross-sectional view of the structure obtained at one stage of an embodiment of a manufacturing process for the optoelectronic device 34.

[0051] Figure 3A, Figure 3B, Figure 3C, Figure 3D, Figure 3E, and Figure 3F illustrate the fabrication of the plate 30 on the substrate 32 in the case where the plate 30 includes several copies of the optoelectronic device 34 with nanowires or microwires.

[0052] Figure 3A is a partial, schematic cross-sectional view of the structure obtained after the steps following: - formation, on a substrate 60 comprising opposite faces 62 and 64, face 62 being preferably flat at least at the level of the light-emitting diodes, of a germination layer 66 in a material promoting the growth of wires and disposed on face 62; - formation of a stack of two insulating layers 68 and 70 covering the germination layer 66 and comprising openings 72 exposing portions of the germination layer 66; and - growth, for each aperture 72, of a light-emitting diode LED in contact with the germination layer 66 through the aperture 72, six light-emitting diodes LED of a single optoelectronic device 34 being shown as an example in figure 3A, the light-emitting diodes LED being arranged in sets of light-emitting diodes LED.

[0053] Figure 3B is a partial, schematic cross-sectional view of the structure obtained after the following steps: - formation of an insulating layer 74 extending over the lateral sides of a lower portion of each LED and extending over the insulating layer 70 between the LEDs; - formation of a layer 76 forming an electrode covering each LED and extending further over the insulating layer 74 between the LEDs; - formation of a protective dielectric layer 78 extending over layer 76; and - formation of a planarization layer 80 extending over the layer 78 and having a free face 81 flat.

[0054] Figure 3C is a partial, schematic cross-sectional view of the structure obtained after the following steps: - fixing a handle 82 to the face 81; and - removal of substrate 60, and of germination layer 66, by any known means.

[0055] Figure 3D is a partial and schematic cross-sectional view of the structure obtained after the formation, on the insulating layer 68, of an interconnection structure 83 comprising a stack 84 of insulating layers and conductive tracks 86 of different levels of metallization, conductive tracks 86 of two levels of metallization being shown as an example in Figure 3D, and conductive vias 88 extending through the stack 84 of insulating layers, the insulating layer 68, and the insulating layer 74, and connecting the electrode layer 76 to the conductive tracks 86, the interconnection structure 83 having a free face 90 preferably planar.

[0056] Figure 3E is a partial, schematic cross-sectional view of the structure obtained after a step of fixing the substrate 32 to the face 90, for example by molecular bonding.

[0057] Figure 3F is a partial, schematic cross-sectional view of the structure obtained in the following steps: - removal of handle 82 by any known means; - etching of the insulating layer 80 at the level of certain LED light-emitting diode assemblies to expose these LED light-emitting diode assemblies, and between the LED light-emitting diode assemblies, the insulating layer 80 being retained for the other LED light-emitting diode assemblies; - formation of photoluminescent blocks 94, 96 covering the assemblies of exposed light-emitting diodes (LEDs), two photoluminescent blocks 94, 96 are shown as an example in figure 3F; - formation of reflective walls 98 between blocks 94, 96; - formation of an encapsulation layer 100 covering each block 94, 96, and the protective dielectric layer 78 between blocks 94, 96, the encapsulation layer 100 comprising the unetched parts of the insulating layer 80; and - formation, in the encapsulation layer 100, of at least one color filter 102, for example a single yellow filter, covering at least some of the photoluminescent blocks 94, 96, a single filter 102 covering the two photoluminescent blocks 94, 96 being represented as an example in figure 3F.

[0058] The structure resting on the substrate 32 forms the plate 30 described previously and the free face 36 of the encapsulation layer 100 corresponds to the face 36 described previously.

[0059] Figure 3G is a partial, schematic cross-sectional view illustrating the step described previously in relation to Figure IC, which involves bonding face 36 to support 5 with a layer of adhesive 50. In Figure 3G, support 5 is shown with two weakened areas 24 and includes an opaque layer 104 on the side opposite plate 30. The opaque layer 104 may be omitted. The opaque layer 104 renders the substrate 5 non-transparent, which can facilitate the detection and handling of the structure by machines.

[0060] Figure 3H is a partial, schematic cross-sectional view illustrating the step described above in relation to Figure 1D, including the removal of substrate 32.

[0061] Figure 31 is a partial, schematic cross-sectional view of the structure obtained after a step of forming openings 106 in the stack 84 of insulating layers to expose conductive tracks 86.

[0062] Figure 3J is a partial, schematic cross-sectional view of the structure obtained after a step of removing the opaque layer 104. As an alternative, the opaque layer 104 can be removed at a later stage of the manufacturing process, in particular after the steps described later in relation to Figure 3L.

[0063] Figure 3K is a partial, schematic cross-sectional view of the structure obtained after a step of forming conductive pads 108 in contact with the conductive tracks 86 exposed through the openings 106, a single conductive pad 108 being shown as an example in Figure 3K. Each conductive pad 108 can have a single-layer or multi-layer structure.

[0064] Figure 3L is a partial, schematic cross-sectional view illustrating the step described above in relation to Figure 1E, comprising the engraving of trenches 52 in the plate 30 at the desired separation lines of the electronic devices 34.

[0065] Figure 3M is a partial, schematic cross-sectional view illustrating the step described above in relation to Figure 1F, including the thinning of support 5.

[0066] Figure 3N is a partial, schematic cross-sectional view illustrating the step described above in relation to Figure IG, including the breaking of the support 5 at the level of the weakened areas 24 to separate the optoelectronic devices 34.

[0067] Figure 4 shows an embodiment of light-emitting diodes (LEDs). In one embodiment, each LED comprises a wire 110 in contact with the seed layer 66 through one of the openings 72 and a shell 112 comprising a stack of semiconductor layers covering the lateral walls and the top of the wire 110. Such a configuration is called radial. The assembly formed by each wire 110 and its associated shell 112 constitutes the LED. Figure 4 also shows a reflective layer 114, for example metallic, covering the electrode layer 76 between the wires 110 and in direct physical contact with the electrode layer 76.

[0068] The shell 112 may comprise a stack of several layers, including an active layer 116 and a bonding layer 118. The active layer 116 is the layer from which the majority, and preferably all, of the radiation emitted by the light-emitting diode (LED) is emitted. For example, the active layer 116 may include containment means, such as a single quantum well or multiple quantum wells. The bonding layer 118 may comprise a stack of semiconductor layers of the same III-V material as the wire 110 but with the opposite conductivity to that of the wire 110.

[0069] Figure 5 shows an embodiment of LEDs. The LED shown in Figure 5 comprises all the elements of the LED shown in Figure 4, except that the shell 112 is present only at the top of the wire 110. Such a configuration is called axial.

[0070] The formation of the light-emitting diodes (LEDs), i.e., the growth of the wires 110 in the openings 72, and the formation of the shells 112 covering the wires 110 can be achieved for example by metal-organic chemical vapor deposition (MOCVD) or any other suitable process.

[0071] Figure 6 illustrates an embodiment of light-emitting diodes (LEDs). The LED shown in Figure 6 has a two-dimensional structure, as it is fabricated by the formation of a stack of substantially planar semiconductor layers on the substrate 60, followed by the delimitation of the LED, for example, by etching trenches in the stack of semiconductor layers. The LED shown in Figure 6 comprises a semiconductor layer 120 doped with a first type of conductivity, covered by an active layer 122, which is itself covered by a semiconductor layer 124 doped with a second type of conductivity.

[0072] The substrate 60 may be a single-piece structure or a layer covering a support made of another material. The substrate 60 is preferably a semiconductor substrate, for example, a silicon, germanium, silicon carbide, III-V compound such as GaN or GaAs, or a ZnO substrate. Preferably, the substrate 60 is a single-crystal silicon substrate. The substrate 60 may be a multilayer silicon-on-insulator (SOI) structure.

[0073] The germination layer 66 is made of a material that promotes wire growth. For example, the material composing the germination layer 66 may be a nitride, a carbide, or a boride of a transition metal. column IV, V or VI of the periodic table of elements or a combination of these compounds

[0074] In another embodiment, the germination layer 66 may not be present. In another embodiment, the germination layer 66 may be replaced by germination pads, for example formed at the bottom of the openings 72.

[0075] Each insulating layer 68, 70, 74, 78, 80, and the encapsulation layer 100 can be made of a dielectric material, for example silicon dioxide (SiCt) or silicon nitride (Si x N y where x is approximately equal to 3 and y is approximately equal to 4 (for example, Si3N4), in silicon oxynitride (notably with the general formula SiO₂ x N y , for example Si2ON2), aluminum oxide (Al2O3), hafnium oxide (HfCy), titanium dioxide (TiCt) or diamond. Each insulating layer 68, 70, 74, 78, 80 can have a single-layer structure or correspond to a stack of two or more layers.

[0076] The electrode layer 76 is designed to allow the passage of electromagnetic radiation emitted by light-emitting diodes. The material forming the electrode layer 76 can be a transparent and conductive material such as indium tin oxide (ITO), aluminum- or gallium-doped zinc oxide, or graphene. The thickness of the electrode layer 76 can range from 0.01 µm to 10 µm.

[0077] According to one embodiment, each photoluminescent block 94, 96 is located opposite one of the light-emitting diodes or a set of light-emitting diodes. Each photoluminescent block 94, 96 comprises phosphors adapted, when excited by the light emitted by the associated LED, to emit light at a wavelength different from the wavelength of the light emitted by the associated LED light-emitting diode.

[0078] Various embodiments and variations have been described. A person skilled in the art will understand that some features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0079] Finally, the practical implementation of the described methods and variants is within the reach of the person in the trade, based on the functional indications given above.

Claims

CLAIMS 1. Method for manufacturing an electronic device (34), comprising: - manufacturing a plate (30) comprising several copies of the electronic device (34), the plate (30) being fixed to a substrate (32); - the formation of weakened zones (24) in a support (5) by means of a laser; - fixing the plate (30) on the support (5) after the formation of the weakened zones (24); - removing the substrate (32) after fixing the plate (30) on the support (5); - etching the plate in the extension of the weakened zones (24) after removal of the substrate (32); and - breaking the support (5) at the weakened areas (24) to separate the electronic devices (34).

2. Method according to claim 1, in which the fixing of the plate (30) to the support (5) is carried out by gluing.

3. Method according to claim 2, in which the fixing of the plate (30) to the support (5) is carried out by gluing with a layer of glue (50).

4. Method according to claim 2, in which the fixing of the plate (30) to the support (5) is carried out by molecular bonding.

5. Method according to any one of claims 1 to 4, comprising, after fixing the plate (30) on the support (5), and before the support (5) breaks at the weakened zones (24), a step of thinning the support (5).

6. A method according to any one of claims 1 to 5, wherein the etching of the plate (30) in the extension of the weakened areas (24) is a dry etching or a wet etching.

7. Method according to any one of claims 1 to 6, in which the step of fixing the plate (30) on the support (5) after the formation of the weakened zones (24) comprises a step of positioning first marks of the support (5) relative to second marks of the plate (30), so that each electronic device (34) to be separated is positioned between two weakened zones (24) among the weakened zones (24).

8. Method according to any one of claims 1 to 7, in which the support (5) is transparent to the laser at least at the level of weakened zones (24).

9. Method according to any one of claims 1 to 8, in which the support (5) is at least partly made of glass, quartz, or sapphire.

10. A method according to any one of claims 1 to 9, wherein the electronic device (34) comprises light-emitting diodes (LEDs).

11. The method of claim 10, wherein each light-emitting diode (LED) comprises a three-dimensional semiconductor element (110) of nanometric or micrometric size, corresponding to a microwire, a nanowire or a structure of nanometric or micrometric size of pyramidal shape, and an active layer (112) covering the three-dimensional semiconductor element (110).

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