Transmitting / receiving circuit and signal transmission system formed therewith

Abstract

The invention relates to a transmitting / receiving circuit comprising a receiver circuit (PHY-R) with a signal input (rx1, rx2) for a differential voltage signal and with a data output (Dout) for a data signal; a transmitter circuit (PHY-T) with an (electronic) current source having two electric poles (+, -), with a data input (Din) for a data signal and with a (LVDS) signal output (tx1, tx2) having connection poles (tx1, tx2) for a differential voltage signal; two (two-pole) resistance elements (R1, R2); and (for connecting a signal cable having a pair of signal conductors) a connection device with two connection poles (tr1, tr2). Each of the connection poles (tx1, tx2) is electrically connected to one of the connection poles (tr1, tr2) with one of the resistance elements connected therebetween. The transmitter circuit (PHY-T) has at least two operating modes (T-l, T-Il) such that the transmitter circuit (PHY-T) is configured to convert a data signal at the data input (Din) into a differential voltage signal at the signal output in a first operating mode (T-l → transmitting operation), and to electrically short-circuit the connection poles (tx1, tx2) or keep them short-circuited in a second operating mode (T-Il → terminating operation).

Description

[0001] Transmitting-receiving circuit and signal transmission system formed thereby

[0002] The invention relates to a transmitting / receiving circuit (transceiver) for (data) signal transmission, in particular ANSI / TIA / EIA-644-1995 (LVDS) compliant, and a signal transmission system formed thereby.

[0003] For the fast (point-to-point) transmission of digital (measurement and / or operating data) at bit rates of more than 500 kbit / s (kilobits per second), signal transmission systems that use differential voltage levels, in particular those that conform to the ANSI / TIA / EIA-644-1995 standard (LVDS - Low Voltage Differential Signaling), are used in (industrial) measurement and / or control systems, for example to serially transmit digital (useful) data, such as measurement and / or operating data, within an (independent) measuring device or measuring system formed by at least one sensor and an electrically connected converter electronics and / or from such a measuring system to an external data processing system.

[0004] Signal transmission systems of the type in question or data processing systems formed therewith are described, for example, in DE-A 102017200687, US-A 2002 / 0126542, US-A 2009 / 0203333, US-A 2015 / 0247747, US-A 2016 / 0290847, US-A 2018 / 0328774, US-A 2019 / 0107425 or the (unpublished) international patent application PCT / EP2022 / 084226.

[0005] As shown, among others, in US-A 2002 / 0126542, such a

[0006] A signal transmission system compliant with the ANSI / TIA / EIA-644-1995 standard or suitable for LVDS transmission comprises two or more transmit / receive circuits (transceivers), each formed by a transmitter circuit, sometimes also referred to as an LVDS driver, a receiver circuit, two or more terminating resistors and one or more (twisted pair) signal cables, wherein each of the transmitter circuits has a data input for a (digital) data signal to be transmitted, a two-pole (LVDS) signal output for a differential (LVDS) voltage signal and an electronic (DC) current source, and each of the receiver circuits has a two-pole (LVDS) signal input for a differential (LVDS) voltage signal, which has an input resistance (typically more than 1 MΩ), and a data output for a (digital) data signal. In the case of the signal to be transmitted or received by means of signal transmission systems of the type in question,The output data signal can, for example, be an ANSI / TIA / EIA-485 (UART - Universal Asynchronous Receiver Transmitter) compliant serial digital signal, i.e., a binary (1-bit) data signal, with which the actual (measurement and / or operational) data is transmitted as a serial bit stream with a fixed frame (corresponding to a specified number of transmitted bits), which typically consists of a start bit, (depending on the protocol) five to a maximum of nine (payload) data bits, an optional parity bit for detecting transmission errors, and one or two stop bits. Accordingly, data transmission can, for example, be asynchronous or byte-synchronous.

[0007] The transmitter circuit of each of the aforementioned transmitting / receiving circuits is designed to be electrically connected to the receiver circuit of another of the transmitting / receiving circuits by means of a pair of signal conductors (of the aforementioned signal cable), wherein the same signal conductors are additionally electrically connected together at a respective receiver circuit end via one of the aforementioned terminating resistors - typically having more than 20 Ω (ohms) and less than 1 kΩ (kiloohms), for example namely approximately 100 Ω - and wherein the signal output of the transmitter circuit and the signal input of the receiver circuit are electrically connected to one another by means of the pair of signal conductors; this in particularsuch that a current loop is formed involving the respective signal output, the pair of signal conductors, and a current divider formed by the terminating resistor (correspondingly matched to the characteristic impedance of the signal cable) and the respective signal input. For connecting the signal conductors or a signal cable formed thereby, the respective transmit / receive circuit can have a corresponding connection device, for example, formed by connection pads or connector strips arranged on a circuit board.

[0008] The transmitter circuit of signal transmission systems of the type in question serves in particular to convert a (digital) data signal at the data input into a differential (LVDS) voltage signal at the (LVDS) signal output, in particular one that conforms to ANSI / TIA / EIA-644-1995 (LVDS), in a transmission mode of the respective transmitter circuit or the transmit / receive circuit formed thereby, which can be selected or activated, if necessary, by means of a value-discrete selection signal at a control input of the transmitter circuit. In addition, the respective receiver circuit (connected to the transmitter circuit) serves to convert the (LVDS) voltage signal supplied to the (LVDS) signal input into a (digital) data signal at the data output by establishing a transmission channel in a receive mode (selected or activated simultaneously with the aforementioned transmit mode) of the receiver circuit or the transmit / receive circuit formed thereby.For this purpose, the transmitter circuit is designed to electrically switch or keep switched a positive (current source) pole (+) of the current source to one of two connection poles of the (LVDS) signal output, as a function of a signal state of the data signal (at the data input), and to complement this, a negative (current source) pole (-) of the current source to the other of the two connection poles of the (LVDS) signal output, or to swap electrical connections established between the first and second (current source) poles and a different one of the two connection poles of the (LVDS) signal output, as a function of a signal edge of the data signal (mediating between two signal states). As a result, the current source of the transmitter circuit supplies a (loop) current with a predeterminable current, typically between 3 mA (milliamperes) and 10 mA, which can also be switched on or off if necessary, during transmission.adjustable (signal) current strength and a predeterminable current direction in the aforementioned current loop, such that the (loop) current flows with an alternating current direction in the current loop, whereby the (loop) current has a first current direction when the input signal has a first signal state (HIGH 1) and that the (loop) current has a second current direction opposite to the first current direction when the input signal has a second signal state (LOW ^ 0) different from the first signal state. The (loop) current, which is accordingly modulated with the data signal, in turn causes a (signal) voltage to drop across the terminating resistor, which serves as an input voltage for the receiver circuit and is likewise modulated with the data signal, with a voltage level proportional to the (signal) current strength of the (loop) current and a polarity dependent on the current direction of the (loop) current.Furthermore, the receiver circuit is configured to convert the (signal) voltage at the signal input into a corresponding output voltage, namely a (signal) voltage at the signal output of the receiver circuit, such that the output voltage of the receiver circuit assumes or has a first voltage level different from zero at a (positive) input voltage with a voltage level exceeding a (positive non-zero) first switching voltage threshold value or lying above the same first switching voltage threshold value.

[0009] As shown, inter alia, in US-A 20020126542, signal transmission systems of the type in question can be operated (bidirectionally) in half-duplex (HDX) such that the at least two transmit / receive circuits of the respective signal transmission system are alternately operated in the transmit and receive modes in the manner described above for the purpose of establishing first and second transmission channels with opposite transmission directions. To ensure that at most one of the aforementioned first and second transmission channels is activated at a time, the transmitter circuit is typically further configured to be placed in an operating mode alternative to the transmit mode, in which the transmitter circuit does not process a data signal at the data input or delivers no (LVDS) voltage signal at the (LVDS) signal output.Alternatively or additionally, the receiver circuit is configured not to convert a differential (LVDS) voltage signal at the (LVDS) signal input into a data signal at the data output or not to output a data signal at the data output in an operating mode alternative to the receive mode.

[0010] The (signal) quality of the (signal) voltage drop across the respective terminating resistor that can be achieved by means of such signal transmission systems with a predetermined transmission rate for a given (transmission) length of the signal conductor is (co-)determined not only by the electrical properties, such as in particular a (wave) impedance or attenuation, of the signal conductor or the (signal) cable formed thereby, but also by the voltage level of the differential (LVDS) voltage signal at the (LVDS) signal input, and thus by a (DC) current strength of the (loop) current as well as its distribution within the aforementioned current divider.

[0011] On the other hand, the electrical power available for operating such a signal transmission system, i.e. the electrical (transmission) power that can actually be fed into the signal conductors by means of the respective transmission circuit, is notoriously limited or contingent to a considerable extent. This is especially true when used in a measuring device in industrial measurement and automation technology that regularly requires the aforementioned high transmission rates of not less than 500 kbits / s, and therefore low bit durations of not more than 2 ps (microseconds), for example a (two-wire) measuring device with at least temporarily low power consumption of less than 50 mW (milliwatts) or a measuring device according to US-A 2018 / 0328774, for example in such a way that the (loop) current can only be permanently set to currents of less than 10 mA, and possibly even to at least temporarily less than 5 mA.a corresponding (transmission) power of less than 10 mW, possibly even less than 5 mW at least temporarily, is available. Consequently, the (signal) transmission distance that can be bridged using a conventional signal transmission system of the type in question is generally limited to a few meters, but in particular less than 20 meters.

[0012] In particular, the terminating resistor of each of the transmitting / receiving circuits, which is essential for the transmission and conversion of the (LVDS) voltage signal, results in the (loop) current fed in by one of the transmitting circuits (during its transmitting operation) being divided between the aforementioned current divider and the other terminating resistor connected in parallel; this is done in particular in such a way that, depending on the level of an (ohmic) resistance of the signal conductors and the characteristic impedance (line characteristic impedance) of the signal cable formed thereby, regularly less than 70%, in particular approximately 50%, of the (loop) current is available for the input of the receiving circuit or can be converted into the (LVDS) voltage signal at the (LVDS) signal input.Based on the aforementioned prior art, one object of the invention is to improve signal transmission systems of the type in question in such a way that, despite an overall low available electrical power of in particular not more than 10 mW or a (transmission) power that can be temporarily reduced to less than 10 mW, digital (measurement and / or operating) data can be transmitted at a transmission rate of more than 500 kbit / s even over transmission distances of more than 20 m, in particular more than 30 m.

[0013] To achieve this object, the invention consists in a transmitting / receiving circuit (transceiver) for (data) signal transmission, in particular ANSI / TIA / EIA-644-1995 (LVDS) compliant, comprising:

[0014] • a receiver circuit with an (LVDS) signal input for a differential (LVDS) voltage signal, in particular ANSI / TIA / EIA-644-1995 (LVDS) compliant, and with a data output for a data signal, in particular ANSI / TIA / EIA-485 (UART) compliant and / or binary;

[0015] • a transmitter circuit with a, in particular controllable, electronic (direct) current source with a (positive) first electrical (current source) pole and with a (negative) second electrical (current source) pole, with a data input for a, in particular

[0016] ANSI / TIA / EIA-485 (UART) compliant and / or binary (UART) data signal and with a (LVDS) signal output having a first connection pin and a second connection pin for a differential (LVDS) voltage signal, in particular ANSI / TIA / EIA-644-1995 (LVDS) compliant;

[0017] • a first (two-pole) resistance element, in particular one having an ohmic resistance of more than 10 Q (Ohm);

[0018] • a second (two-pole) resistance element, in particular one having an ohmic resistance of more than 10 Q and / or identical in construction to the first resistance element;

[0019] • and (for connecting a signal cable having a pair of signal conductors) a connecting device with a first connecting pole and a second connecting pole; wherein the first connecting pole of the transmitter circuit is electrically connected, in particular permanently, to the first connecting pole of the connecting device with the interposition of the first resistance element, and the second connecting pole of the transmitter circuit is electrically connected, in particular permanently, to the second connecting pole of the connecting device with the interposition of the second resistance element;

[0020] • and wherein the transmitter circuit has at least two operating modes (Tl, T-Il), each of which can be selected or activated by means of at least one discrete-value selection signal at a control input of the transmitter circuit, such that the transmitter circuit is set up, in a first operating mode (Tl -> transmit mode), to convert a (UART) data signal, in particular ANSI / TIA / EIA-485 (UART) compliant and / or binary, in particular a 1-bit data signal, at the data input into a differential (LVDS) voltage signal, in particular ANSI / TIA / EIA-644-1995 (LVDS) compliant, at the (LVDS) signal output, namely, depending on a signal state of the data signal (at the data input), the first (current source) pole to one of the first and second connection poles of the (LVDS) signal output and, complementarily thereto, the second (Power source) pole (-) to the other of the first and second connection poles electrically or to keep it connected ordepending on a signal edge of the data signal (at the data input) (mediating between two signal states of the data signal) between the first and second (current source) poles and a different one of the first and second connection poles of the (LVDS) signal output, to exchange electrical connections which are respectively set up, and that the transmitter circuit is set up in a second.

[0021] Operating mode (T-Il termination mode) to electrically short-circuit or keep short-circuited the first and second connection poles of the (LVDS) signal output, in particular in such a way that the first and second resistance elements are electrically connected in series.

[0022] Furthermore, the invention consists in a signal transmission system formed by means of such a transmitting / receiving circuit, for example a (serial) signal transmission system for the bidirectional (point-to-point) transmission of digital (payload) data.

[0023] According to a first embodiment of the invention, it is further provided that the transmitter circuit is configured to electrically connect the current source and the first and second resistance elements in series or to keep them electrically connected in series in the first operating mode.

[0024] According to a second embodiment of the invention, it is further provided that when the transmitter circuit is operating in the first operating mode, each of the first and second resistance elements forms a series resistance of the transmitter circuit between the current source and the respective connection pole of the (LVDS) signal output, for example limiting a (nominal) short-circuit current.

[0025] According to a third embodiment of the invention, it is further provided that the transmitter circuit is configured to electrically separate or keep electrically separated the current source from at least one of the first and second connection poles of the (LVDS) signal output in the second operating mode.

[0026] According to a fourth embodiment of the invention, it is further provided that the transmitter circuit is configured to electrically separate or keep electrically separated the (LVDS) signal output from at least one of the first and second (current source) poles in the second operating mode.

[0027] According to a fifth embodiment of the invention, it is further provided that the transmitter circuit is configured to electrically connect the first and second resistance elements in series or to keep them electrically connected in series in the second operating mode.

[0028] According to a sixth embodiment of the invention, it is further provided that the receiver circuit has at least two operating modes, for example each selectable or activatable by means of a discrete-value selection signal at a control input of the receiver circuit, such that the receiver circuit is set up, in a first operating mode (receiving mode), to convert a, for example ANSI / TIA / EIA-644-1995 (LVDS) compliant, differential (LVDS) voltage signal at the (LVDS) signal input into a, for example ANSI / TIA / EIA-485 (UART) compliant and / or binary, (UART) data signal, for example a 1-bit data signal, at the data output (Dout), and that the receiver circuit is set up, in a second operating mode, to convert a, for example

[0029] Not to convert an ANSI / TIA / EIA-644-1995 (LVDS) compliant differential (LVDS) voltage signal at the (LVDS) signal input into a data signal at the data output or not to output a data signal at the data output.

[0030] According to a seventh embodiment of the invention, it is further provided that the (LVDS) signal input of the receiver circuit has a first connection terminal and a second connection terminal. According to an eighth embodiment of the invention, it is further provided that the transmitter circuit is designed as an integrated circuit, for example, as a component of an application-specific integrated circuit (ASIC).

[0031] According to a ninth embodiment of the invention, it is further provided that the receiver circuit is designed as an integrated circuit, for example as a component of an application-specific integrated circuit (ASIC).

[0032] According to a tenth embodiment of the invention, it is further provided that the transmitter circuit and the receiver circuit are components of one and the same, for example application-specific, integrated circuit.

[0033] According to an eleventh embodiment of the invention, it is further provided that the transmitter circuit has an (H-)bridge circuit formed by means of first, second, third and fourth (semiconductor) switches, of which bridge circuit a supply input is electrically connected to the power source and of which bridge circuit a bridge branch is electrically connected to the first and second connection poles, for example in such a way that a series circuit of the first and second switches and a series circuit of the third and fourth switches are electrically connected in parallel, and / or in such a way that the first and fourth switches are electrically connected to the first (power source) pole and the second and third switches are electrically connected to the second (power source) pole.In a further development of this embodiment, it is further provided that the transmitter circuit is set up, in the first operating mode, in the case of a data signal at the data input with a first signal state corresponding, for example, to a logical one, both to close the (mutually diagonal) first and third switches (of the bridge circuit) or to keep them closed and to open the (mutually diagonal) second and fourth switches (of the bridge circuit) or to keep them open, and that the transmitter circuit is set up, in the first operating mode, in the case of a data signal at the data input with a second signal state that differs from the first signal state and corresponds, for example, to a logical zero, both to open the first and third switches (of the bridge circuit) or to keep them open and to close or keep the second and fourth switches (of the bridge circuit) closed.In addition, the transmitter circuit is further configured, in the first operating mode, in the case of a data signal at the data input with a signal edge transitioning from the first signal state to the second signal state, to both open and keep open the first and third switches (of the bridge circuit) and to close or keep closed the second and fourth switches (of the bridge circuit), and the transmitter circuit is configured, in the first operating mode, in the case of a data signal at the data input with a signal edge transitioning from the second signal state to the first signal state, to both close and keep closed the first and third switches (of the bridge circuit) and to open or keep open the second and fourth switches (of the bridge circuit).

[0034] According to a twelfth embodiment of the invention, it is provided that the transmitter circuit has an (H-)bridge circuit formed by means of first, second, third and fourth (semiconductor) switches, of which bridge circuit a supply input is electrically connected to the power source and of which bridge circuit a bridge branch is electrically connected to the first and second connection poles, for example in such a way that a series connection of the first and second switches and a series connection of the third and fourth switches are electrically connected in parallel, and / or in such a way that the first and fourth switches are electrically connected to the first (power source) pole and the second and third switches are electrically connected to the second (power source) pole, and it is further provided that the transmitter circuit has a (hardware) control logic with first, second, third and fourth control outputs for controlling the first, second, third and fourthfourth (semiconductor) switch of the (H-)bridge circuit. Developing this embodiment further, the control logic is further configured, in the first operating mode of the transmitter circuit, when there is a data signal at the data input with a first signal state corresponding, for example, to a logic one, both to close the first and third switches or to keep them closed and to open or to keep them open the second and fourth switches. The control logic is further configured, in the first operating mode of the transmitter circuit, when there is a data signal at the data input with a second signal state that differs from the first signal state and, for example, corresponds to a logic zero. For this purpose, each of the first, second, third and fourth switches hasfourth (semiconductor) switch further comprises a control terminal, each of which is electrically connected to (exactly) one associated (first, second, third or fourth) control output of the control logic and vice versa, and / or the control logic comprises a first control input and a second control input, for example such that the first control input forms a control input of the transmitting / receiving circuit or is electrically coupled thereto and that the second control input forms the data input of the transmitter circuit or is electrically coupled thereto and / or such that the first and second operating modes of the transmitter circuit can each be selected or activated by means of at least one value-discrete (binary) selection signal at the control input of the transmitter circuit.According to a further development of the invention, the transmit / receive circuit further comprises: a third (two-pole) resistance element, for example, having an ohmic resistance of more than 100 Ω, and a fourth (two-pole) resistance element, for example, having an ohmic resistance of more than 100 Ω and / or being structurally identical to the third resistance element. According to an embodiment of this further development of the invention, the (LVDS) signal input of the receiver circuit further comprises a first connection pole and a second connection pole, and it is further provided that the third resistance element electrically connects the first connection pole of the receiver circuit to the first connection pole of the connection device, and the fourth resistance element electrically connects the second connection pole of the receiver circuit to the second connection pole of the connection device, in particular permanently.

[0035] According to a further development of the signal transmission system of the invention, this further comprises: a further transmitting / receiving circuit, for example of the same type or construction as the transmitting / receiving circuit PHY and / or configured for signal transmission in accordance with ANSI / TIA / EIA-644-1995, and a signal cable having at least one pair of signal conductors, in particular of similar type and / or identical electrical properties and / or twisted together.

[0036] According to a first embodiment of this further development of the signal transmission system, it is provided that the two transmitting / receiving circuits are electrically connected by means of the signal cable (STP) to form a current loop.

[0037] According to a second embodiment of this further development of the signal transmission system, it is provided that the signal cable has a (transmission) length of more than 20 m (meters), for example even more than 50 m.

[0038] According to a third embodiment of this further development of the signal transmission system, it is provided that the signal cable has a wave impedance (line characteristic resistance) of not less than 20 Q, in particular not more than 500 Q.

[0039] A basic idea of ​​the invention is to eliminate the current divider formed by the terminating resistor at the input of the receiver circuit in a transmit / receive circuit of the type in question during the transmit operation of the associated transmitter circuit (the transmit / receive circuit) or to simply set it up while the transmitter circuit is not operating in the transmit mode. This makes it possible for practically the entire (loop) current fed in by the same transmitter circuit to be transferred to the other transmit / receive circuit or its receiver circuit, thus enabling a correspondingly higher proportion of the (transmit) power invested by the transmit / receive circuit to be converted to form the (LVDS) voltage signal received by the receiver circuit. One advantage of the invention is, among other things,in that the resistance elements required for forming the terminating resistor in the transmit / receive circuit can alternatively also serve as (fault) current-limiting series resistors in the transmit mode of the transmitter circuit. A further advantage of the invention is that both the transmitter circuit and the receiver circuit can be implemented using conventional (commercially available) integrated circuits or as components of one and the same (application-specific) integrated circuit, whereby the transmit / receive circuit according to the invention can also be produced at low manufacturing costs or at manufacturing costs comparable to those of conventional transmit / receive circuits.

[0040] The invention and advantageous embodiments thereof are explained in more detail below with reference to exemplary embodiments illustrated in the figures of the drawing. Identical or similarly acting or functioning parts are provided with the same reference numerals in all figures; where clarity requires it or it otherwise seems expedient, previously mentioned reference numerals are omitted in subsequent figures. Further advantageous embodiments or developments, in particular combinations of partial aspects of the invention initially explained only individually, will become apparent from the figures of the drawing and / or from the claims themselves.

[0041] In detail:

[0042] Fig. 1 and 2 respectively show an embodiment of a transmitting / receiving circuit (t ransceiver) according to the invention;

[0043] Fig. 3 shows an embodiment of a signal transmission system according to the invention (formed by means of a transmitting / receiving circuit according to Fig. 1 or 2);

[0044] Fig. 4 and 5 respectively show embodiments of a transmitting / receiving circuit according to Fig. 1; and

[0045] Fig. 6 shows an embodiment of a transmitting / receiving circuit according to Fig. 2; Figs. 1 and 2 schematically show an embodiment of a transmitting / receiving circuit (transceiver) PHY according to the invention, for example an externally and / or battery-powered, for (data) signal transmission, in particular for the transmission of ANSI / TIA / EIA-644-1995 (LVDS) compliant (voltage) signals.

[0046] The transmit / receive circuit PHY according to the invention can serve, for example, as a component of a (serial) signal transmission system (2PHY) for the bidirectional (point-to-point) transmission of digital (payload) data, in particular with a bit rate of more than 500 kbit / s (kilobits per second) and / or over a distance of more than 20 m (meters), in an electronic data processing system, in particular of digital (measurement and / or operating) data in an (industrial) measurement and / or control system, and / or in an (industrial) measuring device. An exemplary embodiment of such a 2PHY signal transmission system is shown schematically in Fig. 3. The signal transmission system 2PHY comprises, in addition to the transmitting / receiving circuit PHY, a further transmitting / receiving circuit PHY', for example of the same type or construction as the transmitting / receiving circuit PHY and / or set up for ANSI / TIA / EIA-644-1995 compliant signal transmission, as well as at least one pair, in particulara signal cable STP having similar and / or identical electrical properties and / or twisted together, comprising signal conductors; this in particular in such a way that the two transmit / receive circuits (PHY, PHY') are electrically connected by means of the signal cable STP to form a current loop. The signal cable STP can advantageously be a symmetrical and / or shielded signal cable or a signal cable suitable for symmetrical signal transmission, for example a twisted pair cable. According to a further embodiment of the invention, the signal cable STP additionally has a (transmission) length of more than 20 m (meters), for example also more than 50 m, possibly even more than 100 m, and / or the signal cable has a characteristic impedance (line characteristic impedance) of not less than 20 Ω, in particular not more than 500 Ω. Alternatively, or in addition orAlso for the purpose of realizing the aforementioned wave impedance, each of the signal conductors of the STP signal cable can advantageously have a (length-)specific ohmic resistance of less than 50 Ω / m (ohms per meter). According to a further embodiment of the invention, the STP signal cable is further configured to transmit an (LVDS) voltage signal, for example, one that is ANSI / TIA / EIA-644-1995 compliant and / or has symmetrical and / or differential voltage levels. The signal transmission system can, for example, be operated (bidirectionally) in a half-duplex (HDX) mode, such that the two transmit / receive circuits (PHY, PHY') are allowed to operate alternately in a transmit and receive mode to establish first and second transmission channels with opposite transmission directions.

[0047] The transmitting / receiving circuit PHY according to the invention, which is supplied, for example, by means of a (unipolar), in particular in a voltage range between 1.5 V (volts) and 3.5 V, direct voltage Un, comprises a receiver circuit PHY-R with a, in particular an input resistance of more than 1 MQ (megaohm),

[0048] (LVDS) signal input (rx1, rx2) for a differential (LVDS) voltage signal, in particular ANSI / TIA / EIA-644-1995 (LVDS) compliant, and with a data output Dout (forming a data output of the transmit / receive circuit) for a data signal, in particular ANSI / TIA / EIA-485 (UART) compliant and / or binary, as well as a transmitter circuit PHY-T with a, in particular controllable, electronic (DC) current source with a (positive) first electrical (current source) pole (+) and with a (negative) second electrical (current source) pole (-), with a data input Din (forming a data input of the transmit / receive circuit) for a, in particular ANSI / TIA / EIA-485 (UART) compliant and / or binary, (UART) data signal and with a (LVDS) signal output (tx1, tx2) having a first connection pin tx1 and a second connection pin tx2 for a differential (LVDS) voltage signal, in particular ANSI / TIA / EIA-644-1995 (LVDS) compliant.

[0049] According to a further embodiment of the invention, the (LVDS) signal input (rx1, rx2) of the receiver circuit PHY-R also has a first connection pin rx1 and a second connection pin rx2. The transmitter circuit PHY-T and / or the receiver circuit PHY-R can each advantageously be implemented as an integrated circuit, for example, as a component of an application-specific integrated circuit (ASIC), for example, such that the transmitter circuit PHY-T and the receiver circuit PHY-R are components of one and the same (application-specific) integrated circuit.

[0050] In addition to the transmitter and receiver circuits (PHY-T, PHY-R), the transmit / receive circuit PHY according to the invention further comprises a first (two-pole) resistance element R1, for example, having an ohmic resistance (value) of more than 10 Ω (ohms), a second (two-pole) resistance element R2, for example, having an ohmic resistance (value) of not less than 10 Ω and / or being identical in construction to the first resistance element R1, and (for connecting a signal cable having a pair of signal conductors) a (cable) connection device with a first connection pole tr1 and a second connection pole tr2. The connection device can be formed, for example, by means of a plug, pin or spring strip (arranged on a printed circuit board of the transmit / receive circuit), by means of solder pins and / or by means of (PCB) terminals. As shown in Fig. 1 or2, the connection pole tx1 of the transmitter circuit PHY-T is connected to the first connection pole tr1 of the connection device with the first resistance element interposed, and the connection pole tx2 of the transmitter circuit PHY-T is connected to the second.

[0051] Resistance element is electrically connected to the connection pole tr2 of the connection device, for example permanently. In order to limit a (maximum) fault current (of the receiver circuit), in particular to a (short-circuit) current value that complies with IEC 60079-11:2011, the transmitting / receiving circuit PHY, according to a further embodiment of the invention, further comprises a third (two-pole) resistance element R3, for example having an ohmic resistance of more than 100 Q, and a fourth (two-pole) resistance element R4, for example having an ohmic resistance of more than 100 Q and / or being identical in construction to the third resistance element, the third resistance element connecting the first connection pole rx1 of the receiver circuit PHY-R to the first connection pole tr1 of the connection device and the fourth resistance element connecting the second connection pole rx2 of the receiver circuit PHY-R to the second connection pole tr2 of the connection device, in particular.permanent, electrical connection.

[0052] The transmitter circuit PHY-T of the transmit / receive circuit PHY according to the invention further has at least two operating modes (Tl, T-Il), each of which can be selected or activated, for example, by means of at least one discrete-value selection signal at a (first) control input of the transmitter circuit PHY-T. In particular, the transmitter circuit PHY-T is configured, in a first operating mode Tl (transmit mode), to convert a (UART) data signal din, in particular an ANSI / TIA / EIA-485 (UART)-compliant and / or binary, for example a 1-bit data signal, at the data input Din into a (LVDS) voltage signal, in particular an ANSI / TIA / EIA-644-1995 (LVDS)-compliant and / or symmetrical, differential (LVDS) voltage signal at the (LVDS) signal output, namely, as also shown in Fig.1, depending on a signal state of the data signal (at the data input), to electrically switch the first (current source) pole (+) to one of the first and second connection poles of the (LVDS) signal output (tx1, tx2) and, complementarily thereto, to electrically switch the second (current source) pole (-) to the other of the first and second connection poles of the (LVDS) signal output (tx1, tx2) or to keep it switched through, or to swap electrical connections established between the first and second (current source) poles and a different one of the first and second connection poles of the (LVDS) signal output (tx1, tx2) depending on a signal edge of the data signal (at the data input) (mediating between two signal states of the data signal).In the aforementioned case that the transmit-receive circuit PHY is electrically connected to another transmit-receive circuit (PHY') via a signal cable (STP), a (loop) current iLVDS with a predeterminable current intensity, in particular one that is kept constant at least temporarily, can be driven or controlled in the current loop - here involving at least the current source, the two signal conductors of the signal cable STP and the transmit-receive circuit PHY'.be imprinted; this in particular in such a way that the aforementioned (loop) current iLVDS has a first current direction (+) for a data signal din having a first signal state (HIGH 1) and that the (loop) current iLVDS has a second current direction (-) opposite to the first current direction (+) for a (UART) data signal din having a second signal state (LOW 0) different from the first signal state (HIGH), whereby the (UART) data signal din is modulated onto the (loop) current iLVDS or the transmitter circuit PHY-T serves as an LVDS driver which converts the data signal din supplied via the signal input Din into a differential voltage level or voltage signal compliant with ANSI / TIA / EIA-644-1995. To limit the aforementioned (loop) current iLVDS or a (maximum) fault current (of the transmitter circuit), in particularto an IEC 60079-11:2011 compliant (short-circuit) current value, according to a further embodiment of the invention, the transmitter circuit PHY-T is further configured to electrically connect the current source and the first and second resistance elements (R1, R2) in series in the first operating mode or to keep them electrically connected in series and / or it is provided that when the transmitter circuit PHY-T is operating in the first operating mode, each of the first and second resistance elements forms a series resistance of the transmitter circuit PHY-T between the current source and the respective connection pole of the (LVDS) signal output (tx1, tx2), in particular a series resistance limiting a (nominal) short-circuit current.

[0053] The transmitter circuit PHY-T of the transmitting / receiving circuit PHY according to the invention is, as also schematically shown in Fig. 2, further configured to electrically short-circuit or keep short-circuited the first and second connection poles of the (LVDS) signal output (tx1, tx2) in a second operating mode T-II (termination mode), which can be activated or is activated, in particular, simultaneously with the aforementioned first operating mode R1 of the receiver circuit PHY-R; this in particular in such a way that the first and second resistance elements are electrically connected in series (for the purpose of forming a current divider involving the (LVDS) signal input).In the aforementioned case that the transmit / receive circuit PHY is electrically connected to another transmit / receive circuit (PHY') via a signal cable (STP), a terminating resistor (of the signal cable) is also formed, electrically connecting the signal conductors to a receiver circuit PHY-R at the (respective) line end. The terminating resistor formed by the first and second resistance elements serves here in particular to establish a voltage drop serving as an (LVDS) voltage signal (with a voltage level proportional to a current flowing therein and a polarity dependent on its current direction) at the input of the receiver circuit PHY-R. This voltage drop can then, for example, be generated by means of a resistor driven by the aforementioned transmit / receive circuit PHY' or its transmitter circuit, if necessary.also be generated in the same way as the aforementioned (by means of the transmitter circuit PHY-T) modulated (loop) current iLVDS. Advantageously, the resistances of the first and second resistance elements can also be selected such that their (resistance) sum matches the characteristic impedance of the aforementioned signal cable (STP) (to be connected to the transmit / receive circuit or the first and second connection poles of the connection device) or that the series-connected first and second resistance elements (R1, R2) form a correspondingly optimized terminating resistance of the signal cable. Not least in order to allow the smallest possible (partial) current to flow through the (LVDS) signal input (rx1, rx2) of the receiver circuit PHY-R during operation, compared to a (partial) current flowing through the aforementioned terminating resistor, this has, according to a further embodiment of the invention, a high input resistance of more than 1 MQ (megaohm).According to a further embodiment of the invention, the.

[0054] Transmitter circuit PHY-T is further configured, in the second operating mode, to electrically separate or keep electrically separate the current source from at least one, in particular each, of the first and second connection poles of the (LVDS) signal output (tx1, tx2) and / or to electrically separate or keep electrically separate the (LVDS) signal output from at least one of the first and second (current source) poles (+, -).

[0055] According to a further embodiment of the invention, the receiver circuit PHY-R also has at least two, for example each selectable or activatable by means of a value-discrete selection signal at a control input of the receiver circuit PHY-R,

[0056] Operating modes (Rl, R-Il). The receiver circuit PHY-R is particularly configured, in a first operating mode Rl (receive mode), to process a differential (LVDS) voltage signal, specifically one having differential voltage levels (uLVDS), particularly one that conforms to ANSI / TIA / EIA-644-1995 (LVDS) and / or is symmetrical, at the (LVDS) signal input (rx1, rx2), specifically to receive it and convert it into a (UART) data signal, specifically a 1-bit data signal, particularly one that conforms to ANSI / TIA / EIA-485 (UART) and / or is binary, at the data output Dout, or to operate as an LVDS receiver.For this purpose, the receiver circuit PHY-R is further configured, according to a further embodiment of the invention, to convert (in its first operating mode Rl) an input voltage uLVDS present at the (LVDS) signal input (rx1, rx2) into a corresponding output voltage at the signal output Dout, which serves as a data signal dout of the receiver circuit; this in particular in such a way that the output voltage assumes a (positive) first voltage level, in particular a (positive) first voltage level different from zero and / or not less than +500 mV, at a (positive) input voltage uLVDS (uLVDS +uLVDS) with a voltage level exceeding a (positive) first switching voltage threshold value (different from zero), for example not less than +5 mV (millivolts), or (continues to) have the first voltage level at a voltage level above the same switching voltage threshold value.Advantageously, the receiver circuit PHY-R can further be configured such that its pre-designated switching voltage threshold is not less than +5 mV, for example, even greater than +7 mV and / or less than +200 mV. Furthermore, the receiver circuit PHY-R is further configured (in its first operating mode Rl) to convert the input voltage uLVDS into the pre-designated output voltage (dout) such that the output voltage assumes a second voltage level deviating from the first voltage level of the output voltage, for example, zero or even different from zero (negative), when the input voltage uLVDS (uLVDS -uLVDS) has a voltage level below a second switching voltage threshold (which can be different from the pre-designated first switching voltage threshold or from zero), or has a second voltage level when the voltage level is below the second switching voltage threshold.The aforementioned second switching voltage threshold value can accordingly be below the aforementioned first switching voltage threshold value. Advantageously, the receiver circuit PHY-R can further be configured such that its second switching voltage threshold value is not more than -5 mV, for example, namely less than -7 mV and / or greater than -200 mV. In addition, the receiver circuit PHY-R can further be configured such that the first and second switching voltage threshold values ​​(representing different polarities of the input voltage uLVDS) have different signs from one another, for example, namely such that the first switching voltage threshold value has a positive sign (+) and the second switching voltage threshold value a negative sign (-), thus the first switching voltage threshold value is accordingly above zero and the second switching voltage threshold value is accordingly below zero, in particular.namely also such that the first and second switching voltage threshold values ​​have the same amount.

[0057] According to a further embodiment of the invention, the receiver circuit PHY-R is further configured, in a second operating mode, not to convert a differential (LVDS) voltage signal, for example an ANSI / TIA / EIA-644-1995 (LVDS) compliant voltage signal, at the (LVDS) signal input (rx1, rx2) into a data signal at the data output Dout or not to output a data signal at the data output Dout in the second operating mode.

[0058] For selecting its aforementioned first and second operating modes (Tl, T-Il), the transmitter circuit PHY-T can have a (first) control input DE for a discrete-value, for example, binary, (operating mode) selection signal. Furthermore, the receiver circuit PHY-R can also have a control input RE for a discrete-value, for example, binary, (operating mode) selection signal used for selecting its aforementioned first and second operating modes (Rl, R-Il).

[0059] In order to connect the first and second resistance elements R1, R2 in the manner described above, the transmitter circuit PHY-T, according to a further embodiment of the invention shown schematically in Fig. 4, 5 and 6, comprises an (H-)bridge circuit formed by means of a first (semiconductor) switch T1, a second (semiconductor) switch T2, a third (semiconductor) switch T3 and a fourth (semiconductor) switch T4. According to a further embodiment of the invention, each of the first, second, third and fourth (semiconductor) switches has at least one control terminal. As shown schematically in Fig. 4, 5 and 6, a supply input of the bridge circuit is electrically connected to the current source and a bridge branch of the bridge circuit is electrically connected to the first and second connection poles of the (LVDS) signal output (tx1, tx2); this in particularsuch that a series connection of the first and second switches and a series connection of the third and fourth switches are electrically connected in parallel, or that the first and fourth switches are electrically connected to the first (current source) pole (+) and the second and third switches are electrically connected to the second (current source) pole (-). In particular, the transmitter circuit (PHY-T) is further configured, in the first operating mode, with a data signal at the data input Din with a first signal state (HIGH), for example, corresponding to a logic one (..1..), as also schematically shown in Fig. 4, both to close or keep closed the (mutually diagonal) first and third switches T1, T3 and to open or keep open the (mutually diagonal) second and fourth switches T2, T4 and, as also schematically shown in Fig.5 schematically shows that, in the case of a data signal at the data input Din with a second signal state (LOW) which differs from the first signal state (HIGH), for example corresponding to logical zero, the first and third switches T1, T3 are to be opened or kept open, and the second and fourth switches (of the bridge circuit) are to be closed or kept closed, as well. Furthermore, the transmitter circuit PHY-T is set up, in the first operating mode, in the case of a data signal at the data input Din with a signal edge transitioning from the aforementioned first signal state (HIGH) to the second signal state (LOW), both to open or keep open the first and third switches T1, T3 and to close or keep closed the second and fourth switches T2, T4 accordingly, or in the case of a data signal at the data input Din with a signal edge transitioning from the second signal state (LOW) to the first.

[0060] According to a further embodiment of the invention, in order to control the bridge circuit, the PHY-T transmitter circuit further comprises a (hardware) control logic (LOGIC) with first, second, third and fourth control outputs for controlling the first, second, third and fourth (semiconductor) switches. The control logic is furthermore particularly designed, in the first operating mode of the PHY-T transmitter circuit, to close or keep closed the first and third switches and to open or keep open the second and fourth switches when a data signal having the aforementioned first signal state is present at the data input Din.Furthermore, the control logic is also designed to open or keep open the first and third switches and to close or keep closed the second and fourth switches when a data signal having the aforementioned second signal state is present at the data input Din. For this purpose, according to a further embodiment, each of the first, second, third and fourth control outputs (of the control logic) is electrically connected to (exactly) one associated control terminal of the first, second, third and fourth (semiconductor) switches and vice versa. Alternatively or additionally, the control logic further has a first control input and a second control input, wherein the first control input forms the aforementioned (first) control input DE of the transmit / receive circuit PHY and the second control input forms the data input Din of the transmitter circuit PHY-T or is electrically coupled thereto.

Claims

PATENT CLAIMS 1. Transceiver circuit for (data) signal transmission, in particular ANSI / TIA / EIA-644-1995 (LVDS) compliant, which includes the following: - a receiver circuit (PHY-R) - with an (LVDS) signal input (rx1, rx2) for a differential (LVDS) voltage signal, in particular ANSI / TIA / EIA-644-1995 (LVDS), with an input resistance of more than 1 MQ (MegaOhm) - and with a data output (Dout) for a data signal, in particular ANSI / TIA / EIA-485 (UART) compliant and / or binary; - a transmitter circuit (PHY-T) - with a, in particular controllable, electronic (direct) current source with a (positive) first electrical (current source) pole (+) and with a (negative) second electrical (current source) pole (-), - with a data input (Din) for a (UART) data signal, especially ANSI / TIA / EIA-485 (UART) compliant and / or binary - and with an (LVDS) signal output (tx1, tx2) having a first connection pole (tx1) and a second connection pole (tx2) for a differential (LVDS) voltage signal, in particular ANSI / TIA / EIA-644-1995 (LVDS) compliant; - a first (two-pole) resistance element, in particular one having an ohmic resistance of more than 10 Q (Ohm); - a second (two-pole) resistance element, in particular one having an ohmic resistance of more than 10 Ω and / or of the same construction as the first resistance element; - and (for connecting a signal cable having a pair of signal conductors) a connecting device with a first connecting pole (tr1) and with a second connecting pole (tr2); - wherein the first connection pole (tx1) of the transmitter circuit (PHY-T) is electrically connected, in particular permanently, to the first connection pole (tr1) of the connection device with the interposition of the first resistance element, and the second connection pole (tx2) of the transmitter circuit (PHY-T) is electrically connected, in particular permanently, to the second connection pole (tr2) of the connection device with the interposition of the second resistance element; - and wherein the transmitter circuit (PHY-T) has at least two operating modes (Tl, T-Il), in particular each selectable or activatable by means of at least one value-discrete selection signal at a control input of the transmitter circuit (PHY-T), such that - that the transmitter circuit (PHY-T) is arranged, in a first Operating mode (Tl -> transmit mode) to convert a, in particular ANSI / TIA / EIA-485 (UART) compliant and / or binary, (UART) data signal, in particular a 1-bit data signal, at the data input (Din) into a, in particular ANSI / TIA / EIA-644-1995 (LVDS) compliant, differential (LVDS) voltage signal at the (LVDS) signal output, namely, depending on a signal state of the data signal (at the data input), to electrically switch the first (current source) pole (+) to one of the first and second connection poles (tx1, tx2) of the (LVDS) signal output and, complementarily thereto, to electrically switch the second (current source) pole (-) to the other of the first and second connection poles (tx1, tx2) or to keep it switched on orto swap electrical connections established between the first and second (current source) poles and a different one of the first and second connection poles (tx1, tx2) of the (LVDS) signal output as a function of a signal edge of the data signal (at the data input) (mediating between two signal states of the data signal). - and that the transmitter circuit (PHY-T) is arranged to electrically short-circuit or keep short-circuited the first and second connection poles (tx1, tx2) of the (LVDS) signal output in a second operating mode (T-II termination mode), in particular in such a way that the first and second resistance elements are electrically connected in series.

2. Transceiver circuit according to one of the preceding claims, - wherein the transmitter circuit (PHY-T) is configured to electrically connect the current source and the first and second resistance elements in series or to keep them electrically connected in series in the first operating mode; and / or - wherein, when the transmitter circuit (PHY-T) is operating in the first operating mode, each of the first and second resistance elements forms a series resistance of the transmitter circuit (PHY-T) between the current source and the respective connection pole (tx1, tx2) of the (LVDS) signal output, in particular a series resistance limiting a (nominal) short-circuit current.

3. Transmitting / receiving circuit according to one of the preceding claims, - wherein the transmitter circuit (PHY-T) is configured to electrically isolate or keep electrically isolated the current source from at least one of the first and second terminal poles (tx1, tx2) of the (LVDS) signal output in the second operating mode; and / or - wherein the transmitter circuit (PHY-T) is configured to electrically separate or keep electrically separated the (LVDS) signal output from at least one of the first and second (current source) poles (+, -) in the second operating mode.

4. Transceiver circuit according to one of the preceding claims, wherein the transmitter circuit (PHY-T) is configured to electrically connect the first and second resistance elements in series or to keep them electrically connected in series in the second operating mode.

5. Transceiver circuit according to one of the preceding claims, - wherein the receiver circuit (PHY-R) has at least two operating modes (Rl, R-Il), in particular each selectable or activatable by means of a value-discrete selection signal at a control input of the receiver circuit (PHY-R), such that - that the receiver circuit (PHY-R) is arranged, in a first Operating mode (Rl -> receive mode), to convert a differential (LVDS) voltage signal at the (LVDS) signal input (rx1, rx2) conforming to ANSI / TIA / EIA-644-1995 (LVDS) into a binary (UART) data signal, in particular a 1-bit data signal, at the data output (Dout), - and that the receiver circuit (PHY-R) is configured, in a second operating mode, not to convert a differential (LVDS) voltage signal at the (LVDS) signal input (rx1, rx2), in particular one conforming to ANSI / TIA / EIA-644-1995 (LVDS), into a data signal at the data output (Dout) or not to output a data signal at the data output (Dout).

6. Transceiver circuit according to one of the preceding claims, wherein the (LVDS) signal input (rx1, rx2) of the receiver circuit (PHY-R) has a first connection pole (rx1) and a second connection pole (rx2).

7. Transceiver circuit according to one of the preceding claims, further comprising: - a third (two-pole) resistance element, in particular one with an ohmic resistance of more than 100 Ω; and - a fourth (two-pole) resistance element, in particular one having an ohmic resistance of more than 100 Q and / or identical in construction to the third resistance element.

8. Transmitting / receiving circuit according to claim 6 and 7, wherein the third resistance element electrically connects the first connection pole (rx1) of the receiver circuit (PHY-R) to the first connection pole (tr1) of the connection device and the fourth resistance element electrically connects the second connection pole (rx2) of the receiver circuit (PHY-R) to the second connection pole (tr2) of the connection device, in particular permanently.

9. Transmitting / receiving circuit according to one of the preceding claims, - wherein the transmitter circuit (PHY-T) is designed as an integrated circuit, in particular as a component of an application-specific integrated circuit (ASIC); and / or - wherein the receiver circuit (PHY-R) is designed as an integrated circuit, in particular as a component of an application-specific integrated circuit (ASIC); and / or - wherein the transmitter circuit (PHY-T) and the receiver circuit (PHY-R) are part of one and the same, in particular application-specific, integrated circuit.

10. Transmitting / receiving circuit according to one of the preceding claims, wherein the transmitter circuit (PHY-T) comprises a first, second, third and fourth (Semiconductor) switches (T1, T2, T3, T4) formed (H-)bridge circuit, of which bridge circuit a supply input is electrically connected to the current source and of which bridge circuit a bridge branch is electrically connected to the first and second connection poles (tx1, tx2), in particular in such a way that a series circuit of the first and second switches and a series circuit of the third and fourth switches are electrically connected in parallel, and / or in such a way that the first and fourth switches are electrically connected to the first (current source) pole (+) and the second and third switches are electrically connected to the second (current source) pole (-). 11 . Transceiver circuit according to claim 10, - wherein the transmitter circuit (PHY-T) is configured, in the first operating mode, to close or keep closed the first and third switches (of the bridge circuit) and to open or keep open the second and fourth switches (of the bridge circuit) in the case of a data signal at the data input (Din) with a first signal state corresponding, in particular, to a logical one; - and wherein the transmitter circuit (PHY-T) is configured, in the first operating mode, to open or keep open the first and third switches (of the bridge circuit) and to close or keep closed the second and fourth switches (of the bridge circuit) in the case of a data signal at the data input (Din) with a second signal state that differs from the first signal state (HIGH), in particular corresponding to logical zero.

12. Transmitting / receiving circuit according to the previous claim, - wherein the transmitter circuit (PHY-T) is configured, in the first operating mode, to open and keep open the first and third switches (of the bridge circuit) and to close and keep closed the second and fourth switches (of the bridge circuit) in the case of a data signal at the data input (Din) with a signal edge transitioning from the first signal state (HIGH) to the second signal state; - and wherein the transmitter circuit (PHY-T) is configured, in the first operating mode, to close or keep closed the first and third switches (of the bridge circuit) and to open or keep open the second and fourth switches (of the bridge circuit) in the case of a data signal at the data input (Din) with a signal edge transitioning from the second signal state (LOW) to the first signal state.

13. Transmitting / receiving circuit according to one of claims 10 to 12, wherein the Transmitter circuit (PHY-T) comprises a (hardware) control logic with first, second, third and fourth control outputs for controlling the first, second, third and fourth (semiconductor) switches of the (H-)bridge circuit.

14. Transmitting / receiving circuit according to the previous claim, - wherein the control logic is configured, in the first operating mode of the transmitter circuit (PHY-T), to close or keep closed the first and third switches and to open or keep open the second and fourth switches in the case of a data signal at the data input (Din) with a first signal state corresponding, in particular, to logic one; - and wherein the control logic is configured, in the first operating mode of the transmitter circuit (PHY-T), to open or keep open the first and third switches and to close or keep closed the second and fourth switches in the case of a data signal at the data input (Din) with a second signal state that differs from the first signal state, in particular corresponding to logical zero.

15. Transmitting / receiving circuit according to claim 13 or 14, - wherein each of the first, second, third and fourth (semiconductor) switches has a control terminal, and each of the first, second, third and fourth control outputs is electrically connected to (exactly) one associated control terminal of the first, second, third and fourth (semiconductor) switches, and vice versa; and / or - wherein the control logic has a first control input (DE) and a second control input, in particular such that the first control input (DE) forms a control input of the transmitting / receiving circuit or is electrically coupled thereto and / or that the second control input forms the data input (Din) of the transmitting circuit (PHY-T) or is electrically coupled thereto.

16. Transmitting / receiving circuit according to the preceding claim, wherein the first and second operating modes (Tl, T-Il) of the transmitter circuit (PHY-T) are each selectable or activatable by means of at least one value-discrete, in particular binary, selection signal at the control input of the transmitter circuit (PHY-T), in particular in such a way that the first operating mode is activated by means of a first signal state (de 1) and the second operating mode is selected or activated by means of a second signal state (de 0) different from the first signal state.

17. Signal transmission system, in particular (serial) signal transmission system for bidirectional (point-to-point) transmission of digital (payload) data, comprising: at least one transmit / receive circuit (PHY) according to one of the preceding claims.

18. Signal transmission system according to the preceding claim, further comprising: - another transmit / receive circuit (PHY'), in particular of the same type or construction as the transmit / receive circuit PHY and / or configured for signal transmission in accordance with ANSI / TIA / EIA-644-1995 - and a signal cable (STP) having at least one pair of signal conductors, in particular of similar and / or identical electrical properties and / or twisted together.

19. Signal transmission system according to the preceding claim, - wherein the two transmit-receive circuits (PHY, PHY') are electrically connected by means of the signal cable (STP) to form a current loop; and / or - the signal cable has a (transmission) length of more than 20 m (meters), in particular more than 50 m; and / or - the signal cable has a characteristic impedance of not less than 20 Ω, in particular not more than 500 Ω.

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