Transmission module and method for transmitting differential signals in a serial bus system

Abstract

The invention relates to a transmission module (121; 1210; 1211; 1212) and a method for transmitting differential signals in a serial bus system (1). The transmission module (121; 1210; 1211; 1212) has a first transmission stage (121A; 121A1) for generating transmission currents (I1 to In) for a first signal (CAN_H) that is to be transmitted to a bus (40) of the bus system (1), a second transmission stage (121B; 121B1) for generating transmission currents (I1 to In) for a second signal (CAN_L) that is to be transmitted, as a differential signal with respect to the first signal (CAN_H), to the bus (40), a third transmission stage (121C; 121C1) for generating transmission currents (I1 to In) for the first signal (CAN_H), a fourth transmission stage (121D; 121D1) for generating transmission currents (I1 to In) for the second signal (CAN_L), and a control circuit (15; 15A; 15B) for balancing a common mode voltage (VCM) for the first to fourth transmission stages (121A to 121D; 121A1 to 121D1), wherein the first to fourth transmission stages (121A to 121D; 121A1 to 121D1) are connected in a full bridge, in which the first and fourth transmission stages (121A, 121D; 121A1, 121D1) are connected in series and the third and second transmission stages (121C, 121B; 121C1, 121B1) are connected in series, wherein the control circuit (15; 15A; 15B) has a replica (152; 153; 153A) of an output stage of the transmission module (121; 1210; 1211; 1212), and wherein the replica (152; 153; 153A) is connected to the output stage of the transmission module (121; 1210; 1211; 1212).

Description

[0001] Description

[0002] Transmission module and method for transmitting differential signals in a serial

[0003] The present invention relates to a transmission module and a method for transmitting differential signals in a serial bus system, which can be used in particular for CAN XL while complying with the emission limits (EMC).

[0004] State of the art

[0005] Serial bus systems are used for message or data transmission in technical systems. For example, a serial bus system can enable communication between sensors and control units in a vehicle or a technical production system, etc.

[0006] In a CAN bus system, messages are transmitted using the CAN and / or CAN FD protocol, as described in the ISO 11898-1:2015 standard as a CAN protocol specification with CAN FD. With CAN FD, transmission on the bus switches back and forth between a slow operating mode in a first communication phase (arbitration phase) and a fast operating mode in a second communication phase (data phase). With a CAN FD bus system, a data transmission rate of greater than 1 Mbit per second (1 Mbps) is possible in the second communication phase. Most manufacturers initially use CAN FD with a 500 kbit / s arbitration bit rate and a 2 Mbps data bit rate in their vehicles.

[0007] To enable even higher data rates in the second communication phase, successor bus systems to CAN FD exist, such as CAN-SIC and CAN XL. With CAN-SIC, according to the CiA601-4 standard of the CAN in Automation (CiA) organization, a data rate of approximately 5 to 8 Mbit / s can be achieved in the second communication phase. CAN XL requires a data rate of > 10 Mbit / s in the second communication phase. A CiA610-3 standard is currently defined for CAN XL.

[0008] To transmit and receive bus signals, a CAN bus system typically uses transmit / receive devices for the individual communication participants. These devices are also referred to as CAN transceivers or CAN FD transceivers, etc. The transmit function of the CAN transceiver is implemented in a block called a transmitter. The transmitter translates a sequence of digital states (HI = high or LW = low) of a digital transmit signal into a differential bus signal between the CANH and CANL bus terminals.

[0009] In all of the CAN-based bus systems mentioned above, a CAN_H bus signal and, ideally, a CAN_L bus signal with a predetermined bus level or bus voltage V_CAN_H, V_CAN_L are driven onto a bus separately for a transmit signal TxD. At least in the first communication phase, one bus state is actively driven in the CAN_H, CAN_L bus signals. The other bus state is not driven and is determined by a terminating resistor for the bus lines or bus wires of the bus. The resulting voltage on the bus is the differential voltage VDIFF = CAN_H - CAN_L; more precisely, the differential voltage is equal to the voltage U of the CAN_H signal minus the voltage U of the CAN_L signal.

[0010] The differential voltage VDIFF varies depending on the state to be transmitted on the bus. For the dominant state, VDIFF_dom = 2 V. For the recessive state, VDIFF_rec = 0 V. For the Level0 state, VDIFF_L0 = 1 V. For the Levell state, VDIFF_L1 = -1 V. However, for all of the above states, the two bus levels or voltage amplitudes VCAN_H, VCAN_L of the CAN_H and CAN_L signals should remain centered around the value of a common-mode voltage VCM = VCAN_H + VCAN_L = 5 V. This is important because variations in this common-mode voltage VCM cause interference from the CAN transceiver. The value of 5 V corresponds to the value of the voltage Vcc, also called the CAN supply. To comply with the CAN specifications (ISO11898-2:2016, CIA601-4, CiA610-3) and the EMC standard (IEC62228-3), the common-mode voltage VCM should always remain at exactly the same voltage, regardless of the bus signal or the differential voltage VDIFF.This also applies during switching between the different bus states.

[0011] CAN transceivers or CAN FD transceivers must not exceed the limits for in-vehicle operation with regard to conducted radiation or emissions. Compared to CAN FD and CAN SIC, transceivers for CAN XL must comply with even stricter limits specified in the IEC 62228-3 standard. This is the only way to operate the bus system at the specified higher bit rates. Depending on the available semiconductor technology, compliance with these strict limits presents a significant challenge.

[0012] Disclosure of the invention

[0013] Therefore, it is an object of the present invention to provide a transmitter module and a method for transmitting differential signals in a serial bus system that solve the aforementioned problems. In particular, the transmitter module and the method for transmitting differential signals in a serial bus system should enable the compensation of interference variables that affect the emission behavior of the transmitter module.

[0014] The object is achieved by a transmission module for transmitting differential signals in a serial bus system having the features of claim 1.The transmission module has a first transmission stage for generating transmission currents for a first signal to be transmitted onto a bus of the bus system, a second transmission stage for generating transmission currents for a second signal to be transmitted onto the bus as a signal differential to the first signal, a third transmission stage for generating transmission currents for the first signal, a fourth transmission stage for generating transmission currents for the second signal, and a control circuit for adjusting a common-mode voltage for the first to fourth transmission stages, wherein the first to fourth transmission stages are connected in a full bridge in which the first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series, wherein the control circuit has a replica of an output stage of the transmission module, and wherein the replica is connected to the output stage of the transmission module.

[0015] The described transmitter module is designed to always maintain the common-mode voltage at exactly the same level, regardless of a bus signal VDIFF. This also applies during switching operations between the different bus states dorn, sic, and rec, or LO and L1.

[0016] In particular, the described transmitter module ensures that the common-mode voltage remains constant, even if the common-mode voltage is influenced by the temperature and process dependence of diodes and cascodes (component parameters and leakage currents) of the transmitter module. This also applies to a transmitter module in which a resistive bridge, also called a current-controlled H-bridge, has an additional dependence on the matching or mismatching of bias currents. Furthermore, this also applies to a transmitter module in which a resistive bridge, also called a resistive H-bridge, has an additional temperature and process dependence on the channel resistance of current-limiting transistors.

[0017] The described transmitter module thus enables the required emission limits for a CAN XL transmit / receive device to be met. In particular, the transmitter module complies with the IEC 62228-3 standard, which defines the specifications for CAN XL and the limits to be observed for the bus states dorn, sic, and rec on the bus, which are generated based on the transmit states dorn, sic, and rec of the transmitter module.

[0018] The transmitter module thus prevents emissions and thus allows operation in the bus system at higher bit rates. Advantageous further embodiments of the transmitter module are described in the dependent claims.

[0019] A common-mode point of the replica can be at the common-mode voltage of the output of the transmitting stages. According to one embodiment, the control circuit further comprises a differential amplifier with an input connected to the common-mode point of the replica, and a control transistor for controlling a common-mode voltage to a predetermined value, wherein the common-mode voltage is applied to the common-mode point of the replica.

[0020] It is conceivable that the replica comprises a series circuit consisting of a transistor, a diode, a transistor, a diode, a transistor, and a transistor in the order mentioned, wherein the sizes of the components of the series circuit are smaller by a predetermined factor than the sizes of the components of the output of the first and fourth transmission stages. In this case, the transistor and the transistor can each be configured as a cascode.

[0021] In the previously described transmitter module, output terminals of the full bridge can be provided for connection to a terminating resistor of the bus, wherein the replica in the series circuit has a bus load which is a replica of a terminating resistor of the bus.

[0022] According to one embodiment, the bus load has two resistors, both connected to the common mode point of the replica.

[0023] According to another embodiment, the replica has a switching unit for switching the bus load on or off.

[0024] Each transmitting stage can be designed to adjust the value of the electrical current output by the transmitting stage during operation of the transmitting module using a current mirror at the input of the transmitting stage.

[0025] The current mirror at the input of each transmission stage can have two CMOS transistors, wherein the CMOS transistors of the current mirror at the input of the first transmission stage are PMOS transistors, wherein the CMOS transistors of the current mirror at the input of the second transmission stage are NMOS transistors, wherein the CMOS transistors of the current mirror at the input of the third transmission stage are PMOS transistors, and wherein the CMOS transistors of the current mirror at the input of the fourth transmission stage are NMOS transistors.

[0026] Each transmitting stage can have at least two current stages connected in parallel. The at least two current stages can have at least one current sink. It is possible for the number n of the at least two current stages to be the same for each of the first to fourth transmitting stages, where n is a natural number greater than 1.

[0027] The transmitter module may also have a first resistor having one end connected to the first transmitter stage and the other end connected to the third transmitter stage, and a second resistor having one end connected to the second transmitter stage and the other end connected to the fourth transmitter stage.

[0028] The transmitter module may also include a control circuit for controlling switchable components of the first to fourth transmission stages depending on a digital transmission signal and an operating mode set for the transmitter module. The control circuit may be configured for the time-staggered and controlled switching of the resistance values ​​of the at least two current stages.

[0029] The previously described transmitting module can be part of a transmitting / receiving device for a subscriber station for a serial bus system, which also has a receiving module for receiving signals from the bus.

[0030] The transmitting / receiving device can be part of a subscriber station for a serial bus system, which also has a communication control device for controlling communication in the bus system and for generating a digital transmission signal for controlling the first to fourth transmission stages. The subscriber station may be configured for communication in a bus system in which exclusive, collision-free access of a subscriber station to the bus of the bus system is guaranteed, at least temporarily.

[0031] The aforementioned object is also achieved by a method for transmitting differential signals in a serial bus system having the features of claim 20. The method is carried out with a transmitting module having a first to fourth transmitting stage and a control circuit, wherein the method comprises the steps of generating, with the first transmitting stage, transmitting currents for a first signal to be transmitted onto a bus of the bus system, generating, with the second transmitting stage, transmitting currents for a second signal to be transmitted onto the bus as a signal differential to the first signal, generating, with the third transmitting stage, transmitting currents for the first signal, generating, with the fourth transmitting stage, transmitting currents for the second signal, and adjusting, with the control circuit, a common-mode voltage for the first to fourth transmitting stages, wherein the first to fourth transmitting stages are connected in a full bridge,in which the first and fourth transmitting stages are connected in series and the third and second transmitting stages are connected in series, wherein the control circuit comprises a replica of an output stage of the transmitting module, and wherein the replica is connected to the output stage of the transmitting module.,

[0032] The method offers the same advantages as previously mentioned with regard to the transmitter module.

[0033] Further possible implementations of the invention also include combinations of features or embodiments described above or below with respect to the exemplary embodiments that are not explicitly mentioned. In this case, the person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the invention.

[0034] Drawings The invention is described in more detail below with reference to the accompanying drawings and exemplary embodiments. They show:

[0035] Fig. 1 is a simplified block diagram of a bus system according to a first embodiment;

[0036] Fig. 2 is a diagram illustrating the structure of a message that can be sent by a subscriber station of the bus system according to the first embodiment;

[0037] Fig. 3 shows an example of the ideal time course of bus signals CAN_H, CAN_L in the bus system of Fig. 1;

[0038] Fig. 4 shows the time course of a differential voltage VDIFF which develops on the bus of the bus system as a result of the bus signals of Fig. 3;

[0039] Fig. 5 shows an example of a time course of a digital transmission signal which is to be converted into bus signals CAN_H, CAN_L for a bus of the bus system of Fig. 1 in the arbitration phase (SIC operating mode);

[0040] Fig. 6 shows the time course of the bus signals CAN_H, CAN_L when changing between a recessive bus state to a dominant bus state and back to the recessive bus state, which are sent to the bus in the arbitration phase (SIC operating mode) due to the transmission signal of Fig. 5;

[0041] Fig. 7 shows an example of a time course of a digital transmission signal which is to be converted in the data phase into bus signals CAN_H, CAN_L for the bus of the bus system of Fig. 1;

[0042] Fig. 8 shows the time course of the bus signals CAN_H, CAN_L, which are sent to the bus in the data phase based on the transmission signal of Fig. 7; Fig. 9 shows a circuit diagram of a transmission module for a subscriber station of the bus system according to the first embodiment;

[0043] Fig. 10 is a timing diagram illustrating the switching on of various current stages of a transmitting stage for a first specific example of the transmitting module of Fig. 9;

[0044] Fig. 11 shows a detail of a transmitting stage for a second specific example of the transmitting module of Fig. 9;

[0045] Fig. 12 is a circuit diagram of a transmitter module for a subscriber station of the bus system according to a second embodiment;

[0046] Fig. 13 is a circuit diagram of a transmitter module for a subscriber station of the bus system according to a third embodiment; and

[0047] Fig. 14 is a circuit diagram of a transmitter module for a subscriber station of the bus system according to a fourth embodiment.

[0048] In the figures, identical or functionally equivalent elements are provided with the same reference numerals unless otherwise indicated.

[0049] Description of the embodiments

[0050] Fig. 1 shows a bus system 1, which can, for example, at least in sections, be a CAN bus system, a CAN-FD bus system, etc. The bus system 1 can be used in a vehicle, in particular a motor vehicle, an aircraft, etc., or in a hospital, etc.

[0051] In Fig. 1, the bus system 1 has a plurality of subscriber stations 10, 20, 30, each connected to a bus 40 or bus line with a first bus wire 41 and a second bus wire 42. The bus wires 41, 42 can also be called CAN_H and CAN_L for the signals on the bus 40. Messages 45, 46, 47 can be transmitted in the form of signals between the individual subscriber stations 10, 20, 30 via the bus 40. The subscriber stations 10, 20, 30 can be, for example, control units or display devices of a motor vehicle.

[0052] As shown in Fig. 1, the subscriber stations 10, 30 each have a communication control device 11 and a transmitting / receiving device 12. The transmitting / receiving device 12 has a transmitting module 121 and a receiving module 122.

[0053] The subscriber station 20 has a communication control device 21 and a transmitting / receiving device 22. The transmitting / receiving device 22 has a transmitting module 221 and a receiving module 222.

[0054] The transmitting / receiving devices 12 of the subscriber stations 10, 30 and the transmitting / receiving device 22 of the subscriber station 20 are each directly connected to the bus 40, even if this is not shown in Fig. 1.

[0055] The communication control devices 11, 21 each serve to control communication of the respective subscriber station 10, 20, 30 via the bus 40 with at least one other subscriber station of the subscriber stations 10, 20, 30 that are connected to the bus 40.

[0056] The communication control devices 11 create and read first messages 45, 47, which are, for example, modified CAN messages 45, 47. The modified CAN messages 45, 47 are structured, for example, based on the CAN SIC format or the CAN XL format. The transmit / receive device 12 serves to transmit and receive the messages 45, 47 from the bus. The transmit module 121 receives a digital transmit signal TxD created by the communication control device 11 for one of the messages 45, 47 and converts this into signals on the bus 40. The receive module 121 receives signals transmitted on the bus 40 corresponding to the messages 45 to 47 and generates a digital receive signal RxD therefrom. The receive module 122 sends the receive signal RxD to the communication control device 11. The communication control device 21 can be designed like a conventional CAN controller according to ISO 11898-1:2015, iesuch as a CAN FD-tolerant Classical CAN controller or a CAN FD controller. The communication control device 21 creates and reads second messages 46, for example, CAN FD messages 46. The transceiver 22 is used to send and receive the messages 46 from the bus 40. The transmit module 221 receives a digital transmit signal TxD created by the communication control device 21 and converts it into signals for a message 46 on the bus 40. The receive module 221 receives signals transmitted on the bus 40 corresponding to the messages 45 to 47 and generates a digital receive signal RxD therefrom. Otherwise, the transceiver 22 can be designed like a conventional CAN transceiver.

[0057] To transmit messages 45 and 47 with CAN XL or CAN SIC, proven features are adopted that are responsible for the robustness and user-friendliness of CAN and CAN FD, in particular the frame structure with identifier and arbitration according to the well-known CSMA / CR method. The CSMA / CR method requires so-called recessive states on bus 40, which can be overwritten by other subscriber stations 10, 20, and 30 with dominant levels or dominant states on bus 40.

[0058] With the two subscriber stations 10, 30, the formation and then transmission of messages 45 with various CAN formats, in particular the CAN FD format or the CAN SIC format or the CAN XL format, as well as the reception of such messages 45, is possible, as described in more detail below.

[0059] Fig. 2 shows a frame 450 for message 45, which is in particular a CAN XL frame, as provided by communication control device 11 for transmitting / receiving device 12 to transmit on bus 40. In this embodiment, communication control device 11 creates frame 450 compatible with CAN FD. Alternatively, frame 450 is compatible with CAN SIC. According to Fig. 2, frame 450 for CAN communication on bus 40 is divided into different communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). The frame 450 has, after a start bit SOF, an arbitration field 453, a control field 454, a first switching field 455, a data field 456, a checksum field 457, a second switching field 458 and a frame termination field 459. The checksum field 457, the second switching field

[0060] 458 and the frame termination field 459 form a frame end phase 457, 458,

[0061] 459 of frame 450.

[0062] In the arbitration phase 451, using an identifier (ID) in the arbitration field 453, the subscriber stations 10, 20, 30 negotiate bit by bit to determine which subscriber station 10, 20, 30 wishes to send the message 45, 46 with the highest priority and will therefore receive exclusive access to the bus 40 of the bus system 1 for the next transmission time in the subsequent data phase 452. In the arbitration phase 451, a physical layer is used, similar to CAN and CAN-FD. The physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection Model).

[0063] An important point during phase 451 is the use of the well-known CSMA / CR method, which allows simultaneous access of the subscriber stations 10, 20, 30 to the bus 40 without destroying the higher-priority message 45, 46. This allows additional bus subscriber stations 10, 20, 30 to be added to the bus system 1 relatively easily, which is very advantageous.

[0064] The CSMA / CR method requires so-called recessive states on bus 40, which can be overwritten by other subscriber stations 10, 20, or 30 with dominant levels or dominant states on bus 40. In the recessive state, high-impedance conditions prevail at the individual subscriber stations 10, 20, or 30, which, in combination with the parasitics of the bus circuitry, results in longer time constants. This limits the maximum bit rate of today's CAN FD physical layer to approximately 2 megabits per second in real-world vehicle use.

[0065] At the end of the arbitration phase 451, the first switching field 455 is used to switch to the data phase 452.

[0066] In the data phase 452, in addition to a portion of the first switching field 455, the payload of the CAN-XL frame 450 or message 45 from the data field 456, as well as the checksum field 457 and a portion of the second switching field 458, are transmitted. At the end of the data phase 452, the system switches back to the arbitration phase 451 using the second switching field 458.

[0067] An end field of the frame termination field 459 may contain at least one acknowledge bit. Furthermore, a sequence of 11 identical bits may be present, indicating the end of the CAN XL frame 450. The at least one acknowledge bit can be used to indicate whether or not a receiver has detected an error in the received CAN XL frame 450 or message 45.

[0068] A sender of the message 45 begins sending bits of the data phase 452 to the bus 40 only when the subscriber station 10 as the sender has won the arbitration and the subscriber station 10 as the sender thus has exclusive access to the bus 40 of the bus system 1 for sending.

[0069] Thus, in the arbitration phase 451 as the first communication phase, the subscriber stations 10, 30 partially use, in particular up to the FDF bit (inclusive), a format known from CAN / CAN-FD according to ISO11898-1:2015. However, compared to CAN or CAN FD, in the data phase 452 as the second communication phase, an increase in the net data transmission rate, in particular to over 10 megabits per second, is possible. Furthermore, an increase in the size of the payload data per frame, in particular to approximately 2 kbytes or any other value, is possible. As shown in Fig. 3, the transmit / receive devices 12 use a physical layer 451_P in the arbitration phase 451 to transmit a transmit signal TxD (Fig. 1) over time t as signals CAN_H, CAN_L to the bus 40. The same applies to the transmit / receive device 22.In contrast, in the data phase 452, the transceiver 12 may use a physical layer 452_P that differs from the physical layer 451_P to transmit the transmit signal TxD (Fig. 1) as signals CAN_H, CAN_L onto the bus 40, as previously described. There are two operating modes for the physical layer 452_P, namely FAST_TX and FAST_RX, as described in more detail below.

[0070] Fig. 3 shows on the left that in the arbitration phase 451, the subscriber stations 10, 20, 30 each transmit signals CAN_H, CAN_L over time t to the bus 40, which have a first bit duration t_bt1. The signals CAN_H, CAN_L are serial signals and alternately have at least one dominant state 401, in which VCAN_H = 3.5 V and VCAN_L = 1.5 V, or at least one recessive state 402, in which VCAN_H = VCAN_L = 2.5. Dominant states 401 are driven during NRZ coding of the transmission signal TXD in phase 451 when TXD = 0 or L (LOW). Recessive states 402 are generated or occur during NRZ coding of the transmitted signal TXD in phase 451 when TXD = 1 or H (HIGH). After arbitration in arbitration phase 451, one of the subscriber stations 10, 20, or 30 is determined as the winner.

[0071] If the subscriber stations 10, 20, 30 detect the signaling in the first switching field 455 of Fig. 3 for switching from the first to the second communication phase 451, 452, the respective transmitting / receiving device 12 switches its physical layer 451_P at the end of the arbitration phase 451 from a first operating mode (SLOW), which can also be implemented as an SIC operating mode, to the physical layer 452_P of the data phase 452. For this purpose, the operating modes of the data phase 452 are activated.

[0072] If, for example, the first subscriber station 10 has won the arbitration, then the transmitting / receiving device 12 of the subscriber station 10 switches its physical layer 451_P at the end of the arbitration phase 451 from the first operating mode (SLOW) to the physical layer 452_P of the data phase 452 for a second operating mode (FAST_TX) of the transmitting / receiving device 12, in particular due to signaling in the first switching field 455 of Fig. 2, since the subscriber station 10 is the sender of the message 45 in the data phase 452. As shown in Fig. 3, the transmitting module 121 then generates the states L0 or L1 with the physical layer 452_P for the signals CAN_H, CAN_L on the bus 40 in the data phase 452 or in the second operating mode (FAST_TX) depending on a transmitting signal TxD one after the other and thus serially. In contrast, for example, the transmitting / receiving device 12 of the subscriber station 30 switches its physical layer 451_P at the end of the arbitration phase

[0073] 451 from the first operating mode (SLOW or SIC) into the physical layer 452_P of the data phase 452 for a third operating mode (FAST_RX) of the transmitting / receiving device 12, since the subscriber station 30 is only a receiver, i.e. not a transmitter, of the frame 450 in the data phase 452.

[0074] The frequency of the signals CAN_H, CAN_L can be increased in the data phase 452. In the example of Fig. 3, the bit time or bit duration t_bt2 in the data phase 452 is shorter or smaller than the bit time or bit duration t_bt1 in the arbitration phase 451. Thus, the net data transmission rate in the data phase is

[0075] 452 in the example of Fig. 3 compared to the arbitration phase 451.

[0076] If the transmitting / receiving device 12 detects, particularly with the signaling in the second switching field 458 of Fig. 2, that a switchover from the data phase 452 back to the arbitration phase 451 is to be performed, the transmitting / receiving device 12 is switched from transmitting (FAST_TX mode) and / or receiving (FAST_RX mode) signals with the physical layer 452_P to transmitting and / or receiving signals with the physical layer 451_P. Thus, after the end of the data phase 452, all transmitting / receiving devices 12 switch their operating mode to the first operating mode (SLOW or SIC). Thus, all transmitting / receiving devices 12 can not only switch between the bit durations t_bt1, t_bt2, but also switch their physical layer, as previously described.

[0077] According to Fig. 4, in the arbitration phase 451, in the ideal case, a differential signal VDIFF = CAN_H - CAN_L with values ​​of VDIFF = 2V for dominant states 401 and VDIFF = 0V for recessive states 402 is formed on bus 40 over time t. The curve of VDIFF in phase 451 is shown on the left side of Fig. 4. In contrast, in the data phase 452, a differential signal VDIFF = CAN_H - CAN_L corresponding to states L0, L1 of Fig. 4 is formed over time t on bus 40, as shown on the right side of Fig. 4. State L0 has a value VDIFF = 1 V. State L1 has a value VDIFF = -1 V.

[0078] The receiving module 122 can distinguish the states 401, 402 using two of the receiving thresholds T1, T2, T3, each of which lies in the ranges TH_T1, TH_T2, TH_T3. For this purpose, the receiving module 122 samples the signals from Fig. 3 or Fig. 4 at times t_A, as shown in Fig. 4. To evaluate the sampling result, the receiving module 122 uses the receiving threshold T1 of, for example, 0.7 V and the receiving threshold T2 of, for example, -0.35 V in the arbitration phase 451. In contrast, the receiving module 122 only uses signals evaluated with the receiving threshold T3 in the data phase 452. When switching between the first to third operating modes (SLOW or SIC, FAST_TX, FAST_RX) previously described with reference to Fig. 3, the receiving module 122 switches the receiving thresholds T2, T3, respectively.

[0079] The reception threshold T2 is used to detect whether the bus 40 is free when the subscriber station 12 is newly connected to the communication on the bus 40 and attempts to integrate itself into the communication on the bus 40.

[0080] Upon receiving the corresponding signals from the bus 40, each transceiver 12 generates the associated receive signal RxD, as shown in Fig. 1. The receive signal RxD ideally has no time offset from the transmit signal TxD.

[0081] Fig. 5 shows an example of a portion of the digital transmission signal TxD, which the transmission module 121 receives from the communication control device 11 in the arbitration phase 451, and from which it generates the signals CAN_H, CAN_L for the bus 40. In Fig. 5, the transmission signal TxD changes from a state LW (Low) to a state Hl (High) and back to the state LW (Low). As shown in more detail in Fig. 6, the transmission module 121 generates the signals CAN_H, CAN_L for the bus wires 41, 42 for the transmission signal TxD of Fig. 5 in such a way that a state 403 (sic) is additionally present. State 403 (sic) can have different lengths, as shown with state 403_0 (sic) during the transition from state 402 (rec) to state 401 (dorn) and with state 403_1 (sic) during the transition from state 401 (dorn) to state 402 (rec). State 403_0 (sic) is shorter in time than state 403_1 (sic). To generate signals according to Fig.6, the transmitter module 121 is switched to a SIC operating mode (SIC mode).

[0082] Transitioning through the short sic state 403_0 is not required by CiA610-3, and the state depends on the implementation type. The duration of the "long" state 403_1 (sic) is specified for CAN-SIC as well as for the SIC operating mode in CAN-XL as t_sic < 530 ns, starting with the rising edge of the transmit signal TxD in Fig. 5.

[0083] In the "long" state 403_1 (sic), the transmitter module 121 should match the impedance between the bus wires 41 (CANH) and 42 (CANL) as closely as possible to the characteristic impedance Zw of the bus line used. Here, Zw=1000 hm or 1200 hm. This matching prevents reflections and thus allows operation at higher bit rates. For simplicity, we will always refer to state 403 (sic) or sic-state 403 below.

[0084] The transmitter module 121 can be used to generate signals for the bus 40 for the following CAN types: CAN-FD, CAN-SIC and CAN-XL.

[0085]

[0086] Table 1: CAN types for transmitter module 121

[0087] Thus, the transmit module state sic can be generated not only with CAN-SIC or CAN-XL (xl_sic). The transmit module state sic can also be generated with CAN-FD. However, in CAN-FD, the time for the transmit module state sic can be shorter than with CAN-SIC or CAN-XL.

[0088] Fig. 7 shows an example of another part of the digital transmission signal TxD, which the transmission module 121 receives from the communication control device 11 in the data phase 452, and from which it generates the signals CAN_H, CAN_L for the bus 40. In Fig. 7, the transmission signal TxD changes several times from state Hl (High) to a state LW (Low) and back to a state Hl (High), and so on.

[0089] As shown in more detail in Fig. 8, the transmit module 121 generates the signals CAN_H and CAN_L for the transmit signal TxD of Fig. 7 for the bus wires 41, 42 in such a way that the state L0 is formed for a state LW (Low). In addition, the state L1 is formed for a state H1 (High).

[0090] Fig. 9 shows the basic structure of the transmitting module 121 for one of the subscriber stations 10, 30. The transmitting module 121 can generate signals CAN_H, CAN_L according to Fig. 3 with the states 401, 402, 403 and with the states L0, L1. Alternatively, the transmitting module 121 can generate signals CAN_H, CAN_L according to Fig. 6 with the states 401, 402, 403 and according to Fig. 8 with the states L0, L1. The transmitting module 121 has a control circuit 15 for adjusting a common-mode voltage VCM for the low-impedance recessive state sic.

[0091] The transmission module 121 has four transmission stages, namely a first transmission stage 121 A, a second transmission stage 121 B, a third transmission stage 121 C, and a fourth transmission stage 121 D. The transmission stages 121 A to 121 D are interconnected as an H-bridge or full bridge. The components of the transmission stages 121 A to 121 D, which are described in more detail below, are controlled via at least one control device 124. The at least one control device 124 sends at least one signal to control terminals 125, to which the components of the transmission stages 121 A to 121 D are connected.

[0092] The transmitter module 121 is connected to the bus 40, more precisely via a CANH connector for the first bus wire 41 for CAN_H and via a CANL connector for its second bus wire 42 for CAN_L. Each of the transmitter stages 121A to 121D is connected to the bus 40.

[0093] The voltage supply for supplying the CANH, CANL terminals for the first and second bus wires 41, 42 with electrical energy, in particular with the CAN supply voltage of typically 5 V, is provided via at least one terminal 43 of the transmitter module 121. The connection to ground or CAN_GND is realized via a terminal 44.

[0094] The first and second bus wires 41, 42 are terminated with a terminating resistor 49. The terminating resistor 49 is connected to the full bridge as an external load resistor. The resistor 49 is connected to the bridge branch between the terminals for the bus wires 41, 42.

[0095] The control circuit 15 is connected to the transmitting stages 121 A to 121 D. The control circuit 15 is not directly connected to the bus 40, but via the transmitting stages 121 A to 121 D.

[0096] The control circuit 15 of Fig. 9 performs a control for the low-impedance recessive state sic, with which a common-mode voltage VCM always remains exactly the same value on bus 40, regardless of the bus signal or the differential voltage VDIFF of, for example, Fig. 4. This reduces the interference emitted by the transmitter module 121, which would otherwise result from a variation in this common-mode voltage VCM. This enables compliance with the CAN specifications (ISO 11898-2:2016, CiA601-4, CiA610-3) and the EMC standard (IEC 62228-3).

[0097] For this purpose, the control circuit 15 has a differential amplifier 151, a replica 152 of the output stage of the transmitting stage 121, and a control transistor MNCTRL. According to Fig. 9, the replica 152 has a series circuit consisting of a transistor MPR, a diode MNDIOPR, a transistor MPCASPR, a diode MNDIONR, a transistor MPCASNR, and a transistor MNR. The replica 152 is a replica of the output stage of the transmitting stage 121, which has a transistor MPo, a diode MNDIOPH, a transistor MPCASPH, a diode MNDIONH, a transistor MPCASNH, and a transistor MNo. The aforementioned components of the output stage of the transmitting stage 121 are components for the transmitting stages 121A, 121D, which are described in more detail below.

[0098] According to Fig. 9, the differential amplifier 151 compares the common-mode voltage VCM with a desired common-mode voltage VREF. The common-mode voltage VCM is tapped at a common-mode point or tap point 157 of the replica 152. Thus, a reference voltage AV = VREF - VCM is present at the input of the differential amplifier 151. The required adjustment voltage for the currents ICTRL and IBIAS is derived from the reference voltage AV. In particular, VREF = 2.5 V = 5 V / 2 = CAN_SUPPLY / 2.

[0099] To keep power consumption in replica 152 of control circuit 15 low, all components in replica 152—i.e., transistor MPR, diode MNDIOPR, transistor MPCASPR, diode MNDIONR, transistor MPCASNR, and transistor MNR—should be or have scaled sizes of the components of the output stage of transmit stage 121. In particular, the sizes of the components in replica 152 are smaller by a factor of 100 than the sizes of the components of the output stage of transmit stage 121. Of course, a different factor can be selected. It is important that replica 152 consists of the same component types as those used in the output stage of transmit stage 121. Furthermore, replica 152 should match the output stage of transmit stage 121 both thermally and in terms of alignment.The term "alignment," which can also be referred to as orientation, is to be understood here as the spatial alignment in the layout on the chip in or with which the transmitting stage 121 is constructed. Influences such as temperature or a piezoelectric effect, which cause elastic deformation, may require that the control circuit 15 be in the same alignment as the output stage of the transmitting stage 121. In particular, the replica 152 and the output stage of the transmitting stage 121 have the same temperature and the same alignment or orientation. The control transistor MNCTRL can be selected to be identical in size and alignment or orientation to the transistor MNMIR, which results in the compensating current or bias current IBIAS. The transistor MNMIR can also be referred to as the parent transistor MNMIR of the bias current IBIAS.

[0100] In the circuit of Fig. 9, the common-mode point or tap point 157 of the replica 152 obtained with the control circuit 15 is thus at the common-mode voltage of the output of the transmitting stages 121A, 121D, i.e., the common-mode voltage VCM, and can be compared with the reference voltage VREF. For example, the common-mode voltage VCM of the output of the transmitting stages 121A, 121D is the common-mode voltage V cm = (VCAN_H+VCAN_L) / 2. The gate voltage of the control transistor MNCTRL, which can be selected to be identical to the parent transistor MNMIR of the bias current IBIAS in terms of size and orientation, then results in the controlled bias current ICTRL = IBIAS + g AV on the CANH side, where g is the gain of the differential amplifier 151.

[0101] The bandwidth of the control loop of the control circuit 15, in particular the bandwidth of the differential amplifier 151, is selected such that within the bit duration t_bt1 or t_bt2 shown in Fig. 3, an adjustment of the common-mode voltage VCM for the low-impedance recessive state sic takes place.

[0102] The replica 152 enables the determination of the (undisturbed) common-mode voltage VCM, which also maps the process and temperature dependencies of the outputs of the transmitter stage 121. With the control circuit 15 of Fig. 9, the common-mode voltage VCM is obtained for the current-controlled H-bridge of the transmitter stage 121 by matching the current ICTRL on the CANH side, which can also be referred to as the high side, and the current IBIAS on the CANL side, which can also be referred to as the low side. Especially in the low-impedance recessive state (SIC state), the precise matching of the currents ICTRL and IBIAS, taking into account the leakage currents due to temperature and process fluctuations, requires very fine and possibly even temperature-dependent tuning of the currents ICTRL and IBIAS. The tuning can be derived from a temperature sensor and stored tuning data.

[0103] This eliminates the need to determine the common-mode voltage VCM by tapping bus 40. However, such a tapping would have the disadvantage that the tapping would again have to meet the overvoltages and current requirements at the tapping point. Meeting these requirements is very difficult, however, because the actual common-mode voltage (V_CANH+V_CANL) / 2 can exhibit considerable amplitudes (up to + / - 60V) in the case of interference (DPI) on bus 40.

[0104] To transmit the signals CAN_H, CAN_L according to Fig. 3 or the signals CAN_H, CAN_L according to Fig. 6 or according to Fig. 8, the transmitting stages 121 A, 121 B, 121 C, 121 D are constructed as follows.

[0105] The first transmitting stage 121 A of Fig. 9 has n current step switches which can be switched between a first position 0 and a second position 1 and are connected to the drain terminal of transistors MPMIR, MPR, MPO, MPI, MP2 to MP nare connected, n is a natural number > 1. The n current step switches can be switched at a frequency fMAiN. The n current step switches can be connected in their position 1 to the anode of a polarity reversal diode MNDIOPH. A source terminal of a transistor MPCASPH is connected to the cathode of the polarity reversal diode MNDIOPH. The drain terminal of the transistor MPCASPH is connected to the terminal CANH for the bus wire 41. The gate terminal of the transistor MPCASPH is connected to a control terminal 125, to which the control device 124 can apply a control voltage VPCAS. The transistors M PMIR, M PR form a current mirror for a first to a-th current stage S1 to Sn, which supply electrical currents I1 to In via the n current step switches of the first transmission stage 121 A, as described in more detail with reference to Fig. 10. In addition, there is a control circuit T_A which controls the n current step switches using the transmission signal TxD (Fig.1) which is fed from a terminal TXD. The control circuit T_A controls the n current step switches according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121.

[0106] The transistors M PMIR, M PR, M PO, M PI , MP2 to MP n can be CMOS transistors, especially PMOS transistors. The transistors M PMIR, M PR, M PO, M PI , MP2 to MP nIn the example of Fig. 1, these are normally off p-channel transistors. The transistor M PCASPH can be a CMOS transistor, in particular a PMOS transistor. The transistor M PCASPH is in particular a cascode to meet the requirements for feedback immunity in the event of overvoltages or undervoltages at the CANH terminal. The abbreviation "CMOS" refers to a semiconductor element in which both p-channel and n-channel MOSFETs are used on a common substrate. The abbreviation CMOS stands for "complementary metal-oxide-semiconductor". The abbreviation "MOSFET" stands for metal-oxide field-effect transistor.

[0107] The second transmitting stage 121 B of Fig. 9 has n current step switches which can be switched between a first position 0 and a second position 1 and are connected to the drain terminal of transistors M NMIR, MNR, M NO, M NI , MN2 to MN nare connected, n is the natural number > 1. The n current step switches can be switched at a frequency fcoMPL. The n current step switches can be connected in their position 1 to the source terminal of a transistor M NCASNH. The drain terminal of the transistor M NCASNH is connected to the cathode of a polarity reversal diode M NDIONH. The terminal CANH for the bus wire 41 is connected to the anode of the polarity reversal diode M NDIONH. The gate terminal of the transistor M NCASNH is connected to a control terminal 125, to which the control device 124 can apply a control voltage VNCAS. The transistors M NMIR, MNR form a current mirror for a first to n-th current stage S1 to Sn, which supply the electrical currents I1 to In via the n current step switches of the second transmission stage 121B, as described in more detail with reference to Fig. 10. In addition, a control circuit T_B is provided, which controls the n current step switches using the transmission signal TxD (Fig.1) which is fed from a terminal TXD. The control circuit T_B controls the n current step switches according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121.

[0108] The transistors M NMIR, MNR, M NO, M NI , MN2 to MN n can be CMOS transistors, especially NMOS transistors. The transistors M NMIR, MNR, M NO, M NI , MN2 to MN n In the example of Fig. 1, these are normally off n-channel transistors. The transistor M NCASNH can be a CMOS transistor, in particular an NMOS transistor. The transistor M NCASNH is, in particular, a cascode to meet the requirements for feedback immunity in the event of overvoltages or undervoltages at the CANH terminal.

[0109] The third transmitting stage 121 C of Fig. 9 has n current step switches which can be switched between a first position 0 and a second position 1 and are connected to the drain terminal of the transistors M PMIR, M PR, M PO, M PI , MP2 to MP nare connected. The n current step switches can be switched at a frequency fcoMPL. In their position 1, the n current step switches can be connected to the anode of a polarity reversal diode M NDIOPL. A source terminal of a transistor M PCASPLH is connected to the cathode of the polarity reversal diode M NDIOPL. The drain terminal of the transistor M PCASPL is connected to the CANL terminal for the bus wire 42. The gate terminal of the transistor M PCASPL is connected to the control terminal 125, to which the control device 124 can apply the control voltage VPCAS. The transistors M PMIR, M PR form a current mirror for a first to n-th current stage S1 to Sn, which supply the electrical currents I1 to In via the n current step switches of the third transmission stage 121 C, as described in more detail with reference to Fig. 10. In addition, a control circuit T_C is provided, which controls the n current tap switches using the transmission signal TxD (Fig. 1), which is fed in from a terminal TXD.The control circuit T_C controls the n current step switches according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121.

[0110] The transistor M PCASPL can be a CMOS transistor, in particular a PMOS transistor. The transistor M PCASPL is, in particular, a cascode transistor to meet the requirements for feedback immunity in the event of overvoltages or undervoltages at the CANL terminal.

[0111] The fourth transmitting stage 121 D of Fig. 9 has n current step switches which can be switched between a first position 0 and a second position 1 and are connected to the drain terminal of the transistors M NMIR, MNR, M NO, M NI , MN2 to MN nare connected, n is the natural number > 1 . The n current step switches can be switched with a frequency fiwuN. The n current step switches can be connected in their position 1 to the source terminal of a transistor M NCASNL. The drain terminal of the transistor M NCASNL is connected to the cathode of a polarity reversal diode M NDIONL. The terminal CANL for the bus wire 42 is connected to the anode of the polarity reversal diode M NDIONL. The gate terminal of the transistor M NCASNL is connected to the control terminal 125, to which the control device 124 can apply the control voltage VNCAS. The transistors M NMIR, MNR form a current mirror for a first to n-th current stage S1 to Sn, which supply the electrical currents I1 to In via the n current step switches of the fourth transmitting stage 121 D, as described in more detail with reference to Fig. 10. In addition, a control circuit T_D is provided, which controls the n current step switches using the transmission signal TxD (Fig.1) which is fed from a terminal TXD. The control circuit T_B controls the n current step switches according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121.

[0112] The transistor M NCASNL can be a CMOS transistor, in particular an NMOS transistor. The transistor M NCASNL is, in particular, a cascode transistor to meet the requirements for feedback immunity in the event of overvoltages or undervoltages at the CANL terminal.

[0113] The number n can be chosen arbitrarily. In particular, the number n, and thus the number of stages or current tap changers, can be selected between 1 and 60. Alternatively, however, a number greater than 60 or a number less than 60, in particular 30, can be chosen for n.

[0114] A resistor R_H is connected between the transmitting stages 121A, 121C. One end of the resistor R_H is connected to the anode of the polarity reversal diode M NDIOPH and to the drain terminal of the transistors M PMIR, M PR, M PO, M PI , MP2 to MP n can be connected via the current step switches of the transmitter stage 121 A. The other end of the resistor R_H is connected to the anode of the polarity reversing diode M NDIOPL and to the drain terminal of the transistors MPo, MP1, MP2 to MP n Can be connected via the current step switches of the transmitter stage 121 C.

[0115] A resistor R_L is connected between the transmitting stages 121 D, 121 B. One end of the resistor R_L is connected to the source terminal of the transistor M NCASNH and to the drain terminal of the transistors MNR, M NO, MN1, MN2 to MN ncan be connected via switches of the fourth transmitting stage 121 D. The other end of the resistor R_L is connected to the source terminal of the transistor M NCASNL and to the drain terminal of the transistors MNR, M NO, M NI , MN2 to MN n Can be connected via the current step switches of the second transmission stage 121 B.

[0116] Each of the polarity reversal diodes M NDIOPH, M NDIONL, M NDIOPL, M NDIONH protects the corresponding transmitter stage 121 A, 121 B, 121 C, 121 D against positive feedback to terminal 43 (CAN supply) and negative feedback to terminal 44 (CAN_GND). Each of the polarity reversal diodes M NDIOPH, M NDIONL, M NDIOPL, M NDIONH can also be referred to as a blocking diode.

[0117] Each of the transmission stages 121 A, 121 B, 121 C, 121 D, or more precisely, their current step switch with the associated control circuit T_A, T_B, T_C, T_D, sets a transmission current value for the associated transmission stage 121 A, 121 B, 121 C, 121 D depending on the operating mode for the arbitration phase 451 or data phase 452 of the transmission module 121 and the transmission signal TxD. Explanations for this are also included in the preceding Table 1. The transmission current value of the individual transmission stage 121 A, 121 B, 121 C, 121 D can thus be set depending on the operating mode, such as arbitration (SLOW or SIC) or data phase (FAST_TX or FAST_RX) of the transmission module 121 and the transmission signal TxD. Thus, each transmitting stage 121 A to 121 D is designed to set the value of the electrical current IA1 to lAn etc. output by the transmitting stage 121 A to 121 D during operation of the transmitting module 121 at the input of the current mirror which is present in the respective transmitting stages 121 A to 121 D. The electrical currents IA1 to lAn etc.can also be referred to as 11 to In for short. The setting of the transmission current values ​​is described in more detail below using Fig. 10 and Fig. 11 for the electrical currents 11 to In of the individual step circuits 121 A1, 121 B1, 121 C1, 121 D1 and Table 2.

[0118] Each of the transistors M NCASPH, M NCASNL, M NCASPL, M NCASNH can also be referred to as an HV standoff device. Each of the transistors M NCASPH, M NCASPL protects the CMOS transistors M PMIR, M PR, M PO, M PI , MP2 to MP n of the current mirror for the transmitting stages 121 A, 121 C, by the transistors M NCASPH, M NCASPL absorbing high voltage drops. Each of the transistors M NCASNH, M NCASNL protects the CMOS transistors M NMIR, MNR, M NO, M NI, MN2 to MN nof the current mirror for the transmitting stages 121 D, 121 B, in which the transistors M NCASPH, M NCASPL absorb high voltage drops. The HV cascodes or transistors M NCASPH, M NCASNL, M NCASPL, M NCASNH enable compliance with limit values ​​(maximum rating parameters), such as voltage at CANH and CANL from -27V to +40V.

[0119] In the transmitter module 121, the transmitter stage 121A is connected between the connection 43 for the power supply and the connection 41 (CANH) for the CAN_H signal. The transmitter stage 121C is connected between the connection 43 for the power supply and the connection 42 (CANL). The transmitter stage 121D is connected between the connection 41 (CANH) for the CAN_H signal and the connection 44 for ground or the connection 44 (CAN_GND). The transmitter stage 121B is connected between the connection 42 (CANL) for the CAN_L signal and the connection 44 for ground or the connection 44 (CAN_GND). Thus, in the transmitter module 121, the transmitter stage 121A is connected to the CANH path on the one hand. The transmitter stage 121D is connected to the CANH path on the other. On the one hand, the transmitting stage 121 C is connected to the CANL path. On the other hand, the transmitting stage 121 B is connected to the CANL path.Thus, the transmitting module 121 has parallel connections of a specific number of switchable currents of the transmitting stages 121 A, 121 B, 121 C, 121 D in the CANH path and in the CAN L path. The current value of the transmitting stages 121 A, 121 B, 121 C, 121 D is determined by the number of current step switches of the transmitting stages 121 A, 121 B, 121 C, 121 D switched to position 1.

[0120] Fig. 10 shows, as an example, the structure of the first to n-th current step switches S1 to Sn of the transmitting stage 121 D. Accordingly, the first current step switch S1 has a current source IrefDI. The second current step switch S2 has a current source IrefD2. The n-th current step switch Sn has a current source IrefDn. Optionally, at least one of the current sources IrefDI to IrefDn is a current sink.

[0121] The current step switches of the transmission stages 121 A, 121 B, 121 C are constructed in the same way.

[0122] The operation of the circuit of Fig. 9, which has circuits according to Fig. 10, is explained using the following Table 2 depending on the operating mode of the transmitting module 121 and the bus state 401 (dorn), 403 (sic), 402 (rec) in the SIC operating mode (arbitration phase 451) and the bus state L0, L1 in the data phase 452. Table 2 specifies the required impedance as well as the impedance of the transmitting stages 121 A / 121 B and the impedance of the transmitting stages 121 C / 121 D, depending on the state of the transmitting module 121 and the operating mode of the transmitting module 121 in phases 451, 452. In addition, depending on the state of the transmitter module 121 and the operating mode of the transmitter module 121, the driver current of the transmitter stages 121A / 121B and the transmitter stages 121C / 121D is specified in phases 451, 452. The driver current of the transmitter stages 121A / 121B and the transmitter stages 121C / 121D is supplied by the associated current step switches S1 to Sn.

[0123] Table 2: Required impedance and driver current depending on the transmit state

[0124] If the impedance is “infinite”, the transmitter module 121 or the respective transmitter stage 121 A, 121 B, 121 C, 121 D is switched off or not conductive.

[0125] In the transmitter stage 121, the resistors R_H and R_L are used to adjust the differential resistance between the terminals CANH, CANL during the transmitter module state (SIC state). The resistors R_H and R_L each have a value of 240 ohms, for example. The target is an impedance of

[0126] 120 Ohm according to the characteristic impedance Zw of the bus wires 41, 42. On the other hand, the impedance of the current mirrors of all four transmitting stages can be 121 A,

[0127] 121 B, 121 C, 121 D must be chosen significantly larger than 240 ohms. This simplifies the process by connecting the two 240 ohm resistors in parallel, resulting in a matched impedance of 120 ohms.

[0128] Furthermore, even in state 401 (dorn), the transmitter stage 121 can set a differential resistance between the CANH and CANL terminals that matches the characteristic impedance of the bus wires 41 and 42, typically 120 ohms each. This prevents reflections in state 401 (dorn).

[0129] The described design of transmit stage 121 prevents the need for a supply voltage of > 5V at terminal 43, which is not possible due to system requirements or CAN specifications. However, this would be necessary if the previously described advantageous behavior were to be achieved with a solution using a resistor concept in transmit stages 121 A, 121 B, 121 C, and 121 D. An additional advantage of the described design of transmit stage 121 is that the current flowing in the two paths of transmit stages 121 A / D and 121 B / C during state 403 (sic) can be set arbitrarily or "freely," as indicated in Table 1.

[0130] The division of each transmission stage 121 A, 121 B, 121 C, 121 D of Fig. 9 into n parts or the n current stages of the current stage switches allows a time-staggered and controlled switching process between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 of the data phase 452. In particular, the current values ​​of the n current stages of the current stage switches are set, as illustrated in Fig. 11 in a specific example.

[0131] Fig. 11 shows an example of the current level per switching stage or the current step switches S1 to S12. Thus, in the example shown, twelve of the current stages or current step switches S1, S2 to S6 to S12 are used for each of the transmitting stages 121 A, 121 B, 121 C, 121 D. The current stages or current step switches S1, S2 to S6 to S12 are connected to the corresponding transistors MPMIR, MPR, MPO, MPI, MP2 to MP nof the current mirror for the transmitting stages 121A, 121C of Fig. 9 or the associated transistors MNMIR, MNR, MNO, MNI, MN2 to MN n The current mirror for the transmitting stages 121 D, 121 B of Fig. 9 can be switched on or off. In the example of Fig. 11, n = 12.

[0132] The value of the current I (vertical axis in Fig. 11) or I1, I2, I6, I12, etc. is set by selecting the value of the electrical current of the respective current stage or current stage switch S1 to S12. The individual current stages or current stage switches S1 to S12 (horizontal axis in Fig. 12) thus have current sources IrefDI, IrefD2 to IrefDn, which supply an electrical current with different current values.

[0133] To generate the bus states 401, 402, 403 in the arbitration phase 451 or the bus states L0, L1 of the data phase 452 according to Table 2, the individual current stages S1 to S12 are switched on or off with a time offset using the control circuits T_A, T_B, T_C, T_D of the transmitting stages 121 A, 121 B, 121 C, 121 D. As a result, a corresponding electrical current I flows in the CANH path or CANL path into which the transmitting stage 121 A, 121 B, 121 C, 121 D is connected.

[0134] In general, it is advantageous to design the staggering stages for each switching stage or current stage S1 to S12 such that the shape of the difference signal VDIFF follows the Gaussian error function. This analytically produces the lowest emission.

[0135] For example, for the transition from a state 402 (recessive) to a state 401 (dominant), which corresponds to a rising edge of the differential voltage VDIFF of Fig. 4, the current in the CANH path and in the CANL path can be gradually increased to generate a dominant level on bus 40 by staggered switching on of the current stages of the transmitting stages 121 A, 121 B, 121 C, 121 D. The transition from a state 401 (dominant) to a state 402 (recessive), which corresponds to a falling edge of the differential voltage VDIFF of Fig. 4, is effected by staggered switching off of the current stages of the transmitting stages 121 A, 121 B, 121 C, 121 D, whereby the current in the CANH and CANL paths is gradually reduced. The total current, which is given by the sum of the currents I1 to I12 or I1 to In of all current stages S1 to Sn, flows during state 401 (dominant).Here, all current stages S1 to Sn of the transmitting stages 121 A, 121 B, 121 C, 121 D are switched on and the total current for generating the dominant level of nominal VDIFF = 2V flows through the bus resistor or terminating resistor 49.

[0136] Timing control makes it possible to adjust the signal shape of CAN_H and CAN_L as required in Fig. 6. Targeted shaping of the signal waveforms for CAN_H and CAN_L is possible. Overall, the bus states 401, 402, and 403 in the arbitration phase 451 or the bus states L0 and L1 in the data phase 452 can be shaped according to the specifications.

[0137] The currents of the individual current stages S1 to Sn of the transmitting stages 121A, 121B, 121C, and thus their respective share of the total current, can be selected in different ways to achieve the lowest possible emission, in particular a low emission of the transmitting module 121. For low emission, it is advantageous to add or remove little current at the beginning and end of a switching operation between bus states 401, 402 and to add or remove a large amount of current in the middle of the switching operation. Therefore, the setting of the currents I1, I2 to I1 of the current stages S1 to S12 shown in Fig. 11 is very advantageous.

[0138] In contrast to an implementation with identical current sources in the current stages S1 to Sn of the transmitting stages 121 A, 121 B, 121 C, the configuration according to Fig. 9 to 11 avoids a current increase during switching off, the transition from the state 401 (dominant) to the state 402 (recessive).

[0139] The granularity of the temporal staggering for switching the individual current stages S1 to S12 on or off is in the range of approximately 2 ns. Such small steps or intervals for the temporal staggering cause minimal common-mode interference and have a minimal negative impact on emissions. The current steps, which are set via the current stages S1, S2, S6, and S12, are kept fixed, and the temporal staggering is varied to ensure the smoothest possible behavior during the switch-on process (according to the Gaussian error function). Varying the time steps or intervals also prevents the occurrence of a narrowband frequency line in the emitted frequency spectrum.

[0140] Alternatively, the staggering steps can be executed using fixed time steps and varied current steps.

[0141] The structure of the transmitting module 121 shown enables symmetrical switching of the bus signals CAN_H and CAN_L (Fig. 6) with steep switching edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, L1 of the data phase 452.

[0142] On the one hand, the structure of the transmitter module 121 shown, due to the use of fast CMOS switches or CMOS transistors, enables much steeper switching edges to be achieved between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states LO, L1 of the data phase 452. On the other hand, the symmetry of the temporal course of the bus signals CAN_H and CAN_L, which is necessary to comply with the emission limits, is achieved during the switching processes. The matching of the characteristic curves is achieved by the selection or use of the current sources of the step circuits 121 A1, 121 B1, 121 C1, 121 D1. The matching of the characteristic curves is therefore less dependent on the parameters of the transistors used in the step circuits 121A1, 121 B1, 121 C1, 121 D1.

[0143] The dominant state 401 (dorn) is determined by matching the tap-changer circuit 121 A1 with the tap-changer circuit 121 B1. Here and in the following, the term "matching" refers to an active trimming step according to one possibility. According to another possibility, "matching" means that the values ​​of the current sources of the tap-changers 121 A1, 121 B1 match as closely as possible, which occurs by default without a matching or trimming step.

[0144] The Sic state (sic) is determined by matching the tap circuit 121 A1 with the tap circuit 121 C1 and by matching the tap circuit 121 D1 with the tap circuit 121 B1.

[0145] In XL-Fast mode, the LO state is determined by matching the tap changer 121 A1 with the tap changer 121 B1. The L1 state is determined by matching the tap changer 121 C1 with the tap changer 121 D1.

[0146] The following Table 3 shows an example of the values ​​a, b, c, d, z that can be selected for the transmitting module 121 of Fig. 9 to generate the respective transmitting module states. The value a indicates how many current step switches of the first transmitting stage 121 B are switched to the conductive state. The value b indicates how many current step switches of the second transmitting stage 121 B are switched to the conductive state. The value c indicates how many current step switches of the third transmitting stage 121 C are switched to the conductive state. The value d indicates how many current step switches of the fourth transmitting stage 121 D are switched to the conductive state. The value z indicates how many of the transistors MPi to MP n and how many transistors of the transistors MNi to MN nare conductive. Thus, Table 3 shows an example of how many parallel-connected current step switches of each transmission stage 121 A, 121 B, 121 C, 121 D are each conductive in order to set the corresponding states of the transmission module 121 (transmitter states). As can be seen from Table 3, for example, in the arbitration phase to drive a state 401 (dorn), a number of 60 transistors MP and a number of 60 transistors MN, as well as a number of 60 current step switches of the first transmission stage 121 A and a number of 60 current step switches of the second transmission stage 121 B, are conductive.

[0147] Table 3: Required number of parallel-connected switching transistors for the transmitting stages 121 A, 121 B, 121 C, 121 D depending on the state of the transmitting module 121 (transmitter state).

[0148] The described transmitter module 121 enables a time-staggered and controlled switching process by dividing its four transmission stages 121A, 121B, 121C, 121D into n parts. Switching on according to a Gaussian error function is possible. This allows for setting a smooth behavior during the switch-on process. Furthermore, the possible variation of time steps during switch-on prevents the occurrence of a narrowband frequency line in the emission frequency spectrum. Alternatively, it is possible to carry out a staggered and controlled switching process with the described transmitter module 121 using fixed time steps and varied voltage steps. This also allows the emission behavior of the transmitter module 121 to be influenced such that the specified limit values ​​are maintained.

[0149] Furthermore, the described transmission module 121 can reduce effects due to asymmetrical behavior of the transmission stages 121 A, 121 B, 121 C, 121 D, which can occur in the dor, sic, and rec transmission states and degrade the emission. The transmission module 121 prevents uneven behavior of components in transmission stages 121 A, 121 B (effect 1) of a full bridge, so that in the dom state, a change in the common-mode voltage is minimized or prevented compared to the rec state. Furthermore, the transmission module 121 can prevent uneven behavior of components in transmission stages 121 A / 121 D and 121 C / 121 B of the full bridge (effect 2), so that in the sic state, a change in the common-mode voltage is minimized or prevented compared to the rec state.This is particularly advantageous because only if, starting from the common mode level of the rec state, the common levels in the dom state and in the sic state match those of the rec state, a sufficient emission result can be achieved, but the causes leading to the behavior of effect 1 may be different from those leading to effect 2.

[0150] All previously described embodiments of the transmitter module 121 can also be used with a modified full-bridge circuit topology. For example, the diodes can be arranged at a different location in the path to terminal 43. In this case, the cascodes can be eliminated, and more voltage-resistant current step switches can be used in the transmitter stages 121A, 121B, 121C, and 121D.

[0151] Fig. 12 shows the basic structure of a transmission module 1210 according to a second embodiment, which can be used for one of the subscriber stations 10, 30 instead of a transmission module 121 of the previous embodiment. The transmission module 1210 according to the present embodiment is constructed identically to the transmission module 121 of the previous embodiment, except for the following differences.

[0152] The transmit module 1210 has a control circuit 15A for adjusting the common-mode voltage VCM for bus states in which VDIFF is not equal to 0V. Such bus states are, for example, the state VDIFF = 2 V, which corresponds to the state 401 (dorn), or the state VDIFF = 1 V, which corresponds to the state levelO or L0, or the state VDIFF = -1 V, which corresponds to the state levell or L1, as previously described with reference to Fig. 3 and Fig. 4 and Fig. 6 and Fig. 8.

[0153] The control circuit 15A has a replica 153 in which a scaled bus load 1531 with two resistors RDLI, RDL2 is arranged. The scaled bus load 1531 has a scaled size of the termination resistor 49 of the bus 40. The scaled bus load 1531 has a size that is, in particular, smaller by a factor of 100 or some other factor than the size of the termination resistor 49. In particular, the scaled bus load 1531 is an adjustable resistor.

[0154] Between the resistors RDLI and RDL2, the replica 153 has a central tapping point that is equal to the common-mode point or tapping point 157. The resistors RDLI and RDL2 have the same size, or more precisely, the same resistance value.

[0155] The replica 153 is otherwise constructed as previously described for the replica 152 of the transmit module 121 of the previous embodiment.

[0156] The bandwidth of the control loop of the control circuit 15A, in particular the bandwidth of the differential amplifier 151, is selected such that within the bit duration t_bt1 or t_bt2 shown in Fig. 3, an adjustment of the common-mode voltage VCM is carried out for bus states in which VDIFF is not equal to 0V.

[0157] The replica 153 makes it possible to determine the (undisturbed) common-mode voltage VCM, which also maps the process and temperature dependencies of the outputs of the transmitting stage 1210. According to a first modification of the transmitting module 1210 of Fig. 12, at least two replicas 153 or at least two replicas 152, 153 are connected in parallel in the control circuit 15. In this way, multiple replicas can be used for calibration in at least two of the possible bus states, in particular all possible bus states 401 (dorn), 402 (rec), 403 (sic), L0, L1 of Fig. 3 to Fig. 4 or Fig. 6 and Fig. 8. In particular, a different replica 152 can be used for each bus state to be calibrated.

[0158] According to a second modification of the transmit module of Fig. 12, at least two replicas are connected in parallel in the control circuit 15, wherein the replica is not only the output stage of the transmit stages 121A, 121D, but a replica of the entire full bridge. Such a replica is the output stage of the transmit stages 121A, 121B, 121C, 121D connected in the H-bridge (full bridge). In this way, multiple replicas can also be used for calibration in at least two of the possible bus states, in particular all possible bus states 401 (dorn), 402 (rec), 403 (sic), L0, L1 of Fig. 3 to Fig. 4 or Fig. 6 and Fig. 8.

[0159] Fig. 13 shows the basic structure of a transmission module 1211 according to a third embodiment, which can be used for one of the subscriber stations 10, 30 instead of a transmission module 121, 1210 of the preceding embodiments. The transmission module 1211 according to the present embodiment is constructed identically to the transmission module 1210 of the preceding embodiment, except for the following differences.

[0160] The transmitter module 1211 has a control circuit 15B with switchable bus load

[0161] 1531 in a replica 153A. For this purpose, the replica 153A has a switching unit

[0162] 1532 and a terminal 1533, into which a control signal sic can be input to control the switching unit 1532. The control signal sic can be output, for example, by the control device 124. In the state with bus voltage VDIFF = 0V, which corresponds to the SIC state 403 of Fig. 6, the logic signal sic=1 is switched to terminal 1534. This short-circuits the scaled bus load 1531.

[0163] Important in this implementation is smooth switching between the control states, especially on the sic signal at terminal 1534. This smooth switching can be achieved, for example, by less steep edges in the sic signal. Additionally or alternatively, the smooth switching can be achieved by a corresponding bandwidth of the differential amplifier 151.

[0164] The replica 153A is otherwise constructed as previously described for the replica 153 of the transmit module 121 of the previous embodiment.

[0165] Thus, the control circuit 15B can be used to adjust the common-mode voltage VCM for bus states in which VDIFF is equal to or unequal to 0V. Such bus states are, for example, the sic state (VDIFF = 0V) or the state VDIFF = 2V, which corresponds to the state 401 (dorn), or the state VDIFF = 1V, which corresponds to the state level0 or L0, or the state VDIFF = -1V, which corresponds to the state level1 or L1, as previously described with reference to Fig. 3 and Fig. 4, as well as Fig. 6 and Fig. 8.

[0166] The replica 153A makes it possible to determine the (undisturbed) common-mode voltage VCM, which reflects the process and temperature dependencies of the outputs of the transmitter stage 1211. This applies to all previously mentioned bus states where VDIFF is equal to or not equal to 0V.

[0167] Also in the transmission stage 1211, several replicas 152, 153, 153A are possible, as previously described with respect to the transmission stage 1210.

[0168] Fig. 14 shows the basic structure of a transmission module 1212 according to a fourth embodiment, which can be used for one of the subscriber stations 10, 30 instead of a transmission module 121, 1210, 1211 of the preceding embodiments. The transmission module 1212 according to the present embodiment is constructed identically to the transmission module 121 of the first embodiment, except for the following differences. The transmission module 1212 has transmission stages 121A1, 121B1, 121C1, 121D1, each constructed as resistive transmission stages. As a result, only transistors MPCURR and MNCURR are present as current limiters. However, the control circuit 15 is constructed as previously described with respect to the transmission module 121.

[0169] Transistor MPCURR ensures that a current IHS flowing from transistor MPCURR into the full bridge to the transmitting stages 121A, 121C is less than a predetermined value. In particular, IHS < 115 mA applies. Transistor MNCURR ensures that a current ILS flowing from the full bridge from the transmitting stages 121D, 121B into transistor MNCURR is less than a predetermined value. In particular, ILS < 115 mA applies.

[0170] The first transmitting stage 121 A1 has resistors R_M_HS, each connected to the current step switches of the transmitting stage 121 A1, as shown in Fig. 14. The second transmitting stage 121 B1 has resistors R_M_LS, each connected to the current step switches of the transmitting stage 121 B1. The third transmitting stage 121 C1 has resistors R_C_LS, each connected to the current step switches of the transmitting stage 121 C1. The fourth transmitting stage 121 D1 has resistors R_C_HS, each connected to the current step switches of the transmitting stage 121 D1.

[0171] Otherwise, the structure and function of the transmit module 1212 for generating the bus states are the same as those described with reference to Fig. 3 to Fig. 8.

[0172] In the transmitter module 1212, which is constructed with a resistive H-bridge (full bridge), the common-mode voltage VCM is determined primarily by matching the resistors of the transmitter stages 121 A1 , 121 B1 , 121 C1 , 121 D1 . Therefore, in the transmitter module 1212, the common-mode voltage VCM can be small depending on the design of the transmitter stages 121 A1 , 121 B1 , 121 C1 , 121 D1 . If the leakage currents of the diodes of the transmitter module 1212 are not negligible, the channel resistance of the current limiters, in particular the transistors MPCURR, M NNCURR, can be adjusted by adjusting the limiting currents (l_CTRL and l_BIAS), thus adjusting the common-mode voltage VCM upwards or downwards.

[0173] Also in the transmission stage 1212, several replicas 152, 153, 153A are possible, as previously described with respect to the transmission stages 1210, 1211.

[0174] Thus, with the previously described transmit modules 121, 1210, 1211, 1212 and their control circuits 15, 15A, 15B, a balancing of the common-mode voltage VCM can be achieved, so that the emission can be minimized even during the switching operations between the different bus states 401, 402, 403, L1, L0 of Fig. 3, Fig. 6 and Fig. 8.

[0175] All previously described configurations of the transmission modules 121, 1210, 1211, 1212, the transmission / reception devices 12, 22, the control circuits 15, 15A, 15B of the subscriber stations 10, 20, 30, the bus system 1, and the method implemented therein according to the first and second embodiments, and their modifications, can be used individually or in all possible combinations. In addition, the following modifications are particularly conceivable.

[0176] The previously described bus system 1 according to the first and second exemplary embodiments is described using a bus system based on the CAN protocol. However, the bus system 1 according to the first and / or second exemplary embodiments can alternatively be a different type of communications network in which the signals are transmitted as differential signals. It is advantageous, but not a mandatory requirement, that in the bus system 1, exclusive, collision-free access of a subscriber station 10, 20, 30 to the bus 40 is guaranteed, at least for certain time periods.

[0177] The bus system 1 according to the first and / or second embodiment and their modifications is, in particular, a CAN bus system, a CAN HS bus system, a CAN FD bus system, a CAN SIC bus system, or a CAN XL bus system. However, the bus system 1 can be another communication network in which the signals are transmitted as differential signals and serially over the bus.

[0178] Thus, the functionality of the previously described embodiments can be used, for example, in transmitting / receiving devices 12, 22 that can be operated in a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system.

[0179] In the bus system 1, subscriber stations 10, 30 may be present, of which at least one subscriber station uses a transmission module 121 according to Fig. 9 and at least one subscriber station uses a transmission module 1210 according to Fig. 12 or a transmission module 1211 according to Fig. 13 or a transmission module 1212 according to Fig. 14.

[0180] The number and arrangement of subscriber stations 10, 20, 30 in the bus system 1 according to the first to fourth embodiments and their modifications are arbitrary. In particular, only subscriber stations 10 or only subscriber stations 30 are present in the bus systems 1 of the first or second embodiment.

Claims

Claims 1) Transmission module (121; 1210; 1211; 1212) for transmitting differential signals in a serial bus system (1), comprising a first transmission stage (121 A; 121 A1) for generating transmission currents (11 to In) for a first signal (CAN_H) to be transmitted onto a bus (40) of the bus system (1), a second transmission stage (121 B; 121 B1) for generating transmission currents (11 to In) for a second signal (CAN_L) to be transmitted onto the bus (40) as a signal differential to the first signal (CAN_H), a third transmission stage (121 C; 121 C1) for generating transmission currents (11 to In) for the first signal (CAN_H), a fourth transmission stage (121 D; 121 D1) for generating Transmission currents (11 to In) for the second signal (CAN_L), and a control circuit (15; 15A; 15B) for adjusting a common-mode voltage (VCM) for the first to fourth transmission stages (121 A to 121 D; 121 A1 to 121 D1), wherein the first to fourth transmission stages (121 A to 121 D;121 A1 to 121 D1) are connected in a full bridge, in which the first and fourth transmitting stages (121 A, 121 D; 121 A1 , 121 D1 ) are connected in series and the third and second transmitting stages (121 C, 121 B; 121 C1 , 121 B1) are connected in series, wherein the control circuit (15; 15A; 15B) has a replica (152; 153; 153A) of an output stage of the transmitting module (121; 1210; 1211; 1212), and wherein the replica (152; 153; 153A) is connected to the output stage of the transmitting module (121; 1210; 1211; 1212). 2) Transmission module (121; 1210; 1211; 1212) according to claim 1, wherein a common mode point (157) of the replica (152; 153; 153A) on the Common mode voltage (VCM) of the output of the transmitting stages (121 A, 121 D; 121 A1, 121 D1). 3) Transmission module (121; 1210; 1211; 1212) according to claim 2, wherein the control circuit (15; 15A; 15B) further comprises a differential amplifier (151) having an input connected to the common mode point (157) of the replica (152; 153; 153A), and a control transistor (MNCTRL) for controlling a common mode voltage (VCM) to a predetermined value (AV), the common mode voltage (VCM) being applied to the common mode point (157) of the replica (152; 153; 153A). 4) Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, wherein the replica (152; 153; 153A) comprises a series circuit of a transistor (MPR), a diode (MNDIOPR), a transistor (MPCASPR), a diode (MNDIONR), a transistor (MPCASNR) and a transistor (MNR) in the order mentioned, and wherein the sizes of the components of the series circuit are smaller by a predetermined factor than the sizes of the components of the output of the first and fourth transmission stages (121A, 121D; 121A1, 121D1). 5) Transmission module (121; 1210; 1211; 1212) according to claim 4, wherein the transistor (MPCASPR) and the transistor (MPCASNR) are each designed as a cascode. 6) Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, wherein output terminals (41, 42) of the full bridge are provided for connection to a terminating resistor (49) of the bus (40), and wherein the replica (153; 153A) in the series circuit has a bus load (1531) which is a replica of a terminating resistor (49) of the bus (40). 7) Transmitter module (121; 1210; 1211; 1212) according to claim 6, wherein the bus load (1531) comprises two resistors (RDLI, RDL2), both of which are connected to the common mode point (157) of the replica (152; 153; 153A). 8) Transmission module (121; 1210; 1211; 1212) according to claim 6 or 7, wherein the replica (153A) comprises a switching unit (1532) for switching on or off the bus load (1531). 9) Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, wherein each transmission stage (121 A to 121 D; 121 A1 to 121 D1) is designed to adjust the value of the electrical current (I1 to In) output by the transmission stage (121 A to 121 D; 121 A1 to 121 D1) during operation of the transmission module (121) with a current mirror at the input of the transmission stage (121 A to 121 D; 121 A1 to 121 D1). 10) Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, wherein the current mirror at the input of each transmission stage (121 A to 121 D; 121 A1 to 121 D1) comprises two CMOS transistors, wherein the CMOS transistors of the current mirror at the input of the first transmission stage (121 A; 121 A1) are PMOS transistors, wherein the CMOS transistors of the current mirror at the input of the second transmission stage (121 B; 121 B1) are NMOS transistors, wherein the CMOS transistors of the current mirror at the input of the third transmission stage (121 C; 121 C1) are PMOS transistors, and wherein the CMOS transistors of the current mirror at the input of the fourth transmission stage (121 D; 121 D1) NMOS transistors are. 11) Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, wherein each transmission stage (121 A to 121 D; 121 A1 to 121 D1) has at least two current stages (S1 to Sn) which are connected in parallel to one another. 12) Transmission module (121; 1210; 1211; 1212) according to claim 11, wherein the at least two current stages (S1 to Sn) have at least one current sink. 13) Transmission module (121; 1210; 1211; 1212) according to claim 11 or 12, wherein a number n of the at least two current stages (S1 to Sn) is the same for each of the first to fourth transmission stages (121 A to 121 D; 121 A1 to 121 D1), where n is a natural number greater than 1. 14) Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, further comprising a first resistor (R_H), one end of which is connected to the first transmission stage (121 A; 121 A1) and the other end of which is connected to the third transmission stage (121 C; 121 C1), and a second resistor (R_L), one end of which is connected to the second transmission stage (121 B; 121 B1) and the other end of which is connected to the fourth transmission stage (121 D; 121 D1). 15) Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, further comprising a control circuit (T_A; T_B; T_C; T_D) for controlling switchable components of the first to fourth transmission stages (121 A to 121 D; 121 A1 to 121 D1) as a function of a digital transmission signal (TxD) and of an operating mode (SIC; FAST_TX) set for the transmission module (121; 1210; 1211; 1212). 16) Transmission module (121; 1210) according to claim 15, wherein the control circuit (T_A; T_B; T_C; T_D) is designed for the time-staggered and controlled switching of the currents of at least two current step switches (S1 to Sn) of the first to fourth transmission stages (121 A to 121 D; 1210A to 1210D). 17) Transmitting / receiving device (12; 22) for a subscriber station (20) for a serial bus system (1), with a transmitting module (121; 1210; 1211; 1212) according to one of the preceding claims, and a receiving module (122) for receiving signals from the bus (40). 18) Subscriber station (10; 20; 30) for a serial bus system (1), with a transmitting / receiving device (12; 22) according to claim 17, and a communication control device (11; 21) for controlling the communication in the bus system (1) and for generating a digital transmission signal (TxD) for controlling the first to fourth transmission stages (121 A to 121 D; 121 A1 to 121 D1). 19) Subscriber station (10; 20; 30) according to claim 18, wherein the subscriber station (10; 20; 30) is designed for communication in a bus system (1) in which at least temporarily exclusive, collision-free access of a subscriber station (10, 20, 30) to the bus (40) of the bus system (1) is ensured. 20) Method for transmitting differential signals in a serial bus system (1), wherein the method is carried out with a transmitting module (121; 1210; 1211; 1212) having a first to fourth transmitting stage (121A to 121D; 1210A to 1210D) and a control circuit (15; 15A; 15B), and wherein the method comprises the steps of Generating, with the first transmission stage (121 A; 121 A1 ), transmission currents (11 to In) for a first signal (CAN_H) to be sent on a bus (40) of the bus system (1), generating, with the second transmission stage (121 B; 121 B1 ), transmission currents (11 to In) for a second signal (CAN_L) which is to be transmitted to the bus (40) as a signal differential to the first signal (CAN_H), Generating, with the third transmission stage (121 C; 121 C1), transmission currents (11 to In) for the first signal (CAN_H), and generating, with the fourth transmission stage (121 D; 121 D1 ), transmission currents (11 to In) for the second signal (CAN_L), Adjusting, with the control circuit (15; 15A; 15B), a common-mode voltage (VCM) for the first to fourth transmitting stages (121 A to 121 D; 121 A1 to 121 D1), wherein the first to fourth transmitting stages (121 A to 121 D; 121 A1 to 121 D1) are connected in a full bridge, in which the first and fourth The first and second transmitting stages (121 A, 121 D; 121 A1, 121 D1) are connected in series and the third and second transmitting stages (121 C, 121 B; 121 C1, 121 B1) are connected in series, wherein the control circuit (15; 15A; 15B) has a replica (152; 153; 153A) of an output stage of the transmitting module (121; 1210; 1211; 1212), and wherein the replica (152; 153; 153A) is connected to the output stage of the transmitting module (121; 1210; 1211; 1212).

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