Method for operating a computing unit in a secure operating mode

Abstract

The invention relates to a method for operating a computing unit in a secure operating mode, comprising: reading in an activation command (208) for activating a secure operating mode; activating the secure operating mode in response to the read-in activation command; in the secure operating mode, reading in commands and calculating a current test value from a command currently being executed and a previous test value; and in the secure operating mode, checking the current test value at least once.

Description

[0001] Description

[0002] Method for operating a computing unit in a secure operating mode

[0003] The present invention relates to a method for operating a computing unit in a secure operating mode as well as a computing unit and a computer program for carrying out the method.

[0004] Background of the invention

[0005] A computing unit such as a microcontroller or a system-on-a-chip (SoC) can implement a functionally safe execution platform (referred to in English as a "safe island," "vital module," "safe backbone," or "safe execution platform") to enable software execution at the highest level of operational safety or functional safety. For example, in the automotive sector, this safety level can be ASIL-D, the highest safety requirement level for safety-relevant systems in motor vehicles according to the ISO 26262 safety standards and the ASIL (Automotive Safety Integrity Level) defined therein.

[0006] Such a functionally reliable execution platform can be implemented, for example, by providing two identical processor cores and operating them in a so-called lockstep mode. The two cores execute the same processes and compare their results against each other. An error signal can be output if deviations are detected. The cores usually have separate clock trees and separate areas on the respective chip. Program code can be stored, for example, in an embedded NOR flash memory, and data in an embedded static ROM. However, such a lockstep concept with an additional, redundant processor core is associated with high energy consumption and a large space requirement. Furthermore, the lockstep concept cannot be implemented equally well for all processor types.For example, the lockstep concept can be well-suited for medium-performance cores used, for example, for engine control or for controlling braking systems in vehicles. However, at higher performance levels, the lockstep approach often scales poorly. High-performance cores often have limited parallel lockstep capability. Nor flash memory often cannot be scaled to nodes below 28 nm and requires more area than NAND flash. Embedded static RAM typically cannot exceed 10 mebibytes.

[0007] Functionally reliable execution platforms based on the lockstep principle are therefore often only suitable to a limited extent for systems with large program code and large amounts of data, as is the case, for example, in autonomous driving.

[0008] Disclosure of the invention

[0009] According to the invention, a method for operating a computing unit in a secure operating mode, as well as a computing unit and a computer program for implementing the method, are proposed, having the features of the independent patent claims. Advantageous embodiments are the subject of the dependent claims and the following description.

[0010] The invention enables the computing unit to be operated in the secure operating mode in a secure manner with respect to operational safety or functional safety. When safety or secure is mentioned in this context, this should be understood in particular in the sense of operational safety or functional safety, which is referred to as "safety" in English, as opposed to information technology security or information security, which is referred to as "security" in English.

[0011] The computing unit comprises, in particular, a processor unit with one or more processor cores, as well as a non-volatile memory unit, e.g., a (NAND) flash memory, and a volatile memory unit, e.g., an (LPDDR) RAM memory. Software or program code is expediently stored in the non-volatile memory unit. The software comprises individual commands, machine commands, or instructions, which were created, in particular, by a compiler during a compilation process. For execution, the individual commands are read from the volatile memory unit by the processor unit and executed. During regular operation or regular operating mode of the computing unit, this reading or fetching of commands occurs in a conventional manner. During the secure operating mode, however, the reading occurs in a special manner to enable secure operation of the computing unit.

[0012] For this purpose, an activation command for activating the secure operating mode is read and executed by the processor unit, particularly during the regular operating mode of the computing unit. In response to this read activation command, the secure operating mode of the processor unit is activated. For example, this activation command can be implemented using a compiler instruction or a pragma directive.

[0013] In the secure operating mode, commands are read by the processor unit, in particular from the volatile memory unit, in particular in each case during an instruction fetch, and a current check value is calculated from a currently executed command and a previous check value by the processor unit, in particular according to a check value calculation scheme pw n =f(o n , pwn -i), where the test value pw n a function f of the previous test value pw n -i and the current command o n The respective read commands o n can then be executed by the processor unit. If no previous check value pwo exists at the first call (n=1), a predetermined value (e.g., zero) can be used instead, or an initial check value pwo can be read in together with the activation command. Accordingly, the activation command can be enriched with the initial check value, for example, as an argument to the command.

[0014] In safe operating mode, the processor unit checks the current test value at least once. For example, the current test value can be compared with a corresponding pre-calculated reference test value. For this purpose, the corresponding reference test value can also be stored in the non-volatile memory unit for each software command. Since the chain or sequence of commands is known in advance, the sequence of test values ​​can also be predetermined. For example, the current test value can be checked at regular intervals or upon specific events.

[0015] Safe operating mode enables the implementation of a functionally safe execution platform ("Safe Island", "Vital Modules", "Safe Backbone", or "Safe Execution Platform") in a low-effort, energy-saving, and space-saving manner. Safe operating mode can enable software to be executed at a high or highest safety level, for example, at the highest safety integrity level ASIL-D according to the ISO 26262 automotive safety standards. Using the check values, the individual commands read in safe operating mode can be conveniently checked for correctness and integrity, and it can also be assessed whether the individual commands were read correctly.If an error is detected during the test value check, a predefined action can be taken, for example, an error message can be issued or an entry can be created in an error log, or the system can be stopped or transferred to a safe state if necessary. In safe operating mode, in particular, safe reading of commands can be enabled, even from an insecure storage unit, e.g., a conventional (NAND) flash memory or (LPDDR) RAM, or even via an insecure communication system, e.g., an internal processor bus system.

[0016] Conveniently, the individual instructions are enriched with a respective reference check value outside the processing unit, for example, during the compilation process. They can then be checked by the processor core during their input into the processing unit, depending on this reference check value and the calculated check value, for example, upon the occurrence of a predefined check event. In this way, the integrity of the instructions from the compiler to the processor core can be ensured.

[0017] The method is suitable, for example, for all processor units and logic units that execute a program and read instructions from memory. The method is particularly well-suited for high-performance cores and systems with large program code and large amounts of data, such as those used in autonomous driving. In particular, no special hardware units are required to implement the safe operating mode; conventional memory units and buses can be used, for example. Furthermore, no implementation of error detection codes (EDC) or error correction codes (ECC) in hardware is required. For example, a large external RAM can be used and connected to the processor unit via a conventional standard interface, e.g., a JEDEC LPDDR interface.Furthermore, a conventional external NAND flash drive, for example, can be used to write program code and initialization data to the RAM. Secure operating mode can be conveniently enabled and disabled at any time as needed.

[0018] While the additional reference check values ​​may increase the program code's memory footprint, secure mode eliminates the need for embedded NOR flash memory and embedded static ROM. Secure mode may require additional logic for the processor core, as well as additional instructions and control and status registers (CSRs), which may slightly increase the on-chip footprint, but significantly less than would be required for separately secured memory.

[0019] For example, the check values ​​can each be calculated according to a cyclic redundancy check (CRC). The length of the individual check values ​​can, for example, be selected such that such a check value can be integrated as an immediate value into the activation instruction. Since the check value calculation occurs with each instruction fetch, which in particular runs at full core clock speed, the calculation takes place in a single clock cycle, at least for 16- and 32-bit instructions. The check values ​​are also expediently applicable to 64-bit instructions and longer instructions. In particular, the check values ​​cover at least 128 32-bit instructions (4096 program memory bits), e.g., to avoid consuming too much program space and runtime. In particular, the check value can thus be calculated continuously, but a precalculated comparison value only exists every 128 instructions.A calculation scheme for the check value calculation can be expediently specified in such a way that the hardware complexity and power consumption for the calculation are as low as possible. Furthermore, the calculation scheme can be specified in such a way that different sequences of the same instructions expediently lead to different check values. For example, to meet the ASIL-D safety level, the check values ​​should expediently detect every possible combination of bit errors with at least 99% accuracy. The so-called Hamming weight, i.e., the number of undetected errors, for any number of bit errors is in particular less than or equal to 1% of the number of possible errors.

[0020] According to one embodiment, the (then) current test value is checked in the secure operating mode upon the occurrence of a predefined check event. In this way, it is expedient to specify how often or at which specific events the respective current test value is to be checked during the secure operating mode. According to one embodiment, the predefined check event comprises reading in a predefined check command. Such a check command can be a special machine command to instruct the processor unit to check the respective current test value. Such a check command can expediently be generated at any time as needed or in response to a specific triggering event, e.g., after a predefined number of commands have been read in.In this way, for example, a specified error detection time can be maintained and it can be prevented, for example, that too many read-in, unchecked instructions reduce error coverage—that is, the probability of detecting every combination of errors. For example, such checking instructions can be generated during the compilation process and conveniently placed at a suitable point in the instruction flow. The checking instruction can be enhanced with a reference value.

[0021] Alternatively or additionally, according to one embodiment, the predetermined verification event comprises reading in a jump instruction for executing a jump in the program flow. Such a jump instruction instructs the processor unit to jump to a specific instruction of the program code or to a corresponding memory address and to execute this or the instruction there. Such a jump can, in principle, lead anywhere, even to a potentially dangerous destination. To prevent this, a check of the respective current check value can expediently be performed with each jump, during which, in particular, the check value itself calculated from the jump instruction is checked.

[0022] Alternatively or additionally, according to one embodiment, the predetermined check event comprises reading in a subroutine instruction for executing a subroutine. Such a subroutine instruction can expediently instruct the processor unit, similar to a jump instruction, to execute specific instructions of a specific program code module. In particular, if this subroutine is large or compiled from a different source file than the remaining instructions, a check can be performed. For this purpose, a check of the then-current check value can be performed, in particular, by reading in a respective subroutine instruction.

[0023] Alternatively or additionally, the specified verification event comprises reading a branch instruction for executing multiple branches of instructions. Such a branch instruction can instruct the processor unit to split a regular, linear program flow. At the beginning of each of these instruction branches, a check of the then-current check value can be conveniently performed.

[0024] According to one embodiment, a predetermined measure is taken if no check of the current check value has been performed after a predetermined maximum number of commands have been read in and / or after a predetermined maximum time interval has elapsed. For example, if no check has been performed after 100 commands have been read in and / or after one microsecond, an error message, e.g., a timeout error, can be output as a measure.

[0025] According to one embodiment, a deactivation command for deactivating the safe operating mode is read in, in particular to terminate the safe operating mode. The current check value is then calculated from this deactivation command and the previous check value, and this current check value is checked. Thus, it can finally be determined that the safe operating mode was error-free. Upon reading this deactivation command, the safe operating mode can be deactivated by the processor unit, and the computing unit can operate in regular operating mode again. For example, this deactivation command, corresponding to the activation command, can also be implemented using a compiler instruction or pragma directive.

[0026] According to one embodiment, after the activation command has been read in, a first test value is calculated from a first command currently being executed and a predetermined initial test value or a read-in initial test value as the previous test value. In the safe operating mode, the respective current test value is then checked based on this first test value. For example, the test value calculation can be initialized with this initial value such that the test value checked upon deactivation corresponds to a predetermined expected value, e.g., the value zero, in an error-free case. Alternatively, the test value calculation can also be initialized with a predetermined initial value, e.g., zero, wherein the final value in an error-free case then corresponds to a value that can be precalculated with knowledge of the command chain.

[0027] According to one embodiment, instructions to be read in, for example one, several, or all, are each provided with a reference check value in advance of activating the safe operating mode. These reference check values ​​are particularly expediently created in the executable machine code during a compilation process of the program code. For execution, the instructions to be read in, together with the respective reference check value, are expediently loaded into the volatile memory unit, from which the individual instructions are read in the safe operating mode together with the reference check value. The verification of the respective current check value calculated from a respective read-in instruction during the safe operating mode can then be carried out depending on the respective reference check value of this respective instruction, in particular by comparing the corresponding current check value with the respective reference check value.

[0028] According to one embodiment, in the secure operating mode, the current check value is modified if a number of instructions are skipped and not executed and / or if a number of already executed instructions are executed again, for example, by executing a corresponding jump or branch instruction. In such a case, if individual instructions are skipped or repeated, the check value verification may fail, even though all instructions were read in and executed correctly and as specified. To prevent this, the current check value is modified or changed using a modification instruction. If a number of instructions are not executed during a jump, a first modification instruction is read in and executed by the processor unit.This first modification instruction, for example, an argument of the first modification instruction, modifies the current check value as if the individual skipped instructions had been executed. If, during a loop, a number of previously executed instructions are re-executed, a second modification instruction is read in. This second modification instruction, or an argument of this instruction, modifies the current check value as if the individual re-executed instructions had been executed only once. For example, the respective modification instruction can be created during the compilation process and inserted into the instruction flow at a suitable point.

[0029] According to one embodiment, the computing unit has a processor unit based on a RISC-V instruction set architecture (ISA). An instruction set generally refers to the totality of machine instructions that a processor unit can execute. The RISC-V instruction set architecture is based on the so-called RISC principle (Reduced Instruction Set Computer, RISC), according to which the instruction set comprises a small number of instructions, usually less than 100, each of which can be easily and quickly processed by the processor unit, thereby achieving a simplified processor design, high processor clock speed, and fast execution speed, in contrast to the so-calledCISC (Complex Instruction Set Computing, CISC) architecture provides an instruction set with a large number of instructions (over 100), allowing a processor to execute complex processes. However, this requires a complex processor design. The RISC-V instruction set architecture is an open standard or "open source" and allows for easy modifications and extensions to the instruction set. RISC-V processors, or more generally, processors with a modifiable instruction set architecture, are therefore particularly well-suited for implementing secure operating mode, as the instructions required to execute secure operating mode, such as activation, deactivation, verification, or modification instructions, can be easily integrated into the instruction set. The method is particularly suitable for use in the automotive sector.The computing unit can be embodied, in particular, as a microcontroller or control unit in a (motor) vehicle. Processes executed by the computing unit can, for example, include safety-critical functions performed for the safe operation and control of the vehicle, for example, in the course of engine control, driver assistance functions, or autonomous driving, etc. The safety or reliability and integrity of the control unit can be increased by the present method. In particular, the method can fulfill safety requirements in the (motor) vehicle sector, such as those specified, for example, in the ISO 26262 standard or, in particular, by the so-called "Automotive Safety Integrity Level" (ASIL), a safety requirement level for safety-relevant systems in motor vehicles specified by ISO 26262.

[0030] A computing unit according to the invention, e.g. a control unit of a motor vehicle, is configured, in particular in terms of programming, to carry out a method according to the invention.

[0031] The implementation of a method according to the invention in the form of a computer program or computer program product with program code for carrying out all method steps is also advantageous, since this entails particularly low costs, in particular if an executing control unit is also used for other tasks and is therefore already present. Finally, a machine-readable storage medium is provided with a computer program stored thereon, as described above. Suitable storage media or data carriers for providing the computer program are, in particular, magnetic, optical, and electrical memories, such as hard disks, flash memories, EEPROMs, DVDs, and others. Downloading a program via computer networks (Internet, intranet, etc.) is also possible. Such a download can be wired or cable-based or wireless (e.g., via a WLAN network, a 3G, 4G, 5G, or 6G connection, etc.).Further advantages and embodiments of the invention will become apparent from the description and the accompanying drawings.

[0032] The invention is illustrated schematically in the drawing using exemplary embodiments and is described below with reference to the drawing.

[0033] Short description of the drawings

[0034] Figure 1 schematically shows an embodiment of a computing unit according to the invention, which is designed to carry out an embodiment of a method according to the invention.

[0035] Figure 2 schematically shows an embodiment of a method according to the invention as a block diagram.

[0036] Figure 3 schematically shows an embodiment of a method according to the invention as a block diagram.

[0037] Figure 4 schematically shows an embodiment of a method according to the invention as a block diagram.

[0038] Figure 5 schematically shows an embodiment of a method according to the invention as a block diagram.

[0039] Figure 6 schematically shows an embodiment of a method according to the invention as a block diagram.

[0040] Figure 7 schematically shows an embodiment of a method according to the invention as a block diagram.

[0041] Figure 8 schematically shows an embodiment of a method according to the invention as a block diagram. Embodiment(s) of the invention

[0042] Figure 1 schematically shows a computing unit designated 100, which can be embodied, for example, as a system-on-a-chip (SoC). For example, the SoC 100 can be provided for a motor vehicle and integrated into a control unit of the vehicle, for example, to perform safety-critical functions for the safe operation of the vehicle, e.g., in the course of engine control, in the course of driver assistance functions, in the course of autonomous driving, etc.

[0043] To ensure the safety and integrity of the control unit, to execute software at the highest safety level, and to meet safety requirements of the (motor) vehicle sector, in particular according to the ASIL-D safety requirement level of the ISO 26262 standard, the SoC 100 is configured, particularly in terms of programming, to carry out an embodiment of a method according to the invention. During this method, the SoC 100 can be operated in a safe operating mode, which enables safe retrieval of commands. In this way, a functionally safe execution platform 110 ("Safe Island", "Vital Modules", "Safe Backbone", or "Safe Execution Platform") is implemented in the SoC 100.

[0044] For this functionally reliable execution platform 110, or for executing the secure operating mode, a processor unit 111, a cache logic unit 112, and a timer 113 are provided in the example shown. The processor unit 111 can expediently (but not restrictively) be a processor core based on a RISC-V instruction set architecture. This RISC-V processor 111 and the cache logic unit 113 are connected, for example, via RAM and cache memory 121 to an interconnect 120 of the SoC 100 as further elements of the functionally reliable execution platform 110. For example, a flash memory unit 140, e.g., a NAND flash memory, can be connected to the interconnect 120 via an interface 141, and a RAM memory unit 150, e.g., an LPDDR RAM, can be connected via a RAM controller 151.The SoC 100 can further comprise one or more additional processor cores 130 with associated RAM and cache memory 131, which are connected to the connection unit 120. Furthermore, a memory unit 122 as a further element of the reliable execution platform 110 for a startup process (boot flash memory) and a peripheral bus 160 can be connected to the connection unit 120. A plurality of peripheral units can be connected to the peripheral bus 160, e.g., an analog-to-digital converter 161, a serial bus system 162 ("Serial Peripheral Interface", SPI), a unit for direct memory access 163 ("Direct Memory Access", DMA), a timer 164, and another fieldbus system 165, e.g., a Flexray fieldbus. It is understood that fewer or even more peripheral units can be provided, indicated by reference numeral 166.For example, an external monitoring unit 180 for detecting and managing an error or failure of the SoC 100 (also known as a "watchdog") can be connected via the serial bus system 162. Furthermore, the SoC 100 can have an error management unit 170 (also known as an "error management module" or EMM) for managing output error messages.

[0045] In the secure operating mode, the processor 111 calculates and checks check values ​​of read-in instructions in order to ensure the integrity of the instructions from a compiler to the processor core 111, as will be explained below with reference to Figures 2 to 8.

[0046] Figures 2 to 8 each schematically illustrate an embodiment of the method according to the invention as a block diagram. Each of the individual figures 2 to 8 shows a sequence of instructions that can be read and executed by the processor 111.

[0047] These individual instructions are generated, for example, by a compiler during the compilation process of a program code, with a reference check value being calculated for each generated instruction. These instructions can be stored, together with the respective reference check value, for example, in the flash memory unit 140 and copied from there into the RAM memory unit 150 during operation of the SoC 100. In particular, at least one of the instructions, expediently the first or the last of those to be safely executed, is stored together with the reference check value, for example, as an argument of the instruction. Preferably, however, several or all of the instructions are each stored with their reference check value. The individual instructions, together with the respective reference check value, can be read and executed from the RAM memory 150 by the processor 111 during an instruction fetch ("instruction fetch").

[0048] As shown in Figure 2, during a regular operating mode, instructions 202, 204, and 206 are read and executed by processor 111 in a regular manner. During this regular operating mode, no check value is calculated for the read instructions. When an activation instruction 208 is read, processor 111 activates the secure operating mode. From then on, until the secure operating mode is deactivated, processor 111 calculates a current check value from each read instruction and the previous check value.

[0049] After reading the activation command 208, a first check value is calculated, in particular from a first command currently being executed and a predetermined initial check value or a read-in initial check value as the previous check value. For example, the check value calculation can be initialized with a read-in initial check value such that a final value to be calculated later should correspond to a predetermined value, e.g., zero, in an error-free case.

[0050] After activating the secure operating mode, processor 111 reads an instruction 210 and calculates the current check value from this instruction 210 and the initial check value. Processor 111 then reads the next instruction 212 and calculates the current check value from this instruction 212 and the previous check value.

[0051] This instruction 212 is, for example, a subroutine instruction for executing a subroutine. The processor 111 executes the corresponding subroutine or a corresponding program code module. In the course of this, the processor 111 reads the instructions 218, 220, 222, 224, 226, 228, 230, and 232 and calculates the current check value from the respective instruction read in and the respective previous check value. The instruction 232 can, for example, be a return instruction that characterizes the end of the subroutine and instructs the processor 111 to return to the previous instruction sequence.

[0052] Upon return command 232, processor 111 reads in commands 214 and 216 and calculates the current test value for each. Command 216 can, for example, be a jump command to jump to a specific command 234 or its memory address in RAM 150. Processor 111 then reads in this command 234 and calculates the current test value. The next command 236 read in can, for example, again be a subroutine command. Upon reading in this subroutine command 236, processor 111 again reads in the individual commands 218, 220, 222, 224, 226, 228, 230, and 232 of this module and calculates the current test value for each.

[0053] Upon re-reading the return instruction 232, the processor 111 returns to the previous instruction sequence and reads the instructions 238 and 240 and calculates the current test value in each case.

[0054] Command 240, for example, is a deactivation command for deactivating the safe operating mode. Upon reading this deactivation command 240, processor 111 deactivates the safe operating mode. Furthermore, upon reading the deactivation command 240, processor 111 performs a check of the current test value. During this check, it checks whether the current test value calculated from the deactivation command 240 corresponds to the specified value, e.g., zero, as the final value.

[0055] If this final value is not zero, this indicates an error and a predetermined action is taken, e.g., an error message is output, the system is stopped, or the system is placed in a safe state. If, on the other hand, the final value is zero, this indicates that no error is present. The processor 111 then returns to the regular operating mode. In the course of this, the processor 111 reads in the instructions 242 and 244 without calculating a check value. According to one embodiment, a check of the current check value can also be performed during the safe operating mode, as explained below with reference to Figure 3. For example, if the subroutine is large or is compiled from a different source file than the other instructions, a check of the check value when starting this subroutine during the safe operating mode can be expedient.

[0056] As shown in Figure 3, during regular operating mode, processor 111 reads commands 302, 304, and 306 without calculating a check value. The next command 308 read in, for example, is the activation command, after which secure operating mode is activated. As explained above, from now on, processor 111 calculates the current check value from each command read in and initializes the check value calculation with an initial check value upon activation command 306.

[0057] In the secure operating mode, processor 111 first reads instruction 310 and then subroutine instruction 312, after which the subroutine is executed. In this subroutine, processor 111 first reads a check instruction 320, after which processor 111 performs a check of the current check value. In this way, the read subroutine instruction 312 can be checked, in particular immediately after its execution. For this check, processor 111 compares the check value calculated from subroutine instruction 312, for example, with the specified value zero.

[0058] After this check, the processor 111 reads the next instruction 322 and calculates the current check value from this instruction 322 and the previous check value (here zero).

[0059] Processor 111 then reads in instructions 324, 326, 328, 330, 332, and 334 of the subroutine and calculates the current check value for each one. Instruction 334, for example, is a return instruction, whereupon processor 111 returns to the previous instruction sequence and executes instruction 314. This instruction 314 is also, for example, a check instruction, whereupon processor 111 again checks the current check value. In this way, the subroutine or its individual instructions can be checked, particularly immediately after their execution. Following this check, the processor also reinitializes the check value calculation by reading in the next instruction 316 with a new initial check value.

[0060] Processor 111 then reads instruction 318, where this instruction 318 is, for example, a jump instruction, whereupon processor 111 jumps to instruction 336 and reads it. Processor 111 then reads instruction 338, which is, for example, again a subroutine instruction. Processor 111 now reads instruction 320 again, performs a check of the current check value, and reinitializes the check value calculation with instruction 322. Processor 111 then reads the further instructions 324, 326, 328, 330, 332, and 334 of the subroutine again, returns to the previous instruction sequence at return instruction 334, and reads instruction 340. This instruction 340 is also a check instruction, for which processor 111 performs a check of the current check value.

[0061] Processor 111 then reads instructions 342, 344, and 346, with instruction 346 being the deactivation instruction and deactivating the secure operating mode. Following deactivation instruction 346, processor 111 also performs a check of the current check value. Processor 111 then returns to regular operating mode and reads instructions 348 and 350 without calculating a check value.

[0062] According to one embodiment, a check of the current test value can also be performed upon a jump command, as explained below with reference to Figure 4. Since jump commands can in principle also lead to a potentially dangerous destination, it may be expedient to perform a check with a jump.

[0063] In the example of Figure 4, processor 111 is already in secure operating mode and, in the process, reads instructions 402, 404, 406, and 408 and calculates the current check value for each of them. Instruction 408, for example, is a jump instruction to perform an indirect jump to multiple addresses or to several additional instructions 410, 416, and 424.

[0064] Processor 111 then reads these instructions 410, 416, and 424 and calculates the current check value for each of them. In particular, each of these instructions 410, 416, and 424 is a check instruction, after which processor 111 performs a check of the respective current check value. In this way, the read-in jump instruction 408 can be checked immediately after its execution. After each check, processor 111 reads the individual instructions 412, 414, 418, 420, 422, 426, 428, and 430 and calculates the current check value for each of them.

[0065] For example, instruction 408 can also be a subroutine instruction to execute multiple subroutines during an indirect function call. In this case, instructions 410, 412, and 414 characterize a first subroutine, instructions 416, 418, 420, and 422 a second subroutine, and instructions 424, 426, 428, and 430 a third subroutine. Furthermore, in this case, the respective last instructions 414, 422, and 430 of the individual subroutines can each be a return instruction.

[0066] According to one embodiment, a check of the current check value may also be performed upon a branch instruction for executing multiple branches of instructions, as explained below with reference to Figure 5.

[0067] In the example of Figure 5, the processor 111 is already in the secure operating mode, during which the processor 111 reads in the instructions 502, 504 and 506 and calculates the current check value in each case. The instruction 506 is, for example, a branch instruction (e.g., If - then) to read in and execute the instructions 508, 510, 512, 514 and 516 as a first branch and to read in and execute the instructions 520, 522, 524, 526, 528, 530 and 532 as a second branch. The processor 111 then reads in the respective first instruction 508 or 518 of these two branches, whereby these instructions 508 and 518 are each a check instruction, whereupon the processor 111 carries out a check of the respective current check value. The processor 111 then reads the remaining instructions from each of the two branches.

[0068] For example, the last instruction 516 or 532 of each of the two branches is a jump instruction to jump to instruction 534. The two branches thus merge again, and processor 111 reads this instruction 534 as well as the subsequent instructions 536 and 538.

[0069] With the help of jump or branch instructions, instructions in the auxiliary sequence can also be skipped or executed again in the course of a loop, as explained below with reference to Figures 6a and 6b.

[0070] In the example of Figure 6a, processor 111 is already in secure operating mode and reads instructions 602, 604, and 606, calculating the current check value for each. Instruction 606 is a jump instruction to skip instructions 608, 610, and 612 and jump to instruction 614. For example, instruction 608 to be skipped may be a check instruction.

[0071] Upon reading the jump instruction 606, the processor 111 reads instruction 614, which is, for example, a check instruction, and performs the corresponding check. The processor then continues with the instruction flow and reads instruction 616.

[0072] In the example of Figure 6b, processor 111 is also in secure operating mode, reads instructions 650, 652, 654, 656, 658, 660, 662, 664, and 666, and calculates the current check value for each. Instructions 652 and 660, for example, are each verification instructions. Instruction 666 is a jump instruction to return to verification instruction 660 and to read instructions 660, 662, and 664 again. After this reread, processor 111 reads instructions 668, 670, 672, 674, and 676. Instruction 668, for example, is also a verification instruction. For example, instruction 676 is a jump instruction to return to the check instruction 652 and to reread instructions 652 through 674. Processor 111 then continues with instructions 678, 680, and 682, with instruction 678 also being a check instruction.

[0073] According to one embodiment, in such cases, when individual commands are omitted or repeated, the current test value can also be modified by means of a modification command, as explained below with reference to Figures 7a and 7b.

[0074] In the example of Figure 7a, processor 111 is in secure operating mode, reads instructions 702, 704, 706, 708, and 710, and calculates the current check value for each of them, with instruction 710 being a jump instruction to skip instructions 712, 714, and 716 and jump to instruction 718. Instruction 704 is a first modification instruction, by which the current check value is modified as if the individual non-executed instructions 712, 714, and 716 had nevertheless been executed.

[0075] In the example of Figure 7b, processor 111 is also in secure operating mode and reads instructions 750, 752, 754, 756, 758, 760, 762, 764, and 766, calculating the current check value for each of them. Instruction 766 is a jump instruction to return to instruction 760 and read instructions 760, 762, and 764 again. Instruction 758 is a second modification instruction, which modifies the current check value as if the individual re-executed instructions 760, 762, and 764 had been executed only once.

[0076] After rereading instructions 760, 762, and 764, processor 111 reads instructions 768, 770, 772, 774, and 776. Instruction 776 is also a jump instruction to return to instruction 752 and reread instructions 752 through 774. Instruction 770 is also a second modification instruction, which modifies the current test value as if each of the re-executed instructions 752 through 774 had been executed only once. After rereading these instructions 752 through 774, processor 111 proceeds to read the next instructions 778, 780, and 782. For example, instruction 780 is also a second modification instruction to modify the current test value for a subsequent jump instruction.

[0077] By using such first and second modification instructions, the number of verification instructions can be reduced compared to Figures 6a and 6b. It is also conceivable to use a combination of modification and verification instructions, as explained below with reference to Figure 8.

[0078] In the example of Figure 8a, processor 111 is in secure operating mode, reads instructions 802, 804, 806, 808, and 810, and calculates the current check value for each of them. Instruction 810 is a jump instruction to skip instructions 812, 814, and 816 and jump to instruction 818. Instruction 804 is a modify instruction, but does not modify the current check value for the immediately next jump instruction 810. Instructions 812 and 818 can each be a verify instruction.

[0079] In the example of Figure 8b, processor 111 is also in secure operating mode and reads instructions 850, 852, 854, 856, 858, 860, 862, 864, and 866, calculating the current check value for each of them. Instruction 866 is a jump instruction to return to instruction 860 and read instructions 860, 862, and 864 again. Instruction 852, for example, is a check instruction. Instruction 858 is a second modification instruction, which modifies the current check value as if the re-executed instructions 860, 862, and 864 had been executed only once.

[0080] After rereading instructions 860, 862, and 864, processor 111 reads instructions 868, 870, 872, 874, and 876, with instruction 876 being a jump instruction to return to check instruction 852. Processor 111 now rereads instructions 852 through 874 and then continues with instructions 878, 880, and 882.

Claims

Claims 1. A method for operating a computing unit (100) in a secure operating mode, comprising: Reading in an activation command (208, 308) for activating a safe operating mode and activating the safe operating mode in response to the read-in activation command; in the safe operating mode, reading in commands and calculating a current test value from a command currently being executed and a previous test value; in the safe operating mode, checking the current test value at least once.

2. The method of claim 1, further comprising: in the secure operating mode, checking the current check value upon occurrence of a predetermined check event.

3. The method of claim 2, wherein the predetermined verification event comprises one or more of the following verification events: reading in a predetermined verification instruction (314, 320, 340); reading in a jump instruction (318) for executing a jump; Reading in a subroutine instruction (312, 338) to execute a subroutine; Reading a branch instruction (408) to execute multiple branches of instructions.

4. Method according to one of the preceding claims, wherein a predetermined measure is carried out if no check of the current test value has been carried out after a predetermined maximum number of commands have been read in and / or after a predetermined maximum time interval has elapsed.

5. The method according to any one of the preceding claims, further comprising: in the secure operating mode, reading in a deactivation command (240, 346) for deactivating the secure operating mode; Calculate the current check value from the deactivation command and the previous check value; Check the current test value.

6. The method according to any one of the preceding claims, further comprising: after reading in the activation command, calculating a first check value from a first command currently to be executed and a predetermined initial check value or a read-in initial check value as the previous check value.

7. The method according to any one of the preceding claims, further comprising, before activating the secure operating mode: Providing each command to be read in with a reference check value.

8. The method according to any one of the preceding claims, further comprising: in the safer operating mode, if a number of instructions (712, 714, 716) are not executed, reading in a first modification instruction (704) and modifying the respective current check value as if the individual non-executed instructions (712, 714, 716) had been executed; and / or in the safer operating mode, when a number of previously executed instructions (752, 754, 756, 758, 760, 762, 764, 766, 768, 770, 772, 774, 776) are executed again, reading in a second modification instruction (758, 770, 780) and modifying the respective current check value in such a way as if the individual re-executed instructions (752, 754, 756, 758, 760, 762, 764, 766, 768, 770, 772, 774, 776) had been executed only once.

9. A computing unit (100) configured to carry out all method steps of a method according to any one of the preceding claims.

10. A computing unit (100) according to claim 9, comprising a processor unit (111) based on a RISC-V instruction set architecture.

11. A computer program which causes a computing unit (100) to carry out all method steps of a method according to one of claims 1 to 8 when it is executed on the computing unit (100).

12. A machine-readable storage medium having stored thereon a computer program according to claim 11.

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