Panel level packaging structure with fully parallel interconnects

Abstract

The disclosure relates to a package or prepackage (100a, 100b) comprising: a semiconductor die (140) and two contact bond sheets (200, 300) encapsulating the semiconductor die (140). The two contact bond sheets (200, 300) are bonded to each other. Each contact bond sheet comprises a core layer (210, 310) and a bonding layer (220, 320). The core layer comprises a core insulating layer (110a, 130a) and one or more metallic through-connections (110b, 110c, 130b) penetrating the core insulating layer (110a, 130a). The bonding layer comprises an insulating bond layer (120a, 120b) formed on the core insulating layer (110a, 130a) and a metal bond layer (120g, 120c, 120d) formed on the one or more metallic through-connections (110b, 110c, 130b). The metal bond layers are designed to electrically and thermally connect the semiconductor die. The insulating bond layers are bonded to each other to form a homogeneous insulating layer encapsulating the semiconductor die.

Description

[0001] PANEL LEVEL PACKAGING STRUCTURE WITH FULLY PARALLEL INTERCONNECTS

[0002] TECHNICAL FIELD

[0003] The disclosure relates to the field of semiconductor packages and prepackages for embedded chip or component packages (ECP) in power applications, in particular to panel level packaging with parallel chip contact formation.

[0004] BACKGROUND

[0005] Panel level packaging usually comprises three key processes: encapsulation, chip contact formation and the formation of an outer metal interface that suits the function of the package - either as a standard package for SMA (surface mount assembly), or as a prepackage for later embedding into a PCB or power module.

[0006] Most available panel level packaging approaches heavily depend on sequential processes for micro via contact formation by laser drilling, and on the necessary expensive manufacturing chemistry and equipment for via filling. As of today, no low-cost manufacturing method is available, which can be scaled to panel level avoiding several mold steps or expensive via drilling and via filling processes during the final assembly.

[0007] SUMMARY

[0008] This disclosure provides a solution for a low-cost package and manufacturing method which can be scaled to panel level. Low cost in the context of this disclosure shall mean simple manufacturing and parallel processing, e.g., a package that can be manufactured with high through-put at reduced process complexity. The package can be used as a prepackage or as an SMA (surface mount assembly) package.

[0009] The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

[0010] Embodiments of the disclosure are based on a low-cost package structure and manufacturing method that is using parallel processing and can be scaled to panel level. Such structure comprises market available chips with solderable and / or sinterable chip metallization systems. All connection between the die and the package are done in parallel and at the same time, which provides reduced production time because time consuming via drilling (sequential process) and expensive panel plating processes are not required. Instead, contact bond sheets as described below are used to directly make connection to the chip metallization.

[0011] Embodiments of the disclosure presented herein do not rely on Cu finishes for chip contact formation. They can omit die-top or Cu plating processes. Embodiments of the disclosure can be based on sinterable or solderable chip metallization, which has a better availability than the usually customized additional Cu die metallization. Embodiments of the disclosure are fully scalable to panel format. Embodiments of the disclosure exploit the benefits of embedding with respect to power density and reduced parasitics. Embodiments of the disclosure reduce process complexity by omitting via drilling / filling processes and respective ownership costs.

[0012] The solution presented in this disclosure can be applied to a broad range of power conversion equipment, spanning low power up to high power board mounted power (BMP) devices such as for example in ICT, PV applications, automotive on-board charging, or even in high power automotive traction inverters. Typical scenarios are embedding of power semiconductor devices as single devices or half-bridge configuration into the circuit board or any other typical power electronics topology that suits the purpose of the application.

[0013] Cost effective manufacturing of power modules scaled to panel level by using laminate embedding or mold embedding technology options as described hereinafter are also provided.

[0014] In order to describe the disclosure in detail, the following terms and notations will be used.

[0015] ECP Embedded Chip / Component Package or Packaging

[0016] CE Chip Embedding

[0017] LV / MV / HV Low Voltage I Medium Voltage I High Voltage

[0018] PCB Printed Circuit Board

[0019] OSAT Outsourced Assembly and T est

[0020] EMC Epoxy Mold Compound

[0021] MIS Molded Interconnect Substrate

[0022] SMT Surface Mount Technology

[0023] SMA Surface Mount Assembly

[0024] RDL Redistribution Layer BMP Board Mounted Power

[0025] ICT Information and Communication Technology

[0026] PV Photo Voltaic

[0027] Chip embedding (CE) or embedded component packaging (ECP) is a packaging technology that uses PCB manufacturing processes for the embedding or encapsulation of semiconductor die. The result can either be an SMT package which can be soldered onto standard PCBs, or a PCB board which has semiconductor die or components integrated inside. Chip embedding is a panel level packaging process technology. Chip embedding for low voltage devices below 100 V has already become an established package option in the market. Even for voltages up to 650 V embedded discrete devices are available on the market today. However, for higher power electronic packaging, market penetration is currently still low due to limited availability of economically scalable solutions for voltages above 100 V.

[0028] Embedded power packaging in the context of this disclosure understands the embedding of power electronic devices and components into PCBs using chip embedding technology. This is in contrast to conventional electronics assembly and packaging, where packaged components are soldered onto the outer layers of a PCB by means of surface mount technology (SMT), also termed surface mount assembly (SMA). It is also in contrast to conventional power module packaging with framed or molded modules. Embedded power packaging as it is understood here does not relate to embedded systems or embedded power systems.

[0029] Prepackages provide a minimum of packaging function for die protection during manufacturing. It is a semi-finished product, which requires further protective encapsulation in the final product. It can also be seen as a minimalistic package, which does not provide solderable terminals for SMT, but is tailored to be used for chip embedding.

[0030] Mold embedding in this disclosure relates to the encapsulation of semiconductor devices or components into mold compound, and using RDL (redistribution layer) processes from wafer manufacturing or PCB manufacturing to form the terminals. In a wider sense it can also be understood as Fan-out panel level packaging.

[0031] Laminate embedding in this disclosure relates to the encapsulation of semiconductor devices or components into PCB type laminate material and using RDL processes from PCB manufacturing technology. Panel level packaging: All mayor packaging manufacturing process steps are carried out on panel scale with typical dimension up to 18” x 24”. As a contrast, conventional packaging typically uses serial processing modes, where smaller production formats like leadframe stripes are manufactured in lots one after another.

[0032] Inlays in the context of this disclosure are small substrate platelets of arbitrary shape and thickness, made of metal or dielectric layers, which can be placed into the cavities of a core layer, or laminated into a PCB board. Inlays can be placed e. g. by means of pick and place equipment. They can enhance the functions of a substrate, e. g. adding thicker copper for better heat dissipation capability, or adding ceramic inlay substrate for thermal conductive insulation functions.

[0033] B-staged material means that a curable bond material is applied or deposited onto a carrier and stabilized for logistics and transport until it is activated during the bond or curing stage. This allows easier pre-manufacturing of components, and thus complexity reduction and throughput increase in a package assembly line.

[0034] Hybrid bonding in this disclosure means that metallic connections and dielectric connections can share the same layer and are formed simultaneously from their B-stage material of bond layers during one single curing and lamination process step. The process of hybrid bonding can be done using core layers coated with bond material, preform placement and prepreg layup, premanufactured hybrid bond sheets (dual side coated), or premanufactured contact bond sheets (single side coated).

[0035] In this disclosure, a package is disclosed for packaging one or more semiconductor dies and / or electronic components. It understands that the disclosed package can also be used to manufacture pre-packages, which usually excludes functions or features for conventional surface mount technology SMT and only provides a minimum of package functions for one or more specific purposes, which are as follows:

[0036] Die protection against PCB laminate material impurities

[0037] PCB laminate material choice for chip embedding is limited. According to standards Halogen Free PCB material can contain halogen up to 900 ppm. High halogen content can easily catalyze corrosion of chip metallization if in direct contact with the die. Standard PCB materials are not designed for the purpose of chip embedding. Applying a voltage bias to chips embedded in standard PCB material can cause electrochemical migration which leads to leakage current and eventually failed devices by short circuited current paths. If the die or its sensitive area is first encapsulated by a minimal package (or pre-package) which has a lower concentration of contaminants - as for example typical epoxy mold compound (EMC) - active or passive components can still be embedded inside a circuit board using standard PCB materials.

[0038] Increasing the breakdown voltage of embedded modules

[0039] Clearance between different potentials on a die surface are usually minimized and matched to the prevalent material sets (EMC or silicone gel) for encapsulation. As the die become thinner, clearance between die backside electrode and die topside electrode is shrinking and increases the demand for encapsulation material with enhanced isolation properties. Standard PCB material usually has inferior breakdown field strength compared to EMC. Prepackages using EMC with high breakdown field strength can enable embedded power packages for voltages above 100 V.

[0040] Providing a Cu metallization system that is compatible with embedding

[0041] It is often very difficult to find a power die or logic die with appropriate Cu metallization thickness and passivation with sufficient adhesion for chip embedding. This is especially true for modules with one or more different dies from different suppliers. The Main market for semiconductors is still serving wire bond interconnect technology, some suppliers provide front metallization systems for clip soldering. The availability of Cu frontside and back side metallization for chip embedding is still rather low. Prepackages can bridge this gap by providing a copper interface for chip embedding, internally connecting to a standard wirebond AI / AICu or solderable Ag / Ni chip finish.

[0042] Robust embedding interposer for thick copper capable standard PCB processes

[0043] Chip-near copper thickness can be increased and standard PCB processes including mechanical via drilling can be used instead of micro vias. Microvias limit the maximum thickness of the metallization in that layer to 35 to 50 micrometers. The pre-package can increase the clearance between pads, such that no high precision placement / alignment is required. This opens options for cost reduction because no expensive high precision alignment systems or die shift compensation measures are required. The thick Cu close to the die also allows better thermal spreading, better connection to the cooling structures and thus lower thermal resistance which is of particular importance for power electronic systems. Design freedom

[0044] Prepackages allow module and power electronic system providers to use embedding at a higher integration level (e. g. in the system board, or motherboard) without a dedicated chip embedding OSAT. Direct chip embedding requires die attach equipment and high precision capability in a high-level clean environment to handle the chips. In contrast, prepackages could potentially be embedded by a PCB manufacturer in a similar way like for example copper inlays, without special processing or handling requirements.

[0045] Testability

[0046] The qualification of bare die products is usually done with the last electrical tests on wafer level and only optical inspection after dicing of the wafer. All logistics and handling of the unprotected die on the dicing foil, or the die in a blister pack remains a risk that could result in yield loss in the final packaged product. In such scenario, usually the customer (the module manufacturer) has to accept this risk. Prepackages introduce a protected testable intermediate product stage with clear liability in case of a damage.

[0047] In this disclosure the terms “insulation” and “isolation” are used. In the context of the disclosure, both terms mean the same, i.e. , “insulation” means “isolation” and vice versa.

[0048] The novel package design as introduced in this disclosure is a package that comprises contact bond sheets as described in the following.

[0049] According to a first aspect, the disclosure relates to a package for packaging at least one semiconductor die, the package comprising: at least one semiconductor die and two contact bond sheets encapsulating the at least one semiconductor die, the two contact bond sheets being bonded to each other; each contact bond sheet comprising a core layer and a bonding layer, the core layer comprising a core insulating layer and one or more metallic through- connections penetrating the core insulating layer, the bonding layer comprising an insulating bond layer formed on the core insulating layer and a metal bond layer formed on the one or more metallic through-connections; wherein the metal bond layers of the two contact bond sheets are designed to electrically and thermally connect the at least one semiconductor die; and wherein the insulating bond layers of the two contact bond sheets are bonded to each other to form a homogeneous insulating layer encapsulating the at least one semiconductor die. Such a package is fully scalable to panel level. No via drilling / filling process and plating line (meaning that no wet chemical processes are needed, and the production can easily be done in a normal PCB manufacturing line) is necessary in the package assembly line. The package can be manufactured at low-cost, in particular a panel level package or prepackage can be manufactured without the need for Cu chip pad metallization.

[0050] A solderable or sinterable chip metallization on the front side and on the backside of the die may still be required. This can be realized, for example, by typical Ni / Ag based or Ni / Pd, Ni / Pd / Au based chip metallization finishes. Al based metallization systems may also apply, in combination with conductive glue, for lower demanding applications with relaxed reliability requirements.

[0051] Full encapsulation can be implemented for this package in one lamination process step. Low manufacturing complexity can be reached with a robust process. This process can better tolerate alignment deviations.

[0052] The one or more metallic through-connections can have any shape, as e. g. formed by core layer via bars.

[0053] In an exemplary implementation of the package, the package comprises: an insulating lamination connection formed by the homogeneous insulating layer, the insulating lamination connection being configured to laminate the two contact bond sheets face-to-face to each other together with the at least one semiconductor die aligned in between; wherein the one or more metallic through-connections are embedded in the insulating lamination connection.

[0054] The insulating lamination connection forms a stable connection of the two contact bond sheets with the embedded semiconductor die in between. The complexity of the process can be reduced since all necessary elements (metal bonding and insulation bonding) are included in the contact bond sheet and no separate process steps like masking, layering, etching, etc. are required in the assembly line.

[0055] In an exemplary implementation of the package, the at least one semiconductor die comprises a first main face and a second main face opposing the first main face; wherein the at least one semiconductor die comprises at least one electrical pad at the first main face and optionally at least one electrical pad or thermal pad at the second main face; and wherein the metal bond layers of the two contact bond sheets are bonded to the electrical pads of the at least one semiconductor die.

[0056] Some GaN dies or logical dies I driver dies may have only a thermal pad at the bottom face. A flip-chip configuration with the bottom side of the die facing upwards is also included by this embodiment. The first main face can be either the top face or the bottom face when the die is flip-chip mounted - or vice versa.

[0057] In an exemplary implementation of the package, the package comprises: a metal connection bonding the metal bond layers of the two contact bond sheets to the electrical pads of the at least one semiconductor die; wherein the metal connection is one or any combination of the following: a sintered metal connection, a soldered metal connection, a diffusion soldered metal connection, a metal connection connected by conductive glue resulting in a non-remelting reliable connection or a nano-structured metal connection.

[0058] A nano-structured metal connection as described in this disclosure is a metallic connection in which one or more metal surfaces with metallic nano hair or nano lawn, nano fibers, filaments, wires, etc. are brought together with pressure and temperature. After a short time, the nano structures, e.g., nano hair, nano lawn, nano fibers, filaments, wires, etc. are sintered together due to diffusion at an atomic level. The result is a sinter-like connection except, the starting point was not a paste with nano and micro scale particles, but a fibrous structure that is for example galvanically grown on the initial surface(es).

[0059] Such formation of a metal bond connection can omit die-top or Cu plating processes, thereby reducing processing complexity.

[0060] In an exemplary implementation of the package, parts of the metal bond layers of the two contact bond sheets are bonded to each other to form a vertical metal connection between the two contact bond sheets, the vertical metal connection forming a non-remelting metal joint.

[0061] All metal bond connections as presented in this disclosure are forming a non-remelting metal joint. In particular, not just direct face-to-face contact bond sheet connections but also contact bond sheet to die pad connections are forming such non-remelting metal joint.

[0062] The formation of a vertical metal connection between the two contact bond sheets allows electrical connections between front side die pads and the backside metallization of the die. The idea behind this is, that for an SMT package, usually all electrical connections need to be routed inside the package to one side, the solder interface. If the die has electrical contacts on both sides, at least one connection has to change the side, going from one contact bond sheet to the other.

[0063] In an exemplary implementation of the package, the non-remelting metal joint interconnects at least parts of the metallic through-connections of the core layers of the two contact bond sheets. Such non-remelting metal joint provides a robust and stable metal connection.

[0064] In an exemplary implementation of the package, the non-remelting metal joint forms a via through the homogeneous insulating layer. Thus, no separate via processing steps are necessary for forming such vias.

[0065] In an exemplary implementation of the package, the package comprises: a pad finish applied to the one or more metallic through-connections to form external pads for an external electrical connection of the at least one semiconductor die. This allows to use the package as leadless SMT (surface mount) package, where all electrical connections of the die need to be connected to one side of the package, the solder side, e.g., as described below with respect to Fig. 3.

[0066] In an exemplary implementation of the package, the one or more metallic through-connections form one of the following structures in the core layer: a non-split structure, a partially split structure, a sectioned or non-sectioned separate contact islands structure, a non-structured copper foil in one of the two contact bond sheets. This provides flexible structuring of the core layer with sufficient mechanical strength of the large area metal through connections.

[0067] In an exemplary implementation of the package, the core layer of one of the contact bond sheets comprises a substrate inlay comprising an electrically insulating and thermally conductive layer in between two electrically conductive layers, the layer stack penetrating the core insulating layer.

[0068] An area of such a substrate inlay may be smaller than the core layer and smaller than the package outline, respectively. This allows to implement packages or leadless packages with thermally conductive integrated isolation by laminating the contact bond sheet containing the substrate inlay to a bond sheet that has a semiconductor die attached to it or by attaching a semiconductor die on top of the substrate inlay of that bond sheet. In an exemplary implementation of the package, the package comprises: at least two semiconductor dies, the at least two semiconductor dies forming one or more of the following or other typical power electronic switching configurations: an electrical half-bridge configuration, a parallel die configuration, a common source configuration, a common drain configuration or other typical power electronic topologies for power conversion. Typical power electronic switching configurations can be the above defined configurations or other configurations as for example half-bridge parallel configuration, electrical full-bridge configuration, single leg configuration, half-bridge type II configuration, etc.

[0069] In an exemplary implementation of the package, the at least two semiconductor dies are arranged side-by-side within the two bonded contact bond sheets. By such arrangement, electrical connection paths between the at least two semiconductor dies can be reduced as compared to single die packages that are connected by soldering onto or by embedding into the PCB.

[0070] In an exemplary implementation of the package, the package comprises at least one second semiconductor die and a third contact bond sheet encapsulating the at least one second semiconductor die, the third contact bond sheet being bonded to each of the two contact bond sheets. This allows manufacturing a multi-layer package reducing the package footprint in a 3D stacked die configuration.

[0071] In an exemplary implementation of the package, at least part of the at least one second semiconductor die is facing the at least one semiconductor die within the three bonded contact bond sheets. The semiconductor die may be stacked with respect to each other. They may be fully overlapping or partially overlapping within the three bonded contact bond sheets, for example.

[0072] In an exemplary implementation of the package, the at least one semiconductor die and the at least one second semiconductor die are forming one of the following configurations: an electrical half-bridge configuration, a parallel die configuration, a common source configuration, a common drain configuration. This allows flexible designs to be implemented by such package.

[0073] In an exemplary implementation of the package, parts of the metal bond layers of the third contact bond sheet are bonded to respective metal bond layers of one or both of the two contact bond sheets to form one or more embedded interconnect traces for an external electrical connection.

[0074] By omitting the internal connection, the package footprint can be reduced and the package function is minimized to a prepackage. In that case, the inner connections are buried and can be connected by means of mechanically drilled vias during the chip embedding process as shown in Figure 8, for example. In order to be accessible, the buried inner connection pads may not intercept with any projected metal layer on the outbound side of the inner layer to be connected.

[0075] The number of contact bond sheets laminated together is only limited by thermal requirements or cooling needs. It can be, for example, more than 3 with, for example, more than 2 active dies above each other.

[0076] BRIEF DESCRIPTION OF THE DRAWINGS

[0077] Further embodiments of the disclosure will be described with respect to the following figures, in which:

[0078] Figure 1a shows an SMT package 100b comprising two contact bond sheets 200, 300 having internal inter-sheet connections that lead all electrical connections to one side according to an embodiment;

[0079] Figure 1 b shows a package 100a comprising two contact bond sheets 200, 300 having electrical contact terminals on both main faces, tailored for embedding into PCBs providing a minimum of prepackage footprint according to an embodiment;

[0080] Figure 2 shows process steps and structure of a package 100a and an SMT package 100b according to an embodiment;

[0081] Figure 3 shows a product 300a according to an embodiment with embedded package 100a and attached SMT package 100b as shown in Figure 2;

[0082] Figure 4 shows different options for contact structures for a package 100a according to the disclosure, it understands that these contact structures can be adapted for SMT package functions likewise; Figure 5 shows a manufacturing process 500 for contact bond sheets with sectioned via bars according to a first option;

[0083] Figure 6 shows a manufacturing process 600 for contact bond sheets with isolating substrate inlays according to a second option;

[0084] Figure 7 shows exemplary process steps for manufacturing a halfbridge side-by-side package 700 and a PCB section or module product 710 embedding the package 700 according to an embodiment;

[0085] Figure 8 shows exemplary process steps for manufacturing a stacked die halfbridge prepackage 810 with buried SW terminal and a product 800 embedding the prepackage 810 using mechanically drilled vias according to an embodiment; and

[0086] Figure 9 shows exemplary process steps for manufacturing a stacked die halfbridge prepackage or SMT package 910 with exposed SW terminal and a product 900 embedding the prepackage or SMT package 910 using laser microvias according to an embodiment.

[0087] DETAILED DESCRIPTION OF EMBODIMENTS

[0088] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific aspects in which the disclosure may be practiced. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the disclosure is defined by the appended claims.

[0089] It is understood that comments made in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise. Figure 1a shows an SMT package 100b comprising two contact bond sheets 200, 300 having internal inter-sheet connections that lead all electrical connections to one side according to an embodiment. The SMT package 100b is a package with an SMT finish as described below.

[0090] The SMT package 100b comprises at least one semiconductor die 140 and two contact bond sheets 200, 300 encapsulating the at least one semiconductor die 140. The two contact bond sheets 200, 300 are bonded to each other.

[0091] The contact bond sheets 200, 300 each comprise a core layer 210, 310 and a bonding layer 220, 320, the core layer 210, 310 comprising a core insulating layer 110a, 130a and one or more metallic through-connections 110b, 110c, 130b penetrating the core insulating layer 110a, 130a, the bonding layer 220, 320 comprising an insulating bond layer 120a, 120b formed on the core insulating layer 110a, 130a and a metal bond layer 120g, 120c, 120d formed on the one or more metallic through-connections 110b, 110c, 130b.

[0092] The metal bond layers 120g, 120c, 120d of the two contact bond sheets 200, 300 are designed to electrically connect the at least one semiconductor die 140. The insulating bond layers 120a, 120b of the two contact bond sheets 200, 300 are bonded to each other to form a homogeneous insulating layer 120a, 120b encapsulating the at least one semiconductor die 140.

[0093] For this SMT package or package 100b, respectively, parts of the metal bond layers 120e, 120f of the two contact bond sheets 200, 300 are bonded to each other to form a vertical metal connection 120e, 120f between the two contact bond sheets 200, 300 as shown in Figure 1a. This vertical metal connection 120e, 120f forms a non-remelting metal joint 120e, 120f.

[0094] The formation of such a vertical metal connection 120e, 120f between the two contact bond sheets 200, 300 allows electrical connections between front side die pads and the backside metallization of the die.

[0095] The non-remelting metal joint 120e, 120f interconnects at least parts of the metallic through- connections 110d, 130b of the core layers 210, 310 of the two contact bond sheets 200, 300 as shown in Figure 1a.

[0096] The non-remelting metal joint 120e, 120f shown in Figure 1a may form a via through the homogeneous insulating layer 120a, 120b. The package 100b comprises a pad finish 150a, 150b, 150c, 150d applied onto the outer surface of the one or more metallic through-connections 110b, 110c, 110d, 130b to form external pads for an external electrical connection of the at least one semiconductor die 140.

[0097] This allows to use the package 100b as a leadless SMT (surface mount) package, where all electrical connections of the die need to be connected to one side of the package, the solder side, e.g., as described below with respect to in Fig. 3.

[0098] This disclosure inter alia describes four specific embodiments, with structural and processing options, that can be applied to each of these four embodiments:

[0099] Embodiment 1 : Single device package or prepackage according to Figures 2 and 3;

[0100] Embodiment 2: Halfbridge package side-by-side according to Figure 7;

[0101] Embodiment 3: Halfbridge package stacked with buried contacts according to Figure 8;

[0102] Embodiment 4: Halfbridge package stacked with exposed contacts according to Figure 9.

[0103] Options for contact structures that apply to all embodiments are shown in Figure 4 are the following:

[0104] Option A: Non-split;

[0105] Option B: Partially split, connected, for stress reduction (chocolate bar design);

[0106] Option C: Separated contact islands, for stress reduction;

[0107] Option D: Non-sectioned separated contact islands.

[0108] Options for contact bond sheets that apply to all embodiments are shown in Figures 5 and 6:

[0109] Option i): With via bars (vertical electrical / thermal conduction);

[0110] Option ii): With insulating substrate inlays (vertical isolation / thermal conduction).

[0111] Figure 1 b shows a package or prepackage 100a comprising two contact bond sheets 200, 300 having electrical contact terminals on both main faces, tailored for embedding into PCBs providing a minimum of prepackage footprint according to an embodiment.

[0112] The package or prepackage 100a shown here in Figure 1 b and described in the following is a package option with reduced protection function tailored for embedding with added benefit for this type of technology. The package 100a comprises at least one semiconductor die 140 and two contact bond sheets 200, 300 encapsulating the at least one semiconductor die 140. The two contact bond sheets 200, 300 are bonded to each other.

[0113] Each contact bond sheet 200, 300 comprises a core layer 210, 310 and a bonding layer 220, 320. The core layer 210, 310 comprises a core insulating layer 110a, 130a and one or more metallic through-connections 110b, 110c, 130b penetrating the core insulating layer 110a, 130a. The bonding layer 220, 320 comprises an insulating bond layer 120a, 120b formed on the core insulating layer 110a, 130a and a metal bond layer 120g, 120c, 120d formed on the one or more metallic through-connections 110b, 110c, 130b.

[0114] The metal bond layers 120g, 120c, 120d of the two contact bond sheets 200, 300 are designed to electrically and thermally connect the at least one semiconductor die 140.

[0115] The insulating bond layers 120a, 120b of the two contact bond sheets 200, 300 are bonded to each other to form a homogeneous insulating layer 120a, 120b encapsulating the at least one semiconductor die 140.

[0116] Such package 100a allows full scalability to panel level; no via drilling / filling process is necessary in the assembly line, low-cost manufacturing; a panel level package can be provided without the need for Cu pad metallization. However, a solderable or sinterable die metallization at the front side and at the backside of the die is still required. This can be for example typical Ni / Ag based or Ni / Pd, Ni / Pd / Au based chip metallization finishes. Al based metallization systems may also apply in combination with conductive glue for lower demanding applications with relaxed reliability requirements. Further advantages are full encapsulation in one lamination process step; low manufacturing complexity; robust process, and better tolerance to alignment deviations.

[0117] The one or more metallic through-connections 110b, 110c, 130b can have any shape, as e. g. formed by core layer.

[0118] The package 100a may comprise an insulating lamination connection 120a, 120b formed by the homogeneous insulating layer 120a, 120b. This insulating lamination connection 120a, 120b can be configured to laminate the two contact bond sheets 200, 300 face-to-face to each other together with the at least one semiconductor die 140 aligned in between. The one or more metallic through-connections 110b, 110c, 130b can be embedded in the insulating lamination connection.

[0119] The insulating lamination connection forms a stable connection of the two contact bond sheets with the embedded semiconductor die in between. The complexity of the process can be reduced since all necessary elements (metal bonding and insulation bonding) are included in the contact bond sheet and no separate process steps like masking, layering, etching, plating, etc. are required.

[0120] The at least one semiconductor die 140 comprises a first main face and a second main face opposing the first main face. The at least one semiconductor die 140 may comprise at least one electrical pad at the first main face and optionally at least one electrical pad or thermal pad at the second main face. The metal bond layers 120g, 120c, 120d of the two contact bond sheets 200, 300 may be bonded to the electrical pads of the at least one semiconductor die 140.

[0121] Some GaN dies or logical dies I driver dies, for example, and power components with lateral current flow may have only a thermal pad at the bottom face. A flip-chip configuration with the bottom side of the die facing upwards is also included by this embodiment. The first main face can be either the top face or the bottom face when the die is flip-chip mounted - or vice versa.

[0122] The package 100a may comprise a metal connection bonding the metal bond layers 120g, 120c, 120d of the two contact bond sheets 200, 300 to the electrical pads of the at least one semiconductor die 140. The metal connection can be one or any combination of the following: a sintered metal connection, a soldered metal connection, a diffusion soldered metal connection, a metal connection connected by conductive glue or a nano-structured metal connection.

[0123] The package 100a implements a low-cost package structure which can be scaled to panel level. Such structure comprises market available solderable / sinterable chip metallization systems. The package 100a can be provided at reduced production effort without via drilling / plating processes.

[0124] The contact bond sheets 200, 300 are used to directly make connection to the chip metallization. These contact bond sheets 200, 300 can be pre-manufactured. The contact bond sheets 200, 300 can be b-staged with polymer glue layer and a bond metal layer on one side only as shown in Fig. 1a, for example.

[0125] The contact bond sheets 200, 300 may have a sectioned through-connection structure as shown in Figure 1a. They can be manufactured by a 2-step plating process, for example, e.g., based on laminate substrates or molded interconnect substrates.

[0126] The main idea is that two contact bond sheets 200, 300 are hybrid-bonded together with the die 140 sandwiched in between, where the die 140 have a solderable / sinterable metal system as shown in the bottom part of Figure 1a.

[0127] The structure can tolerate misalignment across the pad outline, as long as no short circuit results from it. In case of microvia contacts, the laser drilling would destroy the misaligned die.

[0128] The contact process does not require any via-drilling or filling. This way the assembly process for the package can be kept lean, without the need for expensive via drilling, wet chemical plating and etching process equipment.

[0129] By using three or more contact bond sheets, 3D SMT packages or pre-packages with stacked dies can be provided.

[0130] Figure 2 shows process steps and structure of a package 100a and an SMT package 100b according to an embodiment and Figure 3 shows a product 300a according to an embodiment with embedded package 100a and attached SMT package 100b as shown in Figure 2.

[0131] The assembly method is based on laminate contact bond sheets, e.g. contact bond sheets 200, 300 as described above with respect to Figures 1a and 1 b.

[0132] The assembly method starts with the provision of the sheets 200, 300, which optionally can also comprise a mold sheet or molded interconnect substrate sheet with the bond materials readily applied in a pre-dried stage (see Figure 2, first and second steps). The character “B” denotes the bottom contact bond sheet 300 and character “T” denotes the top contact bond sheet 200. The sheets 200, 300 can be scaled up to panel format for best economic scaling and parallel processing of several thousands of packaged dies. In the third step, the die 140 are attached to the bottom contact bond sheet 300 by means of standard high-speed pick and place equipment. In order to keep the die 140 in place, an inert sticking fluid can be applied by means of dispensing or jetting before placing the die 140. Alternatively, the pre-dried (b-staged) bond material can be activated by means of heat and the die 140 can be tacked to the sheet 300.

[0133] The die 140 need to have a bondable surface which is compatible to the hybrid bonding mechanism (e. g. sinterable or solderable frontside and / or back side finish). A thick copper finish of the die 140 can also be used, but is not required, since the contact is formed by hybrid bonding without any via drilling and chemical or electrochemical filling of the same.

[0134] After that, in a fourth step, top 200 and bottom 300 sheets are layed-up and aligned using standard lamination tools, and laminated together thus bonding the conductive areas of the sheets 200, 300 to the die 140 and the non-conductive areas of the sheets 200, 300 together in a face-to-face manner.

[0135] As a result, the semiconductor die 140 or components are sandwiched between the two sheets 200, 300 and entirely encapsulated by non-conductive material. The electrical pads on the front side and at the back side of the die 140 are directly connected to the outer surface.

[0136] Then, the panel is separated into individual packages or prepackages 100a, 100b (see bottom pictures in Figure 2) by means of mechanical sawing (dicing), milling, a plasma process or other typical package separation processes. Optionally, the outer metallization can be coated with a solderable or sinterable finish prior to the separation into individual packages, in order to prepare the terminals for the following assembly / encapsulation processes.

[0137] The packages (e.g., SMT packages 100b or prepackages 100a) can then be further encapsulated by a later laminate chip embedding process (see Figure 3) or panel mold embedding process. Alternatively, the resulting packages (e.g., SMT packages 100b or prepackages 100a) can be used for SMT mounting in a conventional SMT line. Figure 3 shows the product or device 300a in which the package 100a is embedded and the SMT package 100b is attached to its top surface.

[0138] Figure 4 shows different options for contact structures for a package 100a according to the disclosure. With respect to the package 100a, 100b, described above, the one or more metallic through- connections 110b, 110c, 130b may form one of the following structures in the core layer 210, 310: a non-split structure 410 (Option A), a partially split structure 420 (Option B), a sectioned 430 (Option C) or non-sectioned 440 (Option D) separate contact islands structure, a nonstructured copper foil 450 (Option E) on non-structured metal foil or metal pad.

[0139] These options are shown as an example for embodiment 1 described above. These options can also be applied to the other embodiments.

[0140] Option A shows non-split large area contacts to the die top and the die bottom metallization (see Figure 4A). It provides best electrical and thermal performance, but could result in reliability issues due to stress caused by the large contact area and GTE mismatch between the metal, the die and the dielectric material. The via bars or molded interconnect islands are sectioned, in order to provide mechanical anchoring and increased adhesion. This design is intended to prevent the metal bars / islands to separate from the dielectric matrix in thin sheets.

[0141] In option B the large area contacts are partially split into smaller pads which are still connected with each other (chocolate bar design, see Figure 4B). This structure provides compliance to reduce thermo-mechanical stress. It can further increase anchoring and adhesion within the dielectric matrix, replacing a minimum of conductive material (conductive cross section, thermal mass). The chocolate bar design can provide a minimum impact to thermal / electrical contact properties with effective heat spreading.

[0142] Option C partitions the area contacts into separated contact islands for further thermomechanical stress reduction (see Figure 4C). More conductive material is replaced by dielectric material and the circumference of the contacts per area is increased, which can provide a higher mechanical stability and flexibility of the package 100a. However, the electrical and thermal contact performance is expected to be lower for this option.

[0143] In option D the area contacts are separated into non-sectioned contact islands (Figure 4D): Non-sectioned contact islands can provide lower complexity (lower cost), but also lower adhesion of Cu vs. Laminate, which could limit the maximum size of the islands.

[0144] According to option E (Figure 4e), in single die and in some multi-die applications (e.g., paralleled power dies) the bottom sheet [B] (see Figure 2) which connects to the drain (or collector) of a MOSFET / IGBT can also be replaced with non-structured Cu foil. Option E can present a significant complexity reduction and thus a cost reduction.

[0145] Figure 5 shows a manufacturing process 500 for contact bond sheets with sectioned via bars according to a first option.

[0146] In particular, Figures 5 and 6 illustrate two options for pre-manufacturing of the contact bond sheets 200, 300 described above. The options can be applied to all embodiments. Both described options for contact bond sheet manufacturing can either be based on laminate core layer substrates with via bars or molded interconnect substrates. Figures 5 and 6 show the laminate core layer process as an example, but the disclosure does not exclude the molded interconnect substrate (MIS) based contact bond sheets.

[0147] Figure 5 shows a manufacturing process 500 for contact bond sheets 200, 300 with sectioned via bars for vertical electrical / thermal conduction and heat spreading. Application of bond materials in step 10 (510) is shown for one side only, but can also be for both sides, as needed for some of the embodiments.

[0148] The manufacturing process 500 starts with a first step 501 “carrier provision” in which a temporary carrier is provided. In a second step 502 “first photo resist patterning”, a first photo resist patterning is applied on the carrier. In a third step 503 “first Cu pattern plating”, a first Cu pattern is plated. In a fourth step 504 “second photo resist patterning”, a second photo resist patterning is applied on the carrier, the second photoresist pattern having smaller resist openings compared to the first photo resist pattern. In a fifth step 505 “second Cu pattern plating”, a second Cu pattern is plated. In a sixth step 506 “Resist strip & seed etch”, the photo resist is removed and the seed layer is etched using appropriate chemical processes. In a seventh step 507 “Lamination or molding”, a lamination or molding layer is applied. In an eighth step 508 “Grinding or milling”, grinding or milling is performed on the top surface in order to expose the plated metal pattern. In a ninth step 509 “Carrier release”, the carrier is released. In a tenth step 510 “Apply hybrid bond materials or sinter paste, etc.”, the hybrid bond materials or sinter paste or other suitable materials are applied to the top surface.

[0149] Figure 6 shows a manufacturing process 600 for contact bond sheets with isolating substrate inlays according to a second option. In particular, Figure 6 shows the manufacturing process 600 for contact bond sheets with isolating substrate inlays for vertical isolation and thermal conduction. Application of bond materials in step 610 is shown for one side only, but can also be for both sides, as needed for some of the embodiments.

[0150] The manufacturing process 600 starts with a first step 601 “carrier provision” in which a temporary carrier is provided. In a second step 602 “first photo resist patterning”, a first photo resist patterning is applied on the carrier. In a third step 603 “first Cu pattern plating”, a first Cu pattern is plated. In a fourth step 604 “second photo resist patterning”, a second photo resist patterning is applied on the carrier, the second photoresist pattern having smaller resist openings compared to the first photo resist pattern. In a fifth step 605 “second Cu pattern plating”, a second Cu pattern is plated. In a sixth step 606 “Resist strip & seed etch; isolated substrate attach”, the photo resist is removed, the seed layer is etched using appropriate chemical processes, and a layer stack 610 representing the isolating substrate inlay is attached to the top surface. In a seventh step 607 “Lamination or molding”, a lamination or molding layer is applied. In an eighth step 608 “Grinding or milling”, grinding or milling is performed on the top surface in order to expose the plated metal pattern and the top metal layer of the isolating substrate. In a ninth step 609 “Carrier release”, the carrier is released. In a tenth step 620 “Apply hybrid bond materials or sinter paste, etc.”, the hybrid bond materials or sinter paste or other suitable materials are applied to the top surface and in particular onto the top surface of the layer stack 610

[0151] By this process 600, a contact bond sheet 200, 300 is manufactured for which the core layer 210, 310 of one of the contact bond sheets 200, 300 may comprise a substrate inlay 610 comprising an electrically insulating and thermally conductive layer 611 in between two electrically conductive layers 612, 613. This layer stack 610 may penetrate the core insulating layer 130a as shown in Figure 6, last step 610.

[0152] An area of such a substrate inlay 610 is smaller than the core layer and smaller than the package outline, respectively. This allows to implement packages or leadless packages with thermally conductive integrated electrical isolation by laminating the contact bond sheet 200, 300 containing the substrate inlay to a bond sheet that has a semiconductor die 140 attached to it or by attaching a semiconductor die 140 on top of the substrate inlay 610 of that bond sheet. Figure 7 shows exemplary process steps for manufacturing a halfbridge side-by-side package 700 and a PCB section or module product 710 embedding the package 700 according to an embodiment.

[0153] A first process step 701 is bottom sheet [B] 300 provision with 1 -sided b-stage hybrid coating 320. A second process step 702 is top sheet [T] 200 provision with 1 -sided b-stage hybrid coating 220. A third process step 703 is die 140, 160 and spacer 170 tacking onto bottom sheet 300. A fourth process step 704 is lay-up and lamination. A fifth process step 705 is separation by which the halfbridge side-by-side package 700 is created which can be embedded in the PCB section or module product 710.

[0154] The halfbridge side-by-side package 700 is interconnected with top-side metal islands structured as clips as shown in Figure 7. The resulting PCB section or module product 710 can also be SMT soldered after applying solderable pad finish to the external contacts.

[0155] The halfbridge side-by-side package 700 comprises at least two semiconductor dies 140, 160 as shown in Figure 7. These at least two semiconductor dies 140, 160 are forming an electrical half-bridge configuration.

[0156] The metal connection between opposing faces of the contact bond sheets 200, 300, with the electrical connection changing from one side of the package to the other side of the package comprises a spacer 170, the spacer 170 compensating any possible height difference between the surface of the metal through connection and the die surface. This can be necessary in cases where the metal bond layer cannot provide sufficient material to compensate this height difference.

[0157] Other configurations can be implemented as well, for example one or more of the following or other typical power electronic switching configurations: a parallel die configuration, a common source configuration, a common drain configuration.

[0158] Typical power electronic switching configurations can be the above defined configurations or other configurations as for example half-bridge parallel configuration, electrical full-bridge configuration, single leg configuration, half-bridge type II configuration, etc.

[0159] As shown in Figure 7, the at least two semiconductor dies 140, 160 may be arranged side-by- side within the two bonded contact bond sheets 200, 300. In addition to halfbridge configuration such design can also be used to connect two or several power dies in parallel inside one package.

[0160] Figure 8 shows exemplary process steps for manufacturing a stacked die halfbridge prepackage 810 with buried SW terminal and a product 800 embedding the prepackage 810 according to an embodiment.

[0161] A first process step 801 is bottom sheet [B] 300 provision with 1 -sided b-stage hybrid coating 320. A second process step 802 is inter sheet [I] 400 provision with 2-sided b-stage hybrid coating. A third process step 803 is top sheet [T] 200 provision with 1 -sided b-stage hybrid coating. A fourth process step 804 is die 140 tacking onto bottom sheet 300. A fifth process step 805 is die tacking onto inter sheet 400. A sixth process step 806 is lay-up and lamination. A seventh process step 807 is separation by which the stacked die halfbridge package 801 with buried SW terminal is created which can be embedded in the SMT package 800.

[0162] In this embodiment, a stacked die halfbridge package 810 with buried SW terminal is provided, using 3 contact bond sheets: 2x 1-sided b-staged; 1x 2-sided b-staged.

[0163] In this embodiment, the low side gate contact (G_LS) and the SW terminal are buried and can be electrically connected to the next RDL level after embedding of the package by mechanical drilling & plating.

[0164] The option of insulated contact bond sheet may require structural modifications of this embodiment in order to accommodate further contact terminals, with free projection area to the top side.

[0165] This prepackage 810 comprises at least one second semiconductor die 160 and a third contact bond sheet 400 encapsulating the at least one second semiconductor die 160. The third contact bond sheet 400 may be bonded to each of the two contact bond sheets 200, 300 as shown in Figure 8.

[0166] In this prepackage 810, at least part of the at least one second semiconductor die 160 may be facing the at least one semiconductor die 140 within the three bonded contact bond sheets 200, 300, 400. The semiconductor dies may be stacked with respect to each other. They may be fully overlapping or partially overlapping within the three bonded contact bond sheets 200, 300, 400, for example.

[0167] The at least one semiconductor die 140 and the at least one second semiconductor die 160 may form one of the following configurations: an electrical half-bridge configuration, a parallel die configuration, a common source configuration, a common drain configuration.

[0168] One or more vias 820 may be formed for an external electrical connection of the one or more embedded interconnect traces. These vias 820 shown in Figure 8 are not part of the prepackage 810. The frontside electrical connections of the lower die can be buried / embedded within the package. The mechanically drilled vias 820 can be drilled from outside of the PCB to the buried / embedded interconnect trace 170b after embedding the package. Beside the mechanically drilled vias 820, the package or product 800 may include microvias 821.

[0169] Figure 9 shows exemplary process steps for manufacturing a stacked die halfbridge prepackage 910 with exposed SW terminal and a product 900 embedding the pre-package 910 according to an embodiment.

[0170] A first process step 901 is bottom sheet [B] 300 provision with 1 -sided b-stage hybrid coating 320. A second process step 902 is inter sheet [I] 400 provision with 2-sided b-stage hybrid coating. A third process step 903 is top sheet [T] 200 provision with 1 -sided b-stage hybrid coating. A fourth process step 904 is die 140 tacking onto bottom sheet 300. A fifth process step 905 is die tacking onto inter sheet 400. A sixth process step 906 is lay-up and lamination. A seventh process step 907 is separation by which the stacked die halfbridge package 901 with exposed SW terminal is created which can be embedded in the SMT package 900.

[0171] In this embodiment, a stacked die halfbridge prepackage 910 with exposed SW terminal is provided, using 3 contact bond sheets: 2x 1 -sided b-staged; 1x 2-sided b-staged.

[0172] In this embodiment the contact bond sheets 200, 300, 400 may need a 2-stage metal bond b- staging process for the interlayer RDL vertical connection that allows for height compensation of the dies 140, 160. For embedding no mechanically drilled blind vias are needed, because the SW terminal is not buried. Embedding can be done with standard microvia drilling and filling. The resulting package can also be SMT soldered. The option of insulated contact bond sheet can require structural modifications of this embodiment in order to accommodate further contact terminals, with free projection area to the top side.

[0173] In the product 900, parts of the metal bond layers 120e, 120f of the third contact bond sheet 400 may be bonded to respective metal bond layers 120e, 120f of one or both of the two contact bond sheets 200, 300 to form one or more embedded interconnect traces 170b for an external electrical connection as shown in Figure 9.

[0174] This structure allows to use the stacked package also as an SMT package which can be soldered onto a PCB board. In that case, a solderable outer pad finish may be required.

[0175] The number of bond layers laminated together is only limited by thermal requirements or cooling needs. It can be, for example, more than 3 with, for example, more than 2 active dies above each other.

[0176] The option of insulated contact bond sheet can require structural modifications of this embodiment in order to accommodate further contact terminals, with free projection area to the top side.

[0177] While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

[0178] Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and / or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

[0179] Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

[0180] Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the disclosure beyond those described herein. While the disclosure has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the disclosure. It is therefore to be understood that within the scope of the appended claims and their equivalents, the disclosure may be practiced otherwise than as specifically described herein.

Claims

CLAIMS1. A package (100a) for packaging at least one semiconductor die (140), the package (100a) comprising: at least one semiconductor die (140) and two contact bond sheets (200, 300) encapsulating the at least one semiconductor die (140), the two contact bond sheets (200, 300) being bonded to each other; each contact bond sheet (200, 300) comprising a core layer (210, 310) and a bonding layer (220, 320), the core layer (210, 310) comprising a core insulating layer (110a, 130a) and one or more metallic through-connections (110b, 110c, 130b) penetrating the core insulating layer (110a, 130a), the bonding layer (220, 320) comprising an insulating bond layer (120a, 120b) formed on the core insulating layer (110a, 130a) and a metal bond layer (120g, 120c, 120d) formed on the one or more metallic through- connections (110b, 110c, 130b); wherein the metal bond layers (120g, 120c, 120d) of the two contact bond sheets (200, 300) are designed to electrically and thermally connect the at least one semiconductor die (140); and wherein the insulating bond layers (120a, 120b) of the two contact bond sheets (200, 300) are bonded to each other to form a homogeneous insulating layer (120a, 120b) encapsulating the at least one semiconductor die (140).

2. The package (100a) of claim 1 , comprising: an insulating lamination connection (120a, 120b) formed by the homogeneous insulating layer (120a, 120b), the insulating lamination connection (120a, 120b) being configured to laminate the two contact bond sheets (200, 300) face-to-face to each other together with the at least one semiconductor die (140) aligned in between; wherein the one or more metallic through-connections (110b, 110c, 130b) are embedded in the insulating lamination connection.

3. The package (100a) of claim 1 or 2, wherein the at least one semiconductor die (140) comprises a first main face and a second main face opposing the first main face;wherein the at least one semiconductor die (140) comprises at least one electrical pad at the first main face and optionally at least one electrical pad or thermal pad at the second main face; and wherein the metal bond layers (120g, 120c, 120d) of the two contact bond sheets (200, 300) are bonded to the electrical pads of the at least one semiconductor die (140).

4. The package (100a) of claim 3, comprising: a metal connection bonding the metal bond layers (120g, 120c, 120d) of the two contact bond sheets (200, 300) to the electrical pads of the at least one semiconductor die (140); wherein the metal connection is one or any combination of the following: a sintered metal connection, a soldered metal connection, a diffusion soldered metal connection, a metal connection connected by conductive glue or a nano-structured metal connection.

5. The package (100b) of any of the preceding claims, wherein parts of the metal bond layers (120e, 120f) of the two contact bond sheets (200, 300) are bonded to each other to form a vertical metal connection (120e, 120f) between the two contact bond sheets (200, 300), the vertical metal connection (120e, 120f) forming a non-remelting metal joint (120e, 120f).

6. The package (100b) of claim 5, wherein the non-remelting metal joint (120e, 120f) interconnects at least parts of the metallic through-connections (110d, 130b) of the core layers (210, 310) of the two contact bond sheets (200, 300).

7. The package (100b) of claim 6, wherein the non-remelting metal joint (120e, 120f) forms a via through the homogeneous insulating layer (120a, 120b).

8. The package (100b) of claim 7, comprising: a pad finish (150a, 150b, 150c, 150d) applied to the one or more metallic through- connections (110b, 110c, 110d, 130b) to form external pads for an external electrical connection of the at least one semiconductor die (140).

9. The package (100a) of any of the preceding claims, wherein the one or more metallic through-connections (110b, 110c, 130b) form one of the following structures in the core layer (210, 310): a non-split structure (410), a partially split structure (420), a sectioned (430) or non-sectioned (440) separate contact islands structure, a non-structured copper foil (450) in one of the two contact bond sheets (200, 300).

10. The package (100a) of any of the preceding claims, wherein the core layer (210, 310) of one of the contact bond sheets (200, 300) comprises a substrate inlay (610) comprising an electrically insulating and thermally conductive layer (611) in between two electrically conductive layers (612, 613), the layer stack (610) penetrating the core insulating layer (130a).11 . The package (700) of any of the preceding claims, comprising: at least two semiconductor dies (140, 160), the at least two semiconductor dies (140, 160) forming one or more of the following or other typical power electronic switching configurations: an electrical half-bridge configuration, a parallel die configuration, a common source configuration, a common drain configuration.

12. The package (700) of claim 11 , wherein the at least two semiconductor dies (140, 160) are arranged side-by-side within the two bonded contact bond sheets (200, 300).

13. The package (800, 900) of any of the preceding claims, comprising: at least one second semiconductor die (160) and a third contact bond sheet (400) encapsulating the at least one second semiconductor die (160), the third contact bond sheet (400) being bonded to each of the two contact bond sheets (200, 300).

14. The package (800, 900) of claim 13, wherein at least part of the at least one second semiconductor die (160) is facing the at least one semiconductor die (140) within the three bonded contact bond sheets (200, 300, 400).

15. The package (800, 900) of claim 13 or 14, wherein the at least one semiconductor die (140) and the at least one second semiconductor die (160) are forming one of the following configurations: an electrical half-bridge configuration, a parallel die configuration, a common source configuration, a common drain configuration.

16. The package (900) of any of claims 13 to 15, wherein parts of the metal bond layers (120e, 120f) of the third contact bond sheet (400) are bonded to respective metal bond layers (120e, 120f) of one or both of the two contact bond sheets (200, 300) to form one or more embedded interconnect traces (170b) for an external electrical connection.

Images