Silicon nitride waveguide or photonic integrated circuit fabrication method

Abstract

Silicon nitride waveguide fabrication method including providing a substrate including a stress release trench structure, the stress release recess structure being formed in a silicon oxide layer, depositing a silicon nitride material or layer onto the silicon oxide layer, providing a silicon oxide hard mask on the deposited silicon nitride material or layer to provide an exposed surface delimited by the silicon oxide hard mask and defined by the deposited silicon nitride material or layer, the silicon oxide hard mask including or defining an elongation extending on the deposited silicon nitride material or layer, dry etching the exposed surface a silicon nitride elongated waveguide core located between the silicon oxide hard mask and the silicon oxide layer in which the stress release trench structure is formed; and depositing a silicon oxide cladding layer on the silicon oxide hard mask to form a cladding structure of the silicon nitride waveguide.

Description

[0001] SILICON NITRIDE WAVEGUIDE OR PHOTONIC INTEGRATED CIRCUIT FABRICATION METHOD

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] The present application claims priority to the European Application EP23171876.8 that was filed on May 5th 2023, the entire contents thereof being herewith incorporated by reference.

[0004] FIELD OF THE INVENTION

[0005] The present invention relates to an optical waveguide preparation or fabrication method, or a photonic integrated circuit (PIC) fabrication method. The present invention more particularly concerns a preparation or fabrication method, or a photonic integrated circuit (PIC) fabrication method including one or more silicon nitride optical waveguides. The present invention concerns wafer-scale manufacturing of silicon nitride optical waveguides or photonic integrated circuits including such waveguides.

[0006] BACKGROUND

[0007] High-Q Si3N4microresonators are the central elements for Kerr nonlinear photonics, as well as frequency agile low noise lasers, or traveling-wave parametric amplifiers. The ultralow propagation loss greatly facilitates the soliton formation, allowing high sensitivity, narrow bandpass and low power consumption in applications such as optical communications, ultrafast ranging, or spectroscopy, amongst others. These applications usually require operation in the anomalous dispersion regime, where the Si3N4waveguide thickness typically exceeds 600 nm.

[0008] To date, high-Q tightly confining Si3N4microresonators with such thickness have been routinely achieved using the photonic Damascene reflow process, where Si3N4is deposited onto a reflowed waveguide preform with improved sidewall roughness, as described in US2016 / 0327743. However, devices can suffer from inaccurate dimensional transfer as a result of the undercut created in hard mask etching for the waveguide preforms.

[0009] Another fabrication process, the subtractive process, where waveguides are patterned and etched directly after Si3N4film deposition, is more commonly used to fabricate photonic integrated circuits based on a wide range of material platforms. This process is inherently simpler and offers acceptable dimension accuracy. However, notable drawbacks include the fact that an etching process needs to be specifically developed for each material, and cracks occur in thick films with large stress. To address the stress issue, methods such as two-time film deposition and annealing are applied to release the large stress in Si3N4films. However, these introduce process complexity and lower the efficiency of the process.

[0010] Moreover, to date, the lowest loss Si3N4photonic integrated circuits PICs require electronbeam (e-beam) lithography which is incompatible with wafer scale fabrication (“High-Q Si3N4microresonators based on a subtractive processing for Kerr nonlinear optics”, Zhichao Ye et al., Optics Express 27, no. 24 (2019): 35719-35727).

[0011] The artilce entitled “Stress-released Si3N4 fabrication process for dispersion-engineered integrated silicon photonics”, by WU KAIYI ET AL, published in OPTICS EXPRESS, vol. 28, no. 12, 28 May 2020 (2020-05-28), page 17708 discloses using a SiO2hard mask that is etched to fully remove the SiO2hard mask. This is assured by over-etching. This article also discloses that maintaining over-etching to within 5% minimizes the impact of over-etching on surface roughness.

[0012] A goal of the present invention is to provide a solution to these inconveniences, and in particular, to provide an alternative method that overcomes the above-mentioned inconveniences and assures the provision of ultra-low propagation loss silicon nitride waveguides and photonic integrated circuits.

[0013] SUMMARY

[0014] It is therefore one aspect of the present disclosure to provide a silicon nitride waveguide preparation or fabrication method, or a silicon nitride photonic integrated circuit fabrication method according that addresses the above-mentioned inconveniences and needs.

[0015] The silicon nitride waveguide fabrication method or the silicon nitride photonic integrated circuit fabrication method may include:

[0016] - providing a substrate including at least one stress release trench structure for receiving a waveguide material, the at least one stress release recess structure being formed in a silicon oxide layer or material;

[0017] - depositing a silicon nitride material or layer onto the silicon oxide layer or material and into the at least one stress release recess structure; - providing at least one silicon oxide hard mask on the deposited silicon nitride material or layer to provide at least one exposed surface delimited by the at least one silicon oxide hard mask and defined by the deposited silicon nitride material or layer, the at least one silicon oxide hard mask including or defining at least one elongation extending on the deposited silicon nitride material or layer;

[0018] - dry etching the at least one exposed surface to form at least one silicon nitride elongated waveguide core located between the at least one silicon oxide hard mask and the silicon oxide layer or material in which the at least one stress release trench structure is formed; and

[0019] - depositing a silicon oxide cladding layer or material on the at least one silicon oxide hard mask, subsequent to the step of dry etching, to form a cladding structure of the silicon nitride waveguide.

[0020] The present disclosure also concerns a silicon nitride waveguide, and a silicon nitride photonic integrated circuit substrate produced or provided by the above method.

[0021] The method permits to fabricate wafer-scale ultra-low loss, high confinement silicon nitride optical waveguides and photonic integrated circuits with an optimized subtractive process / method. Advantageously, the method can feature only one deposition step for the Si3N4film.

[0022] The Inventors demonstrate the fabrication of Si3N4optical waveguides and photonic integrated circuits featuring ultra-low propagation loss and tight optical confinement, fabricated with the subtractive process of the present disclosure.

[0023] The Inventors also demonstrate that an increase in propagation loss in Si3N4waveguides after exposure to ultraviolet (UV) irradiation may occur, and that such loss can be recovered by a rapid thermal anneal (RTA). An intrinsic quality factor as high as 20x106at 1.55pm across a 100mm wafer can already be achieved using the fabrication method of the present disclosure.

[0024] The above and other objects, features and advantages of the present invention and the manner of realizing them will become more apparent, and the invention itself will best be understood from a study of the following description with reference to the attached drawings showing some preferred embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate the presently preferred embodiments of the invention, and together with the general description given above and the detailed description given below, serve to explain features of the invention.

[0026] Figure lA shows some exemplary steps of an exemplary waveguide preparation or fabrication method of the present disclosure, or a photonic integrated circuit (PIC) fabrication method according to the present disclosure.

[0027] Figure 1 B shows a patterned hard mask on a silicon nitride layeror material at an intermediate stage of the exemplary optical waveguide preparation or fabrication method, or photonic integrated circuit (PIC) fabrication method according to the present disclosure.

[0028] Figure 2 is a scanning electron microscopic image of filler patterns or stress release trench structures in a silicon oxide layer after etching of the silicon oxide layer but prior to deposition of silicon nitride, for example, corresponding to the stage indicated by the number 2 in Figure 1A.

[0029] Figure 3 is a scanning electron microscopic image of elongated silicon nitride waveguides after etching of the silicon nitride core waveguide material with the silicon oxide hard mask remaining on top of the elongated silicon nitride waveguide core material, corresponding to the stage indicated by the number 5 in Figure 1 A. The filler patterns or stress release trench structures are also shown filled with silicon nitride and have stopped the cracks in the structure or the silicon oxide from propagating to the waveguides, as shown in the upper left part of the image.

[0030] Figure 4A is a side-view scanning electron microscopic image of a silicon nitride waveguide after etching using the silicon oxide hard mask to remove surrounding silicon nitride material, corresponding to the stage indicated by the number 5 in Figure 1A. The porous top part or top surface in the image is the outer or top surface of the silicon oxide hard mask after silicon nitride waveguide etching. The pores will be filled during cladding deposition. A smooth side wall of the silicon nitride waveguide extending downwards from the top surface to the thermal silicon oxide are also visible in the image. Figure 4B is another side-view scanning electron microscopic image of the etched waveguide showing the pores on the top surface of SiC>2 hard mask resulting from chemical reactions with the CxFy etchants. The smooth sidewall of the etched waveguide is also visible in the image.

[0031] Figures 5A and 5B show etching end point graphs of a Si3N4 waveguide with two Si3N4deposition steps (Figure 5A) and with a single Si3N4deposition step (Figure 5B). In Figure 5A, an end point in the middle of the waveguide etching is a clear evidence that the boundary or interface is present between the two Si3N4deposited layers, this is absent in single deposition layer of Figure 5B. This boundary or interface produced by the two step deposition process can result in undesired property changes in the Si3N4waveguide compared to that of the Si3N4layer deposited in a single deposition step.

[0032] Figure 6 is a scanning electron microscopic image of a cross section of a silicon nitride waveguide after cladding deposition onto the silicon oxide hard mask and the silicon nitride elongated waveguide core material, corresponding to the stage indicated by the number 7 in Figure 1 A. The sidewall angle of the exemplary silicon nitride waveguide is 87 degrees, and the silicon nitride waveguide has an exemplary thickness of 720nm and a width of 2000nm.

[0033] Figure 7A is a histogram of fitted intrinsic linewidth of fabricated waveguide or resonator devices before a rapid thermal treatment and Figure 7B is a histogram of fitted intrinsic linewidth after rapid thermal treatment.

[0034] Figures 8A to 8D show linear loss measurements of fabricated silicon nitride microresonators with a FSR of 50 GHz. Figure 8Aand 8B show the intrinsic linewidth distribution and histogram across 1350-1650 nm; while Figures 8C and 8D show loss and dispersion dependence on waveguide width.

[0035] Figure 9A shows a DUV stepper exposure layout across the wafer, and the most probable value KO / 2TT of the ring resonator at different positions of the wafer; and Figure 9B shows a recorded resonance with linewidth fitting at 1549.4 nm. The intrinsic loss rate K0 / 2TT is extracted as 9.59 MHz, corresponding to a quality factor of 20.17 million.

[0036] Herein, identical reference numerals are used, where possible, to designate identical elements that are common to the Figures. Also, the images are simplified for illustration purposes and may not be depicted to scale. DETAILED DESCRIPTION OF SEVERAL EMBODIMENTS

[0037] Figure lA shows an exemplary fabrication method according to the present disclosure. Figure 1 A schematically illustrates some exemplary steps of a waveguide 1 preparation or fabrication method of the present disclosure, or a photonic integrated circuit (PIC) 1 fabrication method according to the present disclosure.

[0038] The method is an optical waveguide 1 or optical waveguide device 1 preparation or fabrication method, an in particular, a silicon nitride waveguide 1 preparation or fabrication method.

[0039] The same method can be used for the fabrication of a photonic integrated circuit that comprises one or more silicon nitride waveguides 1 , and may also include other devices or elements

[0040] The optical waveguide 1 and the waveguide core 3 extend in an elongated manner (see, for example, Figure 3) to define a length L of the waveguide. The length L of the waveguide extends in a light propagation direction of the waveguide 1 when light is guided through the waveguide 1 .

[0041] The waveguide core 3 has a thickness t extending in a direction (substantially) perpendicular to the light propagation in the waveguide 1 , and a width w extending also in a direction (substantially) perpendicular to light propagation in the waveguide 1 and (substantially) perpendicular to the direction in which the thickness t extends (see, for example, Figure 6).

[0042] The optical waveguide 1 and the waveguide core 3 may extend linearly and / or in a curved manner. The optical waveguide 1 and the waveguide core 3 may extend to define a curved or ring waveguide, and may extend to define an optical resonator / microresonator. The fabrication method can produce a plurality of waveguides and the resulting structure may include the plurality of waveguides 1 . These waveguides 1 may have the previously mentioned structure and form and may be arranged to assure light coupling and / or distribution between waveguides 1 . Waveguides 1 may, forexample, be positioned relative to one anotherto assure light coupling from one waveguide to another by, for example, evanescent coupling. Light coupling to a waveguide 1 may also be carried via an exposed outer cross-sectional facet of the waveguide 1 . For example, an optical waveguide 1 comprising a straight bus waveguide may be included that is coupled to an optical waveguide forming a ring-resonator. The waveguides may, for example, have the same (or substantially the same) cross-sectional dimensions in terms of thickness t and width w. The resulting fabricated structure may define one or more photonic integrated circuits. The waveguides may, for example, be tapered, or include a tapered extremity.

[0043] The fabrication method includes providing at least one substrate 5 including at least one or a plurality of stress release trench structures 7 (see, for example, stage number 2 of Figure 1A). The stress release trench structure 7 will receive a waveguide material or waveguide core material that is silicon nitride Si3N4.

[0044] The substrate 5 includes at least one or a plurality planar zones 8. The planar zone 8 is a stress release trench structure-free zone. The planar zone 8 defines a surface SC upon which one or more waveguide cores 3 are formed. The planar zone 8 is, for example, enclosed or surrounded by one or more stress release trench structures 7 (see, for example, Figure 2).

[0045] The stress release recess structures 7 are formed in a silicon oxide SiO2layer or material 9. The silicon oxide SiO2layer or material 9 forms, for example, a lower cladding layer or material of the waveguide 1 .

[0046] The fabrication method further includes depositing a silicon nitride Si3N4layer or material 11 onto the silicon oxide SiO2layer or material 9, and into the stress release recess structures 7. The silicon nitride Si3N4layer or material 11 is deposited onto and into the stress release recess structures 7, and onto the exposed surface SC of the planar zones 8 (see, for example, stage number s of Figure 1A).

[0047] Silicon nitride can be deposited, for example, by low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced low-pressure chemical vapor deposition as known to the skilled person (see, for example, Jaeger, Richard C. (2001), “Thermal Oxidation of Silicon”. Introduction to Microelectronic Fabrication, Upper Saddle River: Prentice Hall, ISBN 978-0- 201-44494-0, the entire contents of which are incorporated herein by reference).

[0048] The silicon nitride Si3N4material deposition of the silicon nitride Si3N4layer or material 11 onto the silicon oxide SiO2layer or material 9 is, for example, carried out solely once, or in a single material deposition step. This assures a less complex and more efficient fabrication. This also permits to remove any boundary or interface that forms during multiple Si3N4depositions, to assure more uniform waveguide core properties.

[0049] Figures 5A and 5B show etching end point graphs of a Si3N4 waveguide with two Si3N4deposition steps (Figure 5A) and with a single Si3N4deposition step (Figure 5B). In Figure 5A, an end point in the middle of the waveguide etching is a clear evidence that the boundary or interface is present between the two Si3N4 deposited layers, this is absent in single deposition layer of Figure 5B. This boundary or interface produced by the two step deposition process can result in undesired property changes in the Si3N4 waveguide and optical loss via light scattering which is thus advantageously eliminated by the single the Si3N4material deposition that forms the waveguide core 3 in the method of the present disclosure. The Si3N4waveguide material or the Si3N4waveguide core 3 consists solely of Si3N4material deposited in only one sole material deposition step, or non-multiple Si3N4material deposition steps.

[0050] A thickness t of the deposited silicon nitride Si3N4 layer or material 11 may, for example, be > 600nm, or a thickness t where 2000nm > t > 600nm.

[0051] At least one silicon oxide SiO2hard mask 15 is provided on the deposited silicon nitride 11 (see, for example, Figure 1 B), to provide one or more exposed silicon nitride surfaces 17 delimited by the silicon oxide SiO2hard mask 15 and defined by the deposited silicon nitride 11.

[0052] The silicon oxide SiO2hard mask 15 includes or defines one or more elongations PL (see, for example, Figure 1 B) extending on (or on top of) the deposited silicon nitride 11 (for example, directly in contact with the deposited silicon nitride 11). The elongations PL extend, for example, in the form of an elongated structure or waveguide, for example, in a light propagation direction of the waveguide 1.

[0053] Providing the at least one silicon oxide hard mask 15 includes depositing a silicon oxide SiO2layer or material 19 on the deposited silicon nitride layer or material 11 which is subsequently patterned or structured to provide the silicon oxide hard mask 15 (see, for example, stage numbers 4 and 5 of Figure 1A, and Figure 1 B). The silicon oxide hard mask layer or material 19 is, for example, deposited by low-pressure chemical vapor deposition LPCVD. The silicon oxide hard mask is grown, for example, based on the LPCVD TEOS (tetraethyl orthosilicate Si(OC2Hs)4)) process. It employs the dissociation of TEOS at low pressure, e.g. 250 mTorr, and at temperatures exceeding 600°C: Si(OC2Hs)4 - SiO2+ 2C2H4 + H2O. A layer thickness between 0.5 microns and 1 micron may, for example, be deposited.

[0054] The deposited silicon nitride layer or material 11 is subsequently patterned or structured by carrying out deep ultraviolet (DUV) photolithography to pattern the deposited silicon oxide SiO2layer or material 19 provided on the deposited silicon nitride (Si3N4) layer 11 , to pattern and structure the silicon oxide SiO2layer or material 19 and provide the silicon oxide hard mask 15 including or defining the one or more elongations PL.

[0055] Photolithography or UV lithography is used to transfer a (geometric) pattern or structure from a photomask or optical mask PM to the deposited silicon oxide SiO2layer or material 19. Deep ultraviolet (DUV) photolithography using, for example, light of wavelength <400nm, for example, in the range 193nm-254nm illuminates the photomask PM to define an exposure pattern on and in the deposited silicon oxide SiO2layer or material 19 such that the resulting pattern formed on the deposited silicon oxide SiO2layer or material 19 can be transferred into the underlying silicon nitride (Si3N4) layer 11 .

[0056] The DUV light is passed through, for example, a chrome-on-quartz photomask, whose opaque areas act as a stencil of the desired pattern. The DUV light exposed areas of the deposited silicon oxide SiO2layer or material 19 then undergo an etching using, for example, C4F8and He to remove these areas (the deposited silicon oxide SiO2layer or material 19 remains in areas where the photomask PM blocked light exposure to form the silicon oxide SiO2hard mask 15) and produces the exposed silicon nitride areas or surfaces 17 of the underlying silicon nitride material or layer 11 that can be subsequently processed.

[0057] An ASML PAS 5500 / 350C Deep-UV stepper photolithography tool was, for example, used, for example, to expose and produce the silicon oxide SiO2hard mask 15.

[0058] The above-described approach is a positive photoresist exposure approach. Alternatively, a negative photoresist exposure approach may also be used using negative photoresist.

[0059] The fabrication method further includes dry etching the exposed surfaces 17 to form one or more silicon nitride Si3N4elongated waveguide cores 3 located between the silicon oxide SiO2hard mask 15 and the silicon oxide SiO2layer or material 9 in which the stress release trench structures 7 are formed (see, for example, stage number s of Figure 1A).

[0060] Dry etching of the exposed surfaces 17 is carried out to remove the deposited silicon nitride material 11 between the exposed surface 17 and the silicon oxide layeror material 9 containing the stress release recess structures 7, or in which the stress release recess structures 7 are formed.

[0061] Dry etching the exposed surfaces 17 exposes first and second side walls SW1 , SW2 of the silicon nitride Si3N4waveguide core 3. The side walls SW1 , SW2 extend away from the silicon oxide SiO2hard mask 15 and towards the substrate 5. The side walls SW1 , SW2 may extend, for example, between the silicon oxide SiO2hard mask 15 and the silicon oxide SiO2layer or material 9. Dry etching may, for example, be carried out to remove the silicon nitride material 11 to expose the surface SC (or a portion thereof) of the planar zone or zones 8.

[0062] Dry etching forms a porous surface PS on the silicon oxide (SiO2) hard mask 15 orforms pores in the silicon oxide (SiO2) hard mask 15 (see, for example, Figures 4A and 4B).

[0063] Etching is carried out to such that the silicon nitride Si3N4 elongated waveguide core 3 has, for example, a height or thickness t > 600nm, or a thickness t where 2000nm > t > 600nm, or 10OOnm > t > 600nm, or 830nm > t > 600nm. The silicon nitride Si3N4 elongated waveguide core 3 has, for example, a width w where 4000nm > w > 600nm.The length L of the elongated waveguide core 3 is, for example, application dependent and can typically be several millimeters or more in value.

[0064] Dry etching or plasma etching to form the silicon nitride elongated waveguide core 3 comprises, for example, carrying out anisotropic dry etching carried out using, for example, CxFy-based chemical substances. Oxygen, may, for example, be added in order to remove CF polymers created as an etching by-product. Etching can, for example, be carried out with CHF3and SF6, and with O2also, serving to remove the etching by-product from chemical reactions between Si3N4 and CHF3 / SFe.

[0065] Figure 4A is a side-view scanning electron microscopic image of a silicon nitride waveguide 3 after etching using the silicon oxide hard mask 15 to remove surrounding silicon nitride material 11 , corresponding to the stage indicated by the number 5 in Figure 1 A. The porous top part or top surface PS in the image is the outer or top surface of the silicon oxide hard mask 15 after silicon nitride waveguide etching. The pores will be filled during cladding 21 deposition. A smooth side wall SW2 of the silicon nitride waveguide 3 extending downwards from the top surface to the thermal silicon oxide 9 are also visible in the image.

[0066] Figure 4B is another side-view scanning electron microscopic image of the etched waveguide material 11 showing the pores on the top surface of SiO2hard mask 15 resulting from chemical reactions with the CxFyetchants. The smooth sidewall SW1 of the etched waveguide material 11 is also visible in the image. A silicon oxide SiO2cladding (or passivation) layer or material 21 is deposited on the silicon oxide SiC>2 hard mask 15, subsequent to dry etching of the exposed surfaces 17, to form a (upper) cladding structure or covering CS of the silicon nitride waveguide 1 or waveguides 1 (see, for example, stage number 7 of Figure 1A). The thickness of the silicon oxide SiO2cladding (or passivation) layer or material 21 is, for example, between 0.5 microns and 2.5 microns, for example, 1 micron.

[0067] The silicon oxide hard mask 15 and the silicon oxide cladding layer or material 21 deposited onto the silicon oxide hard mask 15 form the cladding structure CS (or are a part thereof) of the silicon nitride waveguide 1 .

[0068] Advantageously, both the silicon oxide hard mask layer or material 19 used to form the hard mask 15 and the silicon oxide SiO2cladding Iayer 21 are, for example, deposited by the same deposition method. The silicon oxide SiO2cladding layer 21 may, for example, be also deposited by low-pressure chemical vapor deposition LPCVD. The silicon oxide cladding layer 21 is similarly deposited at low pressure, for example, based on the LPCVD TEOS (tetraethyl orthosilicate Si(OC2Hs)4)) process. It employs the dissociation of TEOS at low pressure, e.g. 250 mTorr, and at a temperature exceeding 600°C. The deposition can be expressed as: Si(OC2H5)4 ->• SiO2+ 2C2H4+ H2O.

[0069] The silicon oxide SiO2cladding layer or material 21 is deposited, for example, on the silicon oxide SiO2hard mask 15, the silicon nitride elongated waveguide core or cores 3 and the stress release recess structures subsequent to dry etching the exposed surfaces 17.

[0070] Deposition of the silicon oxide SiO2cladding layeror material 21 forms, for example, a cladding or cladding covering on the (exposed) side walls SW1 , SW2.

[0071] The silicon oxide cladding layer or material 21 is deposited on the porous surface PS or into the pores of the silicon oxide hard mask 15, and fills the pores.

[0072] The optical waveguide 1 (or each optical waveguide) comprises a single deposition silicon nitride Si3N4layer or material, or solely one silicon nitride Si3N4deposition between the lower cladding SiO2material or layer 9 and the upper or opposite cladding SiO2material or layer 21 . The (one and / or the same) single deposition silicon nitride Si3N4 layer or material directly contacts the lower cladding SiO2material or layer 9 and the upper or opposite cladding SiO2material or layer 21 . The single deposition silicon nitride Si3N4layer or material is boundaryless or interface-less with any other silicon nitride Si3N4 layer or material. Thermal annealing may, for example, be carried out subsequent to dry etching and before deposition of the silicon oxide cladding layer or material 21 to remove hydrogen or to break hydrogen bonds (for example, O-H bonds, and / or Si-H bonds). Thermal annealing may, for example, be additionally or alternatively carried out subsequent to the deposition of the silicon oxide cladding layer or material 21 to remove hydrogen or to break hydrogen bonds (for example, O-H bonds, and / or Si-H bonds).

[0073] Thermal heating or annealing of the processed or fabricated structure or device can, for example, be carried out by heating in an oven or a furnace, for example, in a controlled atmosphere, for example, a nitrogen atmosphere. However, different methods can be used, for example, annealing in a chlorine atmosphere, or annealing using UV light. The annealing temperature can, for example, be carried out for a duration between 10 and 35 hours and the annealing temperature may, for example, between 1100°C and 1200°C. For example, annealing can be performed for 11 hours at a temperature of 1200°C.

[0074] The substrate 5 including the stress release trench structures 7 may, for example, be a silicon oxide substrate. The substrate 5 comprises or consists of a silicon oxide layer or material in which the stress release trench structures 7 are formed. The substrate 5 may, for example, comprise or consist of silicon, sapphire, silicon carbide, lithium niobate, fused silica, or quartz.

[0075] The substrate 5 may comprise or consist of silicon, and the silicon oxide SiO2layer or material 9 may be formed orgrown by thermal (wet) oxidation on the silicon substrate. During oxidation, the top-most silicon (Si) atoms of the substrate are converted to SiO2by, for example, flowing oxygen through a high-temperature furnace tube.

[0076] The stress release trench structures 7 comprises at least one or a plurality of indentations or depressions 33 formed in the silicon oxide SiO2layer or material 9 (Figures 1 A, 1 B). The at least one or the plurality of indentations or depressions 33 define or delimit one or more silicon oxide pillars or supports 35. The plurality of indentations or depressions 33 are filled with silicon nitride material 11 when this material is deposited onto the SiO2material or layer 9. The stress release trench structure 7 prevents cracks forming or propagating to or into the waveguide core 3 or waveguide device 1 . The stress release trench structure or structures 7 enclose, for example, the waveguide cores 3 or waveguide devices 1 to prevent crack propagation to the waveguide cores 3 or waveguide devices 1 . A depth of the indentations 33 measured from an outer surface of the silicon oxide material or layer 9 and extending into the silicon oxide material or layer 9 may, for example, be substantially equal to or greater than the thickness t of the at waveguide core 3. A depth of the indentation 33 may, for example, be between 1 .5 microns and 5 microns, for example 2.5 microns. A depth of the indentation 33 may, for example, be >3 microns, for example, >3 microns and <5 microns or 10 microns, for example 3.5 microns. This prevents cracks forming or extending through or across the optical waveguide or waveguide core 3. The depth direction being in a direction perpendicular to the plane of extension defined by the substrate 5, or perpendicular to the elongated guiding direction or propagation direction of light in the waveguide core 3.

[0077] An indentation-free zone 8 may, for example, separate stress release trench structures 7 or groupings of indentations 33 and pillars 35, such a separation distance D may be, for example, 2pm<D<50pm. The waveguide core 3 and the stress release trench structure 7 are, for example, located at different levels or in different planar level or planes of the silicon oxide material or layer 9. The waveguide core 3 is, for example, located above or at a higher level than the stress release trench structure 7. Light guiding or propagation in the waveguide core 3 is above the stress release trench structure 7.

[0078] The plurality of indentations 33 may be, for example, regularly or irregularly spaced one from the other. The plurality of indentations may form, for example, at least one repeating pattern of indentations across the silicon oxide material or layer 9. The plurality of indentations 33 may form, for example, a checkerboard structure or layout across the SiO2material or layer 9.

[0079] The stress release recess structure or structures 7 are formed, for example, by carrying out photolithography to pattern a photoresist layer 37 deposited on the silicon oxide (SiO2) layer or material 9, and carrying out subsequent dry etching.

[0080] DUV Photolithography or UV lithography is, for example, used to transfer a (geometric) pattern or structure from a photomask or optical mask 39 to the photosensitive photoresist 37. Deep ultraviolet (DUV) photolithography using, for example, light of wavelength <400nm, for example, in the range 193nm-254nm illuminates the photomask 39 to define an exposure pattern on and in the photoresist 37 such that the resulting pattern can be transferred into the underlying SiO2layer or material 9 by dry etching. The exposure UV or DUV light is passed through, for example, a chrome-on-quartz photomask 39, whose opaque areas act as a stencil of the desired pattern. The photoresist layer 37 may be baked before and / or after light exposure. The exposed photoresist areas then undergo a chemical development to remove unwanted photoresist areas (photoresist remains in areas where the photomask 39 blocked light exposure) and produces areas that are open or exposing portions of the underlying SiO2material or layer 9 that can be subsequently etched to provide the substrate 5 including the stress release trench structures 7 (see, for example, stage number 2 of Figure 1 A). The SiO2layer 9 is, for example, dry etched with, for example, C4F8 and He, to a depth between, for example, 2 and 4 microns.

[0081] An ASML PAS 5500 / 350C Deep-UV stepper photolithography tool was used, for example, to expose and produce the substrate 5 including the stress release trench structures 7. The photoresist coating and development was performed, for example, using an in-line TEL Clean Track ACT-8 tool. The photoresist may, for example, between 1 and 2 microns thick M108Y (6cP) DUV photoresist from JSR Micro NV, optionally on top of 60nm of DUV42P as bottom layer anti-reflective coating (BARC). Coating / exposure / development may be performed, for example, using the standard recipes, for example, as provided by the vendor.

[0082] The above-described approach is a positive photoresist exposure approach. Alternatively, a negative photoresist exposure approach may also be used using negative photoresist.

[0083] According to a further aspect of the present disclosure, the propagation loss in the Si3N4waveguides 1 can be reduced by carrying out a rapid thermal anneal (RTA). A rapid thermal anneal can, for example, be carried out over a duration between 30 to 90 minutes, and at a temperature between 350°C and 550°C to increase a quality factor of the silicon nitride waveguide 1. For example, rapid thermal anneal can be carried out for 60 minutes at a temperature of 500°C. The rapid thermal anneal is carried out on the structure comprising the fabricated waveguide or waveguides 1 including the waveguide core 3 upon which the outer cladding material or layer 21 has been deposited (for example, after stage number 7 of Figure 1A).

[0084] Thermal annealing carried out subsequent to dry etching and before deposition of the silicon oxide cladding layer or material 21 to remove hydrogen or to break hydrogen bonds (for example, O-H bonds, and / or Si-H bonds) and thermal annealing carried out subsequent to the deposition of the silicon oxide cladding layer or material 21 may both be carried out prior to this rapid thermal anneal. Without being restricted to any particular theory, the Inventors believe that an increase in propagation loss in the Si3N4 waveguides may result following exposure to ultraviolet (UV) irradiation and that the rapid thermal anneal permits recovery of this propagation loss.

[0085] The Inventors show that an intrinsic quality factor as high as 20x106at 1 .55pm across a 100mm wafer can already be achieved using the fabrication method of the present disclosure. This exemplary fabrication is now described.

[0086] SisN4 waveguides / PICs were fabricated on a SiC>2 layer 9 grown using thermal wet oxidation on single-crystal silicon wafers 5. In order to release the tensile stress and prevent crack formation, mechanical trenches 33 are created on the SiC>2 Iayer9, which define filler patterns, to define boundaries and enclose individual local areas with manageable stress. The mechanical trenches 33 are formed by dry-etching to a depth of (about) 2.5 pm to break force accumulation via periodically interrupting the film continuity.

[0087] In contrast to the prevailing two-time deposition approach of the prior art, only one single LPCVD Si3N4film 1 1 is deposited in a single step, and no cracks are observed thanks to the deep filler patterns 7. The as-deposited Si3N4film 11 has a 1.2% variation in thickness uniformity and a 0.3 nm root mean square (RMS) roughness, which renders a smooth top surface with reduced scattering losses.

[0088] The waveguides 3 were then written with a KrF 248 nm deep-ultraviolet (DUV) stepper lithography, and are transferred to the Si3N4 layer via anisotropic dry etching with CxFy-based chemicals.

[0089] For superior etch quality and smooth waveguide sidewalls, a LPCVD SiO2layer 19 was deposited on top of the Si3N4film 11 to provide an etching hard mask 15, and oxygen was added in the waveguide core 3 etching process in order to remove CF polymers as etching by-product.

[0090] The Si3N4waveguide cores 3 are annealed at a high temperature (1200°C) for 1 1 hours to drive out excess H2and to break the Si-H and N-H bonds.

[0091] Cladding of the devices was then performed with 1 pm LPCVD SiO2material 21 , the same material as the hard mask 15, advantageously permitting to avoid further steps for hard mask removal and to preserve the smoothness of the Si3N4waveguide core 3 top surface. The same high-temperature treatment was applied to the SiO2cladding 21 (1200°C, 11 hours) to consolidate the film and to achieve low absorption losses by driving out the H2and breaking the O-H bonds.

[0092] More specifically, ring micro-resonators were fabricated with a radius of 455 pm, a height t of 720 nm and a width w of 2.6 pm, coupled to a straight bus waveguide with the same crosssection. This dimension ensures tight confinement. The waveguide cross-section is shown in Figure 6. The waveguide has a sidewall angle of 87°.

[0093] A scanning electron microscopy (SEM) inspection of the sidewall SW1 , SW2 reveals a smooth surface. Scanning laser spectroscopy was used to characterize the resonance linewidths of the microresonator (i.e. microresonator loss) from 1350 nm to 1630 nm. The intrinsic loss K0 / 2TT for each resonance is extracted, and the histogram of the loss distribution is presented in Figure 7A. The Inventors characterize the microresonator by the most probable K0 / 2TT value, which is 12 MHz, corresponding to an intrinsic quality factor of Q ~ 16.1 x6and a linear loss of ~2.2 dB / m.

[0094] Furthermore, the Inventors report an increase in microresonator quality factor with a rapid thermal anneal (RTA) at 500°C for 1 hour, which they postulate to be an effect of depopulation of defect centers in the silicon nitride layer. The optically active defect centers, such as silicon dangling-bonds, are potentially generated after exposure to ultraviolet (UV) irradiation with an energy larger than the SixNy bandgap (~5 eV), which may be present in plasma cleaning or in a UV ozone cleaning procedure.

[0095] Figures 8A to 8D show linear loss measurements of fabricated silicon nitride microresonators with a FSR of 50 GHz. Figure 8Aand 8B show the intrinsic linewidth distribution and histogram across 1350-1650 nm; while Figures 8C and 8D show loss and dispersion dependence on waveguide width.

[0096] To annihilate the defect states, rapid thermal annealing of the measured device for 1 hour at 500°C was performed, the intrinsic loss K0 / 2TT histogram of the post-annealed device is presented in Figure 7B. The most probable intrinsic loss rate is 8 MHz.

[0097] The measurement of wafer-scale loss over nine DUV stepper exposure fields is depicted in Figure 9A and 9B. In the central field, one measured normalized transmission spectrum at 1549.4 nm with an intrinsic loss rate of 9.59 MHz is presented in Figure 9B. This linewidth corresponds to a quality factor of Q ~20.17x106and a linear loss of ~1 .7 dB / m.

[0098] While the invention has been disclosed with reference to certain preferred embodiments, numerous modifications, alterations, and changes to the described embodiments, and equivalents thereof, are possible without departing from the sphere and scope of the invention. Accordingly, it is intended that the invention not be limited to the described embodiments and be given the broadest reasonable interpretation in accordance with the language of the appended claims. The features of any one of the above described embodiments may be included in any other embodiment described herein.

Claims

CLAIMS1 . Silicon nitride waveguide (1) fabrication method including:- providing a substrate (5) including at least one stress release trench structure (7) for receiving a waveguide material (11), the at least one stress release recess structure (7) being formed in a silicon oxide (SiO2) layer or material (9);- depositing a silicon nitride material or layer (11) onto the silicon oxide (SiO2) layer or material (9) and into the at least one stress release recess structure (7);- providing at least one silicon oxide (SiO2) hard mask (15) on the deposited silicon nitride material or layer (11) to provide at least one exposed surface (17) delimited by the at least one silicon oxide (SiO2) hard mask (15) and defined by the deposited silicon nitride material or layer (11), the at least one silicon oxide (SiO2) hard mask (15) including or defining at least one elongation (PL) extending on the deposited silicon nitride material or layer (11), the at least one elongation (PL) extending in the form of an elongated waveguide;- dry etching the at least one exposed surface (17) to form at least one silicon nitride (SisN^ elongated waveguide core (3) located between the at least one silicon oxide (SiO2) hard mask (15) and the silicon oxide (SiO2) layer or material (9) in which the at least one stress release trench structure (7) is formed; and- depositing a silicon oxide (SiO2) cladding layer or material (21) on the at least one silicon oxide (SiO2) hard mask (15), subsequent to the step of dry etching, to form a cladding structure of the silicon nitride waveguide (1).

2. Method according to claim 1 , wherein the step of dry etching exposes side walls (SW1 , SW2) of the at least one silicon nitride (SisN^ waveguide core (3), and the step of silicon oxide (SiO2) cladding layer or material (21) deposition forms a cladding on the exposed side walls (SW1 , SW2).

3. Method according to claim 1 or2, wherein the silicon nitride layer or material (11) deposition is carried out solely once, or in a single deposition step.

4. Method according to anyone of the previous claims, wherein providing the silicon oxide (SiC>2) hard mask (15) includes carrying out DUV photolithography to pattern a silicon oxide (SiC>2) layer (19) provided on the deposited silicon nitride (Sisl^ ) layer or material (11).

5. Method according to any one of the previous claims, wherein a silicon oxide (SiO2) layer or material (19) is deposited on the deposited silicon nitride material or layer (11) and processed to provide the silicon oxide (SiO2) hard mask (15), and the silicon oxide (SiO2) cladding layer (21) is deposited by the same deposition method as that used for the deposition of the silicon oxide (SiC>2) layer or material (19) on the deposited silicon nitride material or layer (11).

6. Method according to anyone of the previous claims, wherein dry etching used to form the at least one silicon nitride elongated waveguide core (3) comprises anisotropic dry etching carried out using CxFy-based chemical substances.

7. Method according to anyone of the previous claims, wherein the silicon oxide (SiO2) cladding layer or material (21) is deposited on the silicon oxide (SiO2) hard mask, and on the at least one silicon nitride (Sisl^ ) elongated waveguide core (3) and on the at least one stress release recess structure (7) subsequent to the step of dry etching.

8. Method according to anyone of the previous claims, wherein thermal annealing is carried out subsequent to the step of dry etching and before deposition of the silicon oxide (SiC>2) cladding layer or material (21 ) to remove hydrogen or to break hydrogen bonds.

9. Method according to anyone of the previous claims, wherein thermal annealing is carried out subsequent to the deposition of the silicon oxide (SiC>2) cladding layer or material (21) to remove hydrogen or to break hydrogen bonds.

10. Method according to any one of the previous claims, wherein a rapid thermal anneal is carried out over a duration between 30 to 90 minutes, and at a temperature between 350°C and 550°C to increase a quality factor of the silicon nitride waveguide (1).11 . Method according to anyone of the previous claims, wherein the at least one silicon nitride (SisN4) elongated waveguide core (3) has a height or thickness (t) > 600nm.

12. Method according to anyone of the previous claims, wherein dry etching of the at least one exposed surface (17) is carried out to remove deposited silicon nitride (Si3N4) layer ormaterial (11) located between the at least one exposed surface (17) and the silicon oxide (SiO2) layer or material (9) in which the at least one stress release recess structure is formed.

13. Method according to anyone of the previous claims, wherein dry etching the at least one exposed surface forms a porous surface (PS) on the silicon oxide (SiO2) hard mask (15), and the silicon oxide (SiO2) cladding layer or material (21) is deposited on the porous surface (PS) to fill the pores of the silicon oxide (SiO2) hard mask (15).

14. Method according to anyone of the previous claims, wherein the silicon oxide (SiO2) hard mask (15) and the silicon oxide (SiO2) cladding layer or material (21) deposited on the silicon oxide (SiO2) hard mask (15) form a cladding structure of the silicon nitride waveguide (1).

15. Method according to anyone of the previous claims, wherein the at least one stress release recess structure (7) is formed by carrying out DUV photolithography to pattern a photoresist layer or material (37) deposited on the silicon oxide (SiO2) layer or material (9), and subsequently carrying out dry etching.

16. Method according to anyone of the previous claims, wherein a depth of indentations (33) of the at least one stress release trench structure (7) is greater or equal to 3 microns.

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