Device, system and method for optimizing characteristics of a transistor channel

EP4713973A1Pending Publication Date: 2026-03-25VERSUM MATERIALS US LLC
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Patent Information

Authority / Receiving Office
EP · EP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-05-16
Publication Date
2026-03-25

AI Technical Summary

Technical Problem

Amorphous metal-oxide semiconductor materials in semiconductors face challenges in balancing high electron mobility with threshold-voltage stability in transistor channels, leading to inconsistent device performance and potential premature failure.

Method used

A semiconductor device with a multilayered channel structure comprising a carrier deficient layer and an electron injection layer, interleaved to form an interleaved channel, where the carrier deficient layer is an indium(III) oxide with a high bond-dissociation energy dopant and the electron injection layer is pure indium(III) oxide or annealed with a low bond-dissociation energy dopant, enhancing electron mobility and stability.

Benefits of technology

The solution achieves high electron mobility and improved electrical stability of the transistor channel, enabling consistent device performance across a wide range of operating conditions and enhancing the dynamic range of semiconductor devices.

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Abstract

A device and related method are disclosed. The device may include a gate structure, a first electrode, and a second electrode. In addition, the device may include a multilayered channel structure configured to be in electrical communication with the first electrode and the second electrode. The multilayered channel structure has a carrier deficient layer and an electron injection layer disposed on the carrier deficient layer.
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