Systems and methods for reducing leakage-current progression in cold cathode x-ray emission tubes

Abstract

Apparatuses and methods for prolonging longevity of cold cathode X-ray emission tubes by reducing a leakage current between a gate electrode and a cathode electrode of an electron emitter array chip. Sputterproofing elements, such as barrier notches within cavity walls or isolation layers of insulating materials encapsulating cavity walls and the gate electrode, prevent a conductive path forming on interlevel dielectric layer (ILD) cavity walls over time due to deposition of conducting material sputtered from the emitter tips upon the ILD wall surface.

Description

[0001] SYSTEMS AND METHODS FOR REDUCING LEAKAGE-CURRENT PROGRESSION IN COLD CATHODE X-RAY EMISSION TUBES

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of priority from U.S. Provisional Patent Application No. 63 / 469,545, filed May 30, 2023 and U.S. Provisional Patent Application No. 63 / 652,266, filed May 28, 2024 the contents of which are incorporated by reference in their entirety.

[0004] FIELD OF THE DISCLOSURE

[0005] The disclosure herein relates to systems and methods for reducing leakage current in cold cathode x-ray emission tubes. In particular the disclosure relates to using sputterproofing elements to inhibit of leakage current across an interlevel dielectric layer of an electron emitter array chip.

[0006] BACKGROUND

[0007] When assembling a device containing a field emission array (FEA) source, such as an X-ray tube or the like, the FEA chip may be exposed to a high-temperature cycle often in an uncontrolled environment. This may expose the surface of the metallic cones (Molybdenum) and / or the metallic gate layer to uncontrolled oxidation or any other undesired surface change.

[0008] Moreover exposure to oxidation during manufacture increases the conductivity of the exposed surfaces of the interlevel dielectric layer and increasing leak current between the gate electrode and the cathode of the FEA. Great care is therefore taken to prevent oxidation during manufacture of FEA chips.

[0009] Even when oxidation is avoided during manufacture, electron emitter array chips used in imperfect vacuums have been found to deteriorate over time. Over the lifetime of the chip, current leakage between the gate electrode and the emitter cones of the electron emitter increases which limits the useful lifespan of the X-ray tube.

[0010] The need remains, therefore, for a leakage current inhibiting emission chip. The invention described herein addresses the above-described needs.

[0011] SUMMARY OF THE EMBODIMENTS

[0012] It is an objective of the invention to reduce current leakage in cold cathode x-ray emission tubes and enhance its lifetime.

[0013] According to one aspect of the presently disclosed subject matter, an apparatus for reducing a leakage current between a gate electrode and a cathode electrode of an electron emitter array chip is disclosed. The apparatus comprises a non-conductive interlevel dielectric layer (ILD) comprising a plurality of ILD cavities sandwiched between the gate electrode and the cathode electrode. The apparatus also comprises a gated cone electron source having a plurality of emitter tips arranged in an array and situated in cavities within the interlevel dielectric layer (ILD). The apparatus further comprises a layer of an insulating material having high dielectric constant encapsulating the emitter tips and cavity walls of the ILDs to prevent the formation of a conducting path connecting the gate electrode and the cathode electrode formed by deposition of conducting material sputtered from the emitter tips upon the ILD wall surface.

[0014] As appropriate, the emitter tips are made of chromium or molybdenum.

[0015] As appropriate, the insulating material is selected from a group of Hafnium (IV) oxide (HfO2) , Titanium (IV) oxide (TiO2) , Chromium (IV) oxide (CrO2) and Zirconium (IV) oxide (ZrO2).

[0016] As appropriate, the insulating layer is configured to slow down the apparatus deterioration rate by generating an isolation layer over a gate layer surface, preventing or minimizing the current leakage between the base of the gated cone and the bottom of the gate electrode. As appropriate, the insulating layer is configured as an efficient barrier layer that can withstand a very high temperature and is configured to protect the metallic gated cones and metallic gate layer from surface oxidation.

[0017] As appropriate, the insulating layer has a low Work Function and high dielectric constant.

[0018] As appropriate, the insulating layer is configured to enhance electron emission from the emitter tips and reduce the required gate voltage for a given emission current.

[0019] In another aspect of the presently disclosed subject matter, an apparatus for reducing a leakage current between a gate electrode and a cathode electrode of an electron emitter array chip is disclosed. The apparatus comprises a non-conductive interlevel dielectric layer (ILD) comprising a plurality of ILD cavities sandwiched between the gate electrode and the cathode electrode. The apparatus also comprises a gated cone electron source having a plurality of emitter tips arranged in an array and situated in cavities within the interlevel dielectric layer (ILD). The apparatus further comprises a barrier notch provided on cavity walls of the ILDs to prevent the formation of a continuous conducting path connecting the gate electrode and the cathode electrode formed by deposition of conducting material sputtered from the emitter tips upon the ILD wall surface.

[0020] As appropriate, the emitter tips are made of chromium or molybdenum.

[0021] As appropriate, the barrier notch on the ILD walls is configured to prevent the deposition of conducting material upon the internal surfaces of notch which do not have direct line of sight to the adjacent emitter cones.

[0022] As appropriate, the barrier notch on the ILD walls is configured to keep the conductivity of ILD layer low inhibiting the leakage current between the gate electrode and the cathode electrode.

[0023] As appropriate, the dimension of the barrier notch is selected such that there is at least one continuous sputterproof zone forming a ring along the surface of the ILD cavity wall circumscribing the emitter tip to prevent deposition of conducting material thereupon, wherein the continuous sputterproof ring is a region around a locus of points within the notch which do not have a line of sign to the emitter tip and which circumscribe the emitter tip.

[0024] As appropriate, the depth of the barrier notch within the ILD cavity wall is selected to be sufficient to prevent the deposition of the conductive layer and prevent the damage of mechanical integrity of the ILD layer.

[0025] As appropriate, the depth of the barrier notch within the ILD cavity wall can be about half the distance between adjacent emitter tips.

[0026] As appropriate, the depth of the barrier notch within the ILD cavity wall is selected such that a diagonal distance between the adjacent emitter tips may be sufficient to support the ILD layer in case the barrier notches of adjacent ILD cavity wall overlap each other.

[0027] In still another aspect of the presently disclosed subject matter a method is taught for reducing leakage current between a gate electrode and a cathode electrode of an electron emitter array chip. The includes providing a wafer comprising a substrate, a non-conductive interlevel dielectric layer (ILD) and a metallic gate layer; using lithography to etch a plurality of windows through the metallic gate layer and a plurality of ILD cavities within the ILD; shaping internal walls of the ILD cavities; forming a plurality of emission cones within the ILD cavities; and sputterproofing the internal walls of the ILD cavities thereby preventing formation of a conducting path connecting the gate electrode and the cathode electrode formed by deposition of conducting material sputtered from emitter tips upon ILD cavity wall surfaces.

[0028] The step of sputterproofing may include depositing an insulating layer encapsulating any or all of the the gate electrode, the emitter tips, and the ILD cavity wall surfaces. For example by producing an insulating layer comprising at least one oxide material selected from a group consisting of Hafnium(IV) oxide (HfO2), Chromium (IV) oxide (CrO2), Titanium(IV) oxide (TiO2) and Zirconium(IV) oxide (ZrO2) and combination thereof.

[0029] Additionally or alternatively, the step of sputterproofing comprises etching a barrier notch within the cavity walls of the ILDs to prevent the formation of a continuous conducting path connecting the gate electrode and the cathode electrode formed by deposition of conducting material sputtered from the emitter tips upon the ILD cavity wall surfaces.

[0030] Typically, the step of using lithography to etch a plurality of windows through the metallic gate layer and a plurality of ILD cavities within the ILD comprises laying a photoresist layer over the metallic gate layer having gaps where cavities of the isolation layer are required; dry-etching of the isolation layer; and removing the photoresist layer.

[0031] Typically, the step of the step of forming a plurality of emission cones within the ILD cavities comprises using metallic evaporation to deposit cones of metal within the ILD cavities.

[0032] BRIEF DESCRIPTION OF THE FIGURES

[0033] For a better understanding of the embodiments and to show how it may be carried into effect, reference will now be made, purely by way of example, to the accompanying drawings.

[0034] With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of selected embodiments only, and are presented in the cause of providing what is believed to be the most useful and readily understood description of the principles and conceptual aspects. In this regard, no attempt is made to show structural details in more detail than is necessary for a fundamental understanding; the description taken with the drawings making apparent to those skilled in the art how the various selected embodiments may be put into practice. In the accompanying drawings:

[0035] Fig. 1A schematically represents a cross section through an example of an x-ray vacuum tube including a current leakage inhibiting electron emitter array chip of the disclosure;

[0036] Fig. 1 B schematically represents the current leakage inhibiting electron emitter array chip having a sputterproof element for preventing deposition of a continuous conducting path between the gate electrode and the cathode electrode;

[0037] Fig. 2 is a graph of gate leakage current against gate voltage for a prior art electron emitter array chip indicating how performance of the chip deteriorates and the leakage conductivity increases as voltage pulses are applied for progressively longer durations;

[0038] Figs. 3A-F schematically illustrate various stages during the manufacture of an FEA chip;

[0039] Figs 3G-I show a scanning transmission electron microscopic image of a section through an electron emitter array of the prior art showing a layer of conducting material deposited over the surface of the ILD forming a continuous conducting path between the gate electrode and the cathode electrode;

[0040] Figs. 4A-C schematically represent a cross section of adjacent emitter tips and ILDs of a prior art electron emitter and illustrate how sputtering of conducting material dislodged from the emitter tips may give rise to may a continuous conducting path between the gate electrode and the cathode electrode in a prior art electron emitter;

[0041] Figs. 5A-C schematically represent a cross section of adjacent emitter tips and ILDs of a current leakage inhibiting electron emitter array chip of the current disclosure and illustrate how a notched ILD may sputterproof the ILD by preventing deposition of a continuous conducting path between the gate electrode and the cathode electrode; Fig. 5D is a schematic top view representation of an embodiment of a current leakage inhibiting electron emitter array chip of the current disclosure indicating possible relative dimensions of gate electrode windows, ILD cavities and the barrier notch of the current disclosure;

[0042] Fig. 5E is a schematic top view representation of the embodiment of the current leakage inhibiting electron emitter array chip of Fig. 5D with the gate electrode removed;

[0043] Figs. 6A-F schematically illustrate various stages during the manufacture of a current leakage inhibiting electron emitting construct including a conformal isolation layer;

[0044] Fig. 7 schematically represents a cross section of an emitter tip and ILDs of a current leakage inhibiting electron emitter array chip of the current disclosure with the emitter tip and ILDs encapsulated by a layer of Hafnium (IV) oxide (HfO2);

[0045] Figs. 8A-C schematically illustrates how the HfO2 encapsulated emitter tip and ILDs may prevent deposition of a conducting path between the gate electrode and the cathode electrode; and

[0046] Fig. 9 schematically represents a cross section of an emitter tip and ILDs of a current leakage inhibiting electron emitter array chip of the current disclosure with the notched ILD and the emitter tip and ILDs encapsulated by a layer of Hafnium(IV) oxide (HfO2).

[0047] DETAILED DESCRIPTION

[0048] Aspects of the present disclosure relate to systems and methods for reducing current leakage in cold cathode x-ray emission tubes. A current leakage inhibiting electron emitter array chip is introduced which includes a sputterproofing element such as a sputter resistant layer, a notched dielectric or the like for preventing the build up of a conductive path across the isolation layer between a gate electrode and a cathode substrate.

[0049] In one example, a current leakage inhibiting electron emitter array chip includes a sputterproofing element having a notched interlevel dielectric (ILD) to prevent sputtered conducting material depositing a conducting bridge across the ILD from the gate electrode to the cathode electrode and emitter tips.

[0050] In another example, a current leakage inhibiting electron emitter array chip includes a sputterproofing element having an insulating layer of Hafnium(IV) oxide (HfO2) encapsulating the gate electrode layer the emitter tips and the ILD cavity walls and which forms an isolation layer over the Gate Layer surface, preventing (or minimizing) the leakage path between the base of the emitter cone and the bottom of the Gate Layer.

[0051] As required, detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely examples of the invention that may be embodied in various and alternative forms. The figures are not necessarily to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention.

[0052] As appropriate, in various embodiments of the disclosure, one or more tasks as described herein may be performed by a data processor, such as a computing platform or distributed computing system for executing a plurality of instructions. Optionally, the data processor includes or accesses a volatile memory for storing instructions, data or the like. Additionally or alternatively, the data processor may access a non-volatile storage, for example, a magnetic hard disk, flash-drive, removable media or the like, for storing instructions and / or data.

[0053] It is particularly noted that the systems and methods of the disclosure herein may not be limited in its application to the details of construction and the arrangement of the components or methods set forth in the description or illustrated in the drawings and examples. The systems and methods of the disclosure may be capable of other embodiments, or of being practiced and carried out in various ways and technologies.

[0054] Alternative methods and materials similar or equivalent to those described herein may be used in the practice or testing of embodiments of the disclosure. Nevertheless, particular methods and materials described herein for illustrative purposes only. The materials, methods, and examples not intended to be necessarily limiting. Accordingly, various embodiments may omit, substitute, or add various procedures or components as appropriate. For instance, the methods may be performed in an order different from described, and that various steps may be added, omitted or combined. In addition, aspects and components described with respect to certain embodiments may be combined in various other embodiments.

[0055] Reference is now made to Fig. 1 A which is a schematic cross section representation of an example of an x-ray vacuum tube 10 including a current leakage inhibiting electron emitter array chip 100 of the disclosure.

[0056] The x-ray vacuum tube 10 includes a cold cathode electron source 100, a gate electrode 20 and a target anode 40 all held within a sealed glass chamber from which most of the air has been evacuated.

[0057] A beam of electrons may be produced by the cold cathode electron source 100 and directed towards a focal point on the anode target 40 such that x-rays may be produced.

[0058] The cold cathode electron source 100 may be a field array emission chip such as a gated cone electron source having cones (“emitter tips”) arranged in an array, each emitter tip being surrounded by an opening in the gate electrode (a “gate hole”), a Spindt type electron source, a carbon nanotube (CNT) type electron source, a metal-insulator-metal (MIM) type electron source or a metal-insulator-semiconductor (MIS) type electron source. In particular embodiments, the electron source may be a Spindt type electron source.

[0059] It is particularly noted that although ideally all air is evacuated from the glass chamber of the vacuum tube 10. In practice, trace air molecules are typically left in the tube even after most of the air has been evacuated. It has been surprisingly found that the trace molecules of air can have a detrimental effect on the efficiency of the x-ray tube 10 and may cause deterioration of the electrical properties of the emitter chip over time as described herein below.

[0060] Accordingly, it is a feature of the current invention to provide a current leakage inhibiting electron emitter array chip 100 with a sputterproof element such as a notched interlevel dielectric (ILD) or a insulating encapsulation layer for preventing conducting material which is deposited on the ILD over time from building up into a continuous conducting path between the gate electrode and the cathode electrode.

[0061] Fig. 1 B schematically represents such a current leakage inhibiting electron emitter array chip 100, the emitter chip 100 may be bound to the substrate using metal bonding or the like.

[0062] The current leakage inhibiting electron emitter array chip 100 is a field array emission chip such as a gated cone electron source having cones 102 arranged in an array and situated in cavities within an interlevel dielectric layer (ILD) 105 sandwiched between a gate electrode 103 and a cathode electrode 107.

[0063] It is a particular feature of the current leakage inhibiting electron emitter array chip 100 that the cavity walls of the ILD cavity are adapted so as to reduce current leakage between the gate electrode and the cathode electrode.

[0064] An active area of the electron emitting construct may comprise a substrate, a cathode electrode, an isolative interlevel dielectric layer ILD, a gated cone electron source, and a gate electrode. The active area may be defined as the area occupied by the gated cone electron source and / or the corresponding gate electrode.

[0065] The gated cone electron source 100 may comprise a plurality of emitter tips 102 arranged in an array. The gated cone electron source 100 may further comprise an interlevel dielectric (ILD) layer 107 having a plurality of ILD cavities, with an emitter tip 102 being situated at each ILD cavity. The ILD 107 may further serve as a support for the gate electrode 103 situated thereupon.

[0066] The emitter tip 102 may be constructed of, e.g., chromium, molybdenum or the like. Each emitter tip 102 may be about 500 nanometers (nm), about 400 nm, about 300 nm, about 200 nm, about 100 nm, less than 500 nm, less than 400 nm, less than 300 nm, less than 200 nm, less than 100 nm, between 100 and 300 nm, or between 200 and 400 nm in height. Each emitter tip 102 may be about 500 nm, about 400 nm, about 300 nm, about 200 nm, about 100 nm, less than 500 nm, less than 400 nm, less than 300 nm, less than 200 nm, less than 100 nm, between 100 and 300 nm, or between 200 and 400 nm in width at the base. In a particular embodiment, the emitter tip 102 may be less than 300 nm in height and less than 300 nm in width at the base.

[0067] The gate electrode 103 may comprise a plurality of gate holes. The gate electrode 103 may be constructed out of a conductive material such as chromium, niobium or the like. Typically, the position of the gate holes corresponds to the position of the ILD cavities and the emitter tips, such that each emitter tip is configured to emit an electron beam outwards out of the gate hole. The gate hole may have a diameter of between 50 and 500 nanometers, between 100 and 400 nanometers, between 150 and 250 nanometers, about 100 nanometers, about 150 nanometers, about 175 nanometers, about 200 nanometers, about 225 nanometers, about 250 nanometers, about 300 nanometers, about 350 nanometers, less than 300 nanometers, less than 250 nanometers, less than 200 nanometers, less than 150 nanometers, and less than 100 nanometers.

[0068] The gate electrode 103 may be conductively connected to a voltage source via the gate interconnect lead. The gate electrode 103 may have a thickness of about 50 nanometers (nm), about 60 nm, about 70 nm, about 80 nm, about 90 nm, about 100 nm, about 125, between 50 nm and 125 nm or between 80 nm and 100 nm. The gate interconnect lead 64 may have a thickness of between 0.5 microns and 20 microns. As such, the gate electrode 103 is thinner than the gate interconnect lead. Due to the thinness, as well as the presence of the gate holes, the resistance of the gate electrode is substantially higher than the resistance of the gate interconnect lead.

[0069] It has surprisingly been found that typical electron emitter array chips often deteriorate over time. Referring now to the graph of Fig. 2 which shows a plot of gate leakage current against the number of pulses of gate voltage for a typical electron emitter array chip. It is noted that the slope of the graph indicates the ILD conductivity. Accordingly, it is clear that the slope increases as more voltage pulses are applied ILD conductivity increases to the detriment to the performance of the chip. This phenomenon can be explained by postulating that a layer of conductive material is deposited over the surface of the ILD creating a conductive path bridging over the dielectric insulating layer.

[0070] Reference is now made to Figs. 3A-F which illustrate various stages during the manufacture of an FEA chip. In particular, Fig. 3A shows a schematic cross section through a layered wafer produced by deposition of an isolation layer which will become the ILD upon a substrate and the deposition of a gate metal layer on top of the isolation layer.

[0071] As shown in Fig. 3B photolithographic techniques may be used to lay a photoresist layer over the gate metal layer having gaps where cones will be situated in cavities of the isolation layer are required. Dryetching of the isolation layer produces these cavities as required.

[0072] Fig. 3C is another cross section illustrating the wafer following removal of the photoresist layer and wet etching used to shape the walls of the cavities ready for cones to be formed therein.

[0073] Fig. 3D shows how molybdenum evaporation forms cones within the cavities along with a top layer of molybdenum layer which can be removed later, as shown in Fig. 3E. Referring now to Figs 3G-I which show a scanning transmission electron microscopic image of a section through an electron emitter array of the prior art at various magnifications. The image shows a typical molybdenum Spindt-type gated cone electron source in which the ILD is not adapted to reduce current leakage.

[0074] Fig. 3G at the broadest field of view, the array 300 of molybdenum Spindt-type cones 312 can be seen each occupying a cavity within a silicon ILD 314 with their tips extending beyond the window in a chromium gate electrode.

[0075] Fig. 3H shows a selected region 310 which shows a row of six cones within their cavities and highlights the ILD cavity walls which are made of non-conducting dielectric material to maintain electrical isolation between the gate electrode layer and the substrate layer to which the emitter cones and the cathode electrode are conductively connected.

[0076] Fig. 3I focusses on the selected region 320 which shows the ILD layer 340 between two electron cones 360A, 360B. At this magnification, a dark line 342 is clearly visible over the ILD surface indicating a layer of conducting material creating a conductive path bridging between the gate electrode and the emitter cones. Surprisingly, Energy dispersive X-ray (EDX) mapping of the cross section reveals the conductive layer to be formed of molybdenum.

[0077] Deposition of the molybdenum conducting layer is the surprising consequence of sputtering of molybdenum from the emitter tips as a result of trace amounts of air in the x-ray tube. A model for such a process is presented with reference to Figs. 4A-C, which schematically represent a cross section 400 of adjacent emitter tips and ILDs of a Spindt-type electron emitter.

[0078] Fig. 4A illustrates how electrons emitted from the emitter tips 402 may ionize air molecules 404 within an imperfect X-ray vacuum tube. When the emitted electrons collide with the air molecules, the electron strips the air molecules of its other electrons generating positively charged ions. Fig. 4B illustrates how positively charged ions 406, accelerated towards the cathode, may collide with the emitter cones 402. The collision may cause molybdenum material of the cones to sputter therefrom. The sputtering of dislodged conductive molybdenum from the emitters leads to the deposition of conductive molybdenum material upon the adjacent surfaces of the insulating ILD cavity walls.

[0079] As shown in Fig. 4G, over time this sputtering may result in the build-up of a molybdenum conductive layer 408 over the surface of the cavity walls thereby creating a continuous conductive path bridging between the emitter tips and the gate electrode. Accordingly, a continuous conducting path develops between the gate electrode and the cathode electrode.

[0080] It is therefore a particular aspect of the current invention to provide a solution to the current leakage problem in imperfect vacuum tubes of X-ray emitters by inhibiting the development of the continuous conducting path over time by the sputtered molybdenum.

[0081] Accordingly, a current leakage inhibiting electron emitting construct is introduced for use in an imperfect vacuum tube of an X-ray emitter. The current leakage inhibiting electron emitting construct includes a substrate, a cathode electrode, an isolative layer, a gated cone electron source and a gate electrode, a sputterproofing element and an adapted non-conducting interlevel dielectric (ILD).

[0082] Various sputterproofing elements are described herein such as a notched ILD, or an insulating encapsulation layer of oxide, of Hafnium (IV) oxide (HfO2) or the like which may be used to prevent sputtering from developing

[0083] The non-conducting interlevel dielectric (ILD) layer is configured to support the gate electrode and further to conductively isolate the gate electrode from the cathode electrode. A plurality of emitter tips are each situated in a cavity within the ILD and are conductively connected to the cathode electrode. Referring now to Figs. 5A-C a schematic cross section 500 is presented of adjacent emitter tips 502 and notched ILDs 504 of a current leakage inhibiting electron emitter array chip of the current disclosure. The notched ILD 504 of Figs. 5A-C may be contrasted with the smooth cavity walls of the ILD of Fig. 4A-C to illustrate how the notched ILD may prevent deposition of a continuous conducting path between the gate electrode and the cathode electrode.

[0084] Referring to Fig 5A, similarly to what is shown in Fig. 4A, electrons emitted from the emitter tips 502 may ionize air molecules 506 within the imperfect X-ray vacuum tube. Fig. 5B illustrates how positively charged ions 508 are still accelerated towards the cathode and may collide with the emitter cones in a similar manner to the standard emitter shown in Fig. 4B. Although the collision of ions with the emitter may still cause molybdenum material of the cones to sputter therefrom, it is noted that the notched ILD prevents the deposition of conductive molybdenum material upon the internal surfaces of notch which do not have direct line of sight to the adjacent emitter cones.

[0085] With particular reference to Fig. 5C, it is shown that over time molybdenum sputtering still results in the build-up of a molybdenum conductive layer 510 over the surface of the cavity walls, however the conductive layer is interrupted by the groove 512 thereby preventing a continuous conductive path from bridging between the emitter tips and the gate electrode. Accordingly, the conductivity of the ILD layer remains low and current leakage is inhibited.

[0086] The dimensions of the notch are typically selected such that there is at least one continuous sputterproof zone forming a ring along the surface of the ILD cavity wall circumscribing the emitter tip to prevent deposition of conducting material thereupon. The continuous sputterproof ring may be defined by a region around a locus of points within the notch which do not have a line of sign to the emitter tip and which circumscribe the emitter tip.

[0087] Reference is now made to Fig. 5D and 5E which are schematic top views of an embodiment of the current leakage inhibiting electron emitter array chip of the current disclosure indicating possible relative dimensions of gate electrode windows 606, ILD cavities 605 and the barrier notch 609 of the current disclosure. For ease of illustration Fig. 5E is a schematic top view representation of the embodiment of the current leakage inhibiting electron emitter array chip of Fig. 5D with the gate electrode removed so that the ILD cavities are apparent.

[0088] Emitter tips are situated within a two-dimensional array of cavities 605 within the ILD layer. The gate electrode is aligned such that an array of windows 606 coincides with the emitter tips 603. Each window in the gate electrode 606 has a diameter smaller than the diameter of the ILD cavity wall 605 which it overhangs.

[0089] It is noted that the notches 609 extend into the ILD cavity wall to a depth sufficient to prevent the deposition of the conductive layer. The depth of these notches may be to about a half the distance between adjacent tips so as not to damage the mechanical integrity of the ILD layer. Alternatively, the diagonal distance between tips may be sufficient to support the layer even if the notches of adjacent cavities do encroach (or overlap) upon each other.

[0090] One embodiment of the current leakage inhibiting electron emitting construct may be formed by introducing an additional stage during manufacture of the wafer. Reference is now made to Figs. 6A-F which illustrate various stages during the manufacture of a current leakage inhibiting electron emitting construct including a conformal isolation layer.

[0091] It is noted that the initial stages of Figs 6A-E correspond to similar stages in the method of manufacture of the FEA chip of Figs. 3A-E. However, Fig. 6F illustrates an additional stage which may be required before the addition of the gold pads. A conformal isolation layer is deposited which encapsulates the conductive gate layer and the cones slope all around. This conformal isolation layer may prevents any continuous leakage path that may form between the base of the cones and the bottom of the gate layer. It is important to deposit the conformal isolation layer during wafer manufacture and before attaching the gold pads so as not to encapsulate the conducting surfaces of the contacts. Alternatively, still another additional step may be required of clearing of the pads by etching the deposited isolation layer may be required for chip connectivity.

[0092] One embodiment of the present disclosure is illustrated in Fig. 7 which schematically represents a cross section 700 of an emitter tip 702 and ILDs 704 of a current leakage inhibiting electron emitter array chip with the emitter tip and ILDs encapsulated by a layer of Hafnium(IV) oxide (HfO2) 706. The layer of HfO2 prevents the deposition of conducting molybdenum layer over the emitter tips and ILDs. This prevents or minimizes the formation of a conducting path between the gate electrode and the cathode electrode.

[0093] The HfO2 has several material properties which provide a longer device lifetime, more stable device performance, and improved device efficiency. HfO2 being a good insulator, slows down the FEA device deterioration rate by generating an isolation layer over the Gate Layer surface, preventing (or minimizing) the formation of leakage path between the base of the cone 710 and the bottom of the Gate Layer 712 (even if there is a shunt layer buildup). HfO2 is an efficient barrier layer that can withstand a very high temperature. It is an efficient barrier layer that may protect the metallic cones (Molybdenum or others) and the metallic Gate Layer from surface oxidation.

[0094] In addition, HfO2 has a relatively low Work Function and high dielectric constant, both of which have been found to enhance electron emission and reduce the required Gate Voltage (for a given emission current).

[0095] The work function of a material determines how much energy is required by a material to release electrons. Accordingly, it has been found that coating the emission cones with a material having a low work function, such as HfO2 or the like, reduces the energy required to release electrons consequently increasing the kinetic energy of the released electrons.

[0096] Moreover, increasing the dielectric constant of a medium increases the field produced at a given voltage, accordingly by coating the gate electron in a high dielectric material such as HfO2 which has a high permittivity with a dielectric constant of about 20-25.

[0097] Although the example of HfO2 is given above for illustrative purposes only, coatings of embodiments of the present invention may be provided using various material or compounds having high permittivity and low work function such as Hafnium(IV) oxide (HfO2), Chromium (IV) oxide (CrO2), Titanium(IV) oxide (TiO2) and Zirconium(IV) oxide (ZrO2).

[0098] Referring now to Figs. 8A-C a schematic cross section 800 is presented of an encapsulated emitter tip 802 and ILDs 804 of a current leakage inhibiting electron emitter array chip of the current disclosure. The encapsulated emitter tip 802 and ILDs 804 of Figs. 8A-C may be contrasted with the non-encapsulated emitter tip and ILDs of Fig. 4A-C to illustrate how the HfO2 layer may prevent deposition of a conducting path between the gate electrode and the cathode electrode.

[0099] Referring to Fig 8A, similarly to what is shown in Fig. 4A, electrons emitted from the emitter tips 802 may ionize air molecules 806 within the imperfect X-ray vacuum tube. Fig. 8B illustrates how positively charged ions 808 are still accelerated towards the cathode and may collide with the emitter cones in a similar manner to the standard emitter shown in Fig. 4B. Due to the insulated HfO2 layer, the collision of ions with the emitter will not cause the molybdenum material of the cones to sputter therefrom, consequently preventing the deposition of conductive molybdenum material upon the emitter cones and ILDs as shown in Fig. 8C which shows only the insulated HfO2 layer over the emitter cones and ILDs. Accordingly, the conductivity of the ILD layer remains low and current leakage is inhibited.

[0100] Fig. 9 illustrates another embodiment of the present disclosure which schematically represents a cross section of an emitter tip and ILDs of a current leakage inhibiting electron emitter array chip comprising the notched ILD 902 and the emitter tip and ILDs encapsulated by a layer of Hafnium(IV) oxide (HfO2) 904. The dual provision will further minimize the leakage current. In case there is a chance of the deposition of a thin conducting molybdenum layer in spite of the HfO2 encapsulation, the notched ILD will prevent the deposition of a continuous conducting layer. The combined provision can further slow down the FEA device deterioration rate prolonging the device’s lifetime.

[0101] Technical and scientific terms used herein should have the same meaning as commonly understood by one of ordinary skill in the art to which the disclosure pertains. Nevertheless, it is expected that during the life of a patent maturing from this application many relevant systems and methods will be developed. Accordingly, the scope of the terms such as computing unit, network, display, memory, server and the like are intended to include all such new technologies a priori.

[0102] As used herein the term “about” refers to at least ± 10 %.

[0103] The terms "comprises", "comprising", "includes", "including", “having” and their conjugates mean "including but not limited to" and indicate that the components listed are included, but not generally to the exclusion of other components. Such terms encompass the terms "consisting of' and "consisting essentially of".

[0104] The phrase "consisting essentially of' means that the composition or method may include additional ingredients and / or steps, but only if the additional ingredients and / or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

[0105] As used herein, the singular form "a", "an" and "the" may include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

[0106] The word “exemplary” is used herein to mean “serving as an example, instance or illustration”. Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or to exclude the incorporation of features from other embodiments.

[0107] The word “optionally” is used herein to mean “is provided in some embodiments and not provided in other embodiments”. Any particular embodiment of the disclosure may include a plurality of “optional” features unless such features conflict.

[0108] Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases “ranging / ranges between” a first indicate number and a second indicate number and “ranging / ranges from” a first indicate number “to” a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals therebetween. It should be understood, therefore, that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the disclosure. Accordingly, the description of a range should be considered to have specifically disclosed all the possible sub-ranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1 , 2, 3, 4, 5, and 6 as well as non-integral intermediate values. This applies regardless of the breadth of the range.

[0109] It is appreciated that certain features of the disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination or as suitable in any other described embodiment of the disclosure. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments unless the embodiment is inoperative without those elements. Although the disclosure has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims. All publications, patents and patent applications mentioned in this specification are herein incorporated in their entirety by reference into the specification, to the same extent as if each individual publication, patent or patent application was specifically and individually indicated to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present disclosure. To the extent that section headings are used, they should not be construed as necessarily limiting.

[0110] The scope of the disclosed subject matter is defined by the appended claims and includes both combinations and sub combinations of the various features described hereinabove as well as variations and modifications thereof, which would occur to persons skilled in the art upon reading the foregoing description.

Claims

CLAIMS1. An apparatus for reducing a leakage current between a gate electrode and a cathode electrode of an electron emitter array chip, the apparatus comprising: a non-conductive interlevel dielectric layer (ILD) comprising a plurality of ILD cavities sandwiched between the gate electrode and the cathode electrode; and a gated cone electron source having a plurality of emitter tips arranged in an array and situated in cavities within the interlevel dielectric layer (ILD); a sputterproofing element for preventing formation of a conducting path connecting the gate electrode and the cathode electrode formed by deposition of conducting material sputtered from the emitter tips upon the ILD cavity wall surfaces.

2. The apparatus of claim 1 wherein the sputterproofing element comprises an insulating layer encapsulating the gate electrode.

3. The apparatus of claim 1 wherein the sputterproofing element comprises an insulating layer encapsulating the emitter tips.

4. The apparatus of claim 1 wherein the sputterproofing element comprises an insulating layer encapsulating the ILD cavity wall surfaces.

5. The apparatus of claim 1 wherein the sputterproofing element comprises an insulating layer encapsulating the gate electrode wherein the insulating layer comprising at least one oxide material selected from a group consisting of Hafnium(IV) oxide (HfO2), Chromium (IV) oxide (CrO2), Titanium(IV) oxide (TiO2) and Zirconium(IV) oxide (ZrO2) and combination thereof.

6. The apparatus of claim 1 wherein the sputterproofing element comprises an insulating layer encapsulating the gate electrode wherein the material of the insulating layer is characterized by a low work function.

7. The apparatus of claim 1 wherein the sputterproofing element comprises an insulating layer encapsulating the gate electrode wherein the material of the insulating layer is characterized by a high dielectric constant.

8. The apparatus of claim 1 wherein the sputterproofing element comprises an insulating layer encapsulating the gate electrode wherein the material of the insulating layer is characterized by being able to withstand a high temperature.

9. The apparatus of claim 1 , wherein the emitter tips are made of chromium or molybdenum.

10. The apparatus of claim 1 wherein the sputterproofing element comprises a barrier notch provided on cavity walls of the ILDs to prevent the formation of a continuous conducting path connecting the gate electrode and the cathode electrode formed by deposition of conducting material sputtered from the emitter tips upon the ILD cavity wall surfaces.

11. The apparatus of claim 10, wherein the barrier notch on the ILD walls is configured to prevent the deposition of conducting material upon the internal surfaces of notch which do not have direct line of sight to the adjacent emitter cones.

12. The apparatus of claim 10, wherein the barrier notch on the ILD walls is configured to keep the conductivity of ILD layer low inhibiting the leakage current between the gate electrode and the cathode electrode.

13. The apparatus of claim 10, wherein the dimension of the barrier notch is selected such that there is at least one continuous sputterproof zone forming a ring along the surface of the ILD cavity wall circumscribingthe emitter tip to prevent deposition of conducting material thereupon, wherein the continuous sputterproof ring is a region around a locus of points within the notch which do not have a line of sign to the emitter tip and which circumscribe the emitter tip.

14. The apparatus of claim 10, wherein the depth of the barrier notch within the ILD cavity wall is selected to be sufficient to prevent the deposition of the conductive layer and prevent the damage of mechanical integrity of the ILD layer.

15. The apparatus of claim 14, wherein the depth of the barrier notch within the ILD cavity wall is about half the distance between adjacent emitter tips.

16. The apparatus of claim 10, wherein the depth of the barrier notch within the ILD cavity wall is selected such that a diagonal distance between the adjacent emitter tips may be sufficient to support the ILD layer in case the barrier notches of adjacent ILD cavity wall overlap each other.

17. An apparatus for reducing a leakage current between a gate electrode and a cathode electrode of an electron emitter array chip, the apparatus comprising: a non-conductive interlevel dielectric layer (ILD) comprising a plurality of ILD cavities sandwiched between the gate electrode and the cathode electrode; and a gated cone electron source having a plurality of emitter tips arranged in an array and situated in cavities within the interlevel dielectric layer (ILD); wherein a layer of an insulating material having high dielectric constant is encapsulated on the emitter tips and cavity walls of the ILDs to prevent the formation of a conducting path connecting the gate electrode and the cathode electrode formed by deposition of conducting material sputtered from the emitter tips upon the ILD wall surface.

18. The apparatus of claim 17, wherein the emitter tips are made of chromium or molybdenum.

19. The apparatus of claim 17, wherein the insulating material is selected from a group of Hafnium(IV) oxide (HfO2), Titanium(IV) oxide (TiO2) and Zirconium(IV) oxide (ZrO2).

20. The apparatus of claim 17, wherein the insulating layer is configured to slow down the apparatus deterioration rate by generating an isolation layer over a gate layer surface, preventing or minimizing the current leakage between the base of the gated cone and the bottom of the gate electrode.21 . The apparatus of claim 17, wherein the insulating layer is configured as an efficient barrier layer that can withstand a very high temperature and is configured to protect the metallic gated cones and metallic gate layer from surface oxidation.

22. The apparatus of claim 17, wherein the insulating layer has a low Work Function and high dielectric constant.

23. The apparatus of claim 17, wherein the insulating layer is configured to enhance electron emission from the emitter tips and reduce the required gate voltage for a given emission current.

24. An apparatus for reducing a leakage current between a gate electrode and a cathode electrode of an electron emitter array chip, the apparatus comprising: a non-conductive interlevel dielectric layer (ILD) comprising a plurality of ILD cavities sandwiched between the gate electrode and the cathode electrode; anda gated cone electron source having a plurality of emitter tips arranged in an array and situated in cavities within the interlevel dielectric layer (ILD); wherein a barrier notch is provided on cavity walls of the ILDs, wherein a layer of an insulating material having high dielectric constant is encapsulated on the emitter tips and cavity walls of the ILDs, and wherein the barrier notch on cavity walls of the ILDs and the layer of insulating material on the emitter tips and cavity walls of the ILDs prevent the formation of a conducting path connecting the gate electrode and the cathode electrode formed by deposition of conducting material sputtered from the emitter tips upon the ILD wall surface.

25. A method for reducing leakage current between a gate electrode and a cathode electrode of an electron emitter array chip, the method comprising: providing a wafer comprising a substrate, a non-conductive interlevel dielectric layer (ILD) and a metallic gate layer; using lithography to etch a plurality of windows through the metallic gate layer and a plurality of ILD cavities within the ILD; shaping internal walls of the ILD cavities; forming a plurality of emission cones within the ILD cavities; and sputterproofing the internal walls of the ILD cavities thereby preventing formation of a conducting path connecting the gate electrode and the cathode electrode formed by deposition of conducting material sputtered from emitter tips upon ILD cavity wall surfaces.

26. The method of claim 25 wherein the step of sputterproofing comprises depositing an insulating layer encapsulating the gate electrode.

27. The method of claim 25 wherein the step of sputterproofing comprises depositing an insulating layer encapsulating the emitter tips.

28. The method of claim 25 wherein the step of sputterproofing comprises depositing an insulating layer encapsulating the ILD cavity wall surfaces.

29. . The method of claim 25 wherein the step of sputterproofing comprises depositing an insulating layer encapsulating the gate electrode wherein the insulating layer comprising at least one oxide material selected from a group consisting of Hafnium(IV) oxide (HfO2), Chromium (IV) oxide (CrO2), Titanium(IV) oxide (TiO2) and Zirconium(IV) oxide (ZrO2) and combination thereof.

30. . The method of claim 25 wherein the step of sputterproofing comprises depositing an insulating layer encapsulating the gate electrode wherein the material of the insulating layer is characterized by a low work function.

31. The method of claim 25 wherein the step of sputterproofing comprises depositing an insulating layer encapsulating the gate electrode wherein the material of the insulating layer is characterized by a high dielectric constant.

32. The method of claim 25 wherein the step of sputterproofing comprises depositing an insulating layer encapsulating the gate electrode wherein the material of the insulating layer is characterized by being able to withstand a high temperature.

33. The method of claim 25 wherein the step of sputterproofing comprises depositing a conformal isolation layer encapsulating the gate electrode, the emitter tips and the ILD cavity wall surfaces.

34. The method of claim 25 wherein the step of using lithography to etch a plurality of windows through the metallic gate layer and a plurality of ILD cavities within the ILD comprises laying a photoresist layer over the metallic gate layer having gaps where cavities of the isolation layer are required; dry-etching of the isolation layer; and removing the photoresist layer.

35. The method of claim 25 wherein the step of forming a plurality of emission cones within the ILD cavities comprises using metallic evaporation to deposit cones of metal within the ILD cavities.

36. The method of claim 25 wherein the step of forming a plurality of emission cones within the ILD cavities comprises using molybdenum evaporation to deposit cones of molybdenum within the ILD cavities.

37. The method of claim 25 wherein the step of forming a plurality of emission cones within the ILD cavities comprises using chromium evaporation to deposit cones of chromium within the ILD cavities.

38. The method of claim 25 wherein the step of sputterproofing comprises etching a barrier notch within the cavity walls of the ILDs to prevent the formation of a continuous conducting path connecting the gate electrode and the cathode electrode formed by deposition of conducting material sputtered from the emitter tips upon the ILD cavity wall surfaces.

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