Substrate comprising a thick buried dielectric layer and method for preparing such a substrate

Abstract

The invention relates to a final substrate (S) comprising, consecutively and in contact with one another, an upper layer (5) made of semiconductor material, a dielectric layer (4) having a thickness greater than 200 nm, an electrical charge trapping layer (2) and a base substrate (3). The final substrate (S) has a curvature of less than 60 micrometres, preferably less than 40 micrometres. An exposed surface of the upper layer (5) has a roughness of less than 0.3 nm as a root mean square measurement over a field of 30 micrometres by 30 micrometres. The invention also relates to a method for preparing such a substrate.

Description

SUBSTRATE COMPRISING A THICK BURIED DIELECTRIC LAYER AND METHOD FOR PREPARING SUCH A SUBSTRATE FIELD OF THE INVENTION

[0001] The present invention relates to a substrate of the semiconductor-on-insulator type comprising a charge trapping layer, the insulating (or dielectric) layer having a relatively large thickness, greater than 200 nm. These substrates find a notable application in the field of integrated radiofrequency devices, i.e. electronic devices processing signals whose frequency is between approximately 3 kHz and 300 GHz, for example in the field of telecommunications (telephony, Wi-Fi, Bluetooth, etc.). These substrates also find their application in the field of photonics. The invention also relates to a method for manufacturing such a substrate. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Document WO2022023630 reveals that the formation of a final substrate of the semiconductor-on-insulator type comprising a charge trapping layer and a thick dielectric layer (greater than 200 nm according to this document) is particularly delicate. According to the introduction of this document, it is industrially preferable to place this dielectric layer on the support substrate of the final substrate, and the dielectric layer, made of silicon oxide, can be obtained by oxidation of a surface portion of the electric charge trapping layer. The oxidation step tends to deform the support substrate and to cause a significant curvature to appear (designated by the English term "bow" in the terminology used in the field of semiconductors which is defined as the deviation between a central point of the median surface of the substrate relative to a reference plane).This curvature is generally measured by interferometry, for example using equipment such as WaferSight™ supplied by the company KLA. The presence of such curvature makes the step of transferring the upper layer of the substrate, and more generally the handling of the support substrate in the production line by conventional equipment, tricky. It is generally sought to limit this curvature to less than 60 micrometers or, preferably, less than 40 micrometers, for a disc-shaped substrate with a diameter of 300 mm.

[0003] Furthermore, it is essential in many applications that the exposed surface of the top layer be very smooth, and have a roughness well below 0.5 nm in root mean square measurement over an atomic force measurement field of 30 micrometers by 30 micrometers. To obtain a top layer having such roughness, it is known to apply to the substrate, after the transfer of the top layer to the support substrate, one or a plurality of thermal annealing operations in neutral or reducing atmospheres.

[0004] This may involve so-called "rapid" annealing ("rapid thermal anneal" according to the accepted Anglo-Saxon expression) consisting of exposing the exposed surface of the upper layer to the annealing atmosphere at temperature for a very short time, less than 2 minutes. The neutral or reducing atmosphere of the annealing chamber is suddenly heated to the treatment temperature which can reach 1200°C, then cooled during heating / cooling ramps which can exceed 50° / s. During this treatment, the substrate is held by its rear face in the furnace chamber, on a plurality of points of a support. The applicant has however observed that this type of annealing generates lines or planes of dislocations at the points of contact of the substrate with the support. These lines or planes of dislocations come from thermal stresses and gravitational stresses which this substrate undergoes during the very rapid thermal excursion which it undergoes.They sometimes make the substrate unsuitable for use in the following stages of manufacturing microelectronic components or, at the very least, can lead to the formation of non-functional components when these are placed in line with these defects.

[0005] As an alternative to rapid annealing, a long anneal can be applied during the finishing stage of substrate preparation, often referred to in the field as "batch annealing", as the substrates are generally placed in batches in the furnace chamber, in a horizontal or vertical arrangement. The atmosphere in the chamber is gradually raised, in gentle ramps of a few degrees per minute to reach a treatment temperature typically of the order of 1100°C. The treatment is continued for an extended period at this temperature, of the order of a few minutes to several hours. The gentleness of the ramps limits the thermal stresses experienced by the substrate and limits the appearance of dislocation lines or planes observed after rapid heat treatment.

[0006] The applicant observed, as reported on the graph of the, that the curvature of the substrate (on the ordinate of this graph) which is generated by the curvature of the support substrate after the oxidation of the trapping layer could be compensated by exposing the substrate during the finishing step to a high temperature (abscissa of the graph), strictly greater than 1050°C to decrease this curvature below 40 micrometers and approach 1100°C to pass below 30 micrometers of curvature. On the graph of the, the data collected at 1050°C, 1075°C and 1100°C were obtained at the end of long anneals, the data collected at 1200°C were obtained at the end of fast anneals.

[0007] The applicant also observed that the roughness of the exposed surface of the upper layer of the substrate tended to degrade with increasing temperature when the dielectric layer (formed by oxidation of the trapping layer of the support) has a thickness greater than 200 nm. This is revealed in the measurements reported in the graph in which reports the roughness of the exposed surface of the upper layer (measured by atomic force on a measuring field of 30 micrometers by 30 micrometers) at the center (reference "C") and at the edge (reference "B"), for increasing annealing temperatures. These anneals were carried out on final substrates each having a buried dielectric layer of 400 nm, obtained by oxidation of the trapping layer of the support substrate as previously explained. It is observed in this case that the roughness tends to increase almost exponentially with the annealing temperature.It appears that the stack forming the substrate becomes thermally unstable when the dielectric layer has a significant thickness, greater than 200 nm, this instability leading to a degradation of the state of the free surface of the substrate. The finishing heat treatment causes this thermal instability, possibly through stress relaxations stored in this stack, this relaxation manifesting itself on the surface of the upper layer by increased roughness.

[0008] Also, it does not seem easy to obtain a final substrate of the semiconductor on insulator type comprising a thick dielectric layer, with a thickness greater than 200nm, having both low roughness (less than the limit indicated in a previous passage) and low curvature, less for example than 60 micrometers and, advantageously, devoid of an excessive quantity of planes or dislocation lines. SUBJECT OF THE INVENTION

[0009] An aim of the invention is to provide a solution to this problem. More specifically, the invention provides a substrate comprising a thick buried dielectric layer, greater than 2000 nm, which has both low roughness and low curvature. The invention also provides a method for preparing such a substrate. BRIEF DESCRIPTION OF THE INVENTION

[0010] In order to achieve this aim, the subject of the invention proposes a method for preparing a final substrate comprising a thick buried dielectric layer, the method comprising: a step of preparing a support substrate comprising an electric charge trapping layer arranged on a base substrate; a step of forming a dielectric layer having a thickness greater than 200 nm on the electric charge trapping layer; a step of transferring an upper layer comprising a semiconductor material onto the dielectric layer; a step of finishing the exposed face of the upper layer.

[0011] According to the invention, the step of forming the dielectric layer is carried out by high-density plasma chemical vapor deposition and the finishing step comprises a first annealing carried out in a neutral or reducing atmosphere at a temperature above 1050°C for a duration of more than 30 minutes.

[0012] Surprisingly, this process makes it possible to obtain a final substrate with both reduced curvature and a satisfactory surface finish.

[0013] According to other advantageous and non-limiting characteristics of the invention, taken alone or in any technically feasible combination: the step of forming the dielectric layer comprises, after the high-density plasma chemical vapor deposition of the dielectric layer, a densification annealing of the support substrate; the densification annealing is carried out in a neutral atmosphere at a temperature below 1000°C and for a duration of less than 1 hour; the finishing step comprises, before and / or after the first annealing, a thinning of the upper layer; the thinning is carried out by sacrificial oxidation.the finishing step comprises a second annealing, the second annealing being carried out in a neutral or reducing atmosphere at a temperature above 1050°C for a duration of less than 2 minutes; the neutral or reducing atmosphere of the first annealing comprises or consists of argon; the step of forming the dielectric layer is devoid of polishing the exposed face of the dielectric layer; the semiconductor material is silicon; the dielectric layer is made of silicon dioxide; the dielectric layer has a thickness greater than or equal to 400 nm; the step of transferring the upper layer comprises a step of implanting so-called "light" species in a donor substrate to form a fragile plane there, the assembly of the donor substrate with the support substrate, and the fracture of the donor substrate at the fragile plane.

[0014] According to another aspect, the invention provides a final substrate comprising, successively in contact with each other, an upper layer of semiconductor material, a dielectric layer having a thickness greater than 200 nm, an electric charge trapping layer and a base substrate.

[0015] According to the invention, the final substrate has an exposed surface of the semiconductor material layer having a roughness of less than 0.3 nm in root mean square measurement over a field of 30 micrometers by 30 micrometers and a curvature of less than 60 micrometers, preferably less than 40 micrometers.

[0016] According to other advantageous and non-limiting characteristics of this other aspect of the invention, taken alone or in any technically feasible combination: the upper layer is made of silicon; the dielectric layer is made of silicon oxide; the final substrate is in the form of a disc of 300 mm or more in diameter; the final substrate has a cumulative length of planes or lines of dislocations, measured by deflectometry, less than 20 mm.

[0017] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0018]

[0019] Larepresents a graph relating the curvature of a silicon-on-insulator substrate according to the temperature of an anneal applied during a finishing step in the preparation of this substrate;

[0020]

[0021] Larepresents a graph relating, for a buried dielectric layer of 400nm, the roughness of the exposed surface of the upper layer of a final substrate according to the temperature of an anneal applied during a finishing step of preparation of this substrate;

[0022]

[0023] La represents a substrate in accordance with the invention;

[0024]

[0025]

[0026]

[0027]

[0028] Figures 4a, 4b, 4c, 4d show a method of preparing a final substrate according to the present invention;

[0029]

[0030]

[0031] Figures 5a, 5b respectively represent measurements of curvature and roughness carried out during experiments which led to the invention;

[0032]

[0033] Illustrates the benefit provided by the use of a "long" anneal, rather than a "fast" anneal in terms of dislocation-type defects in a manufacturing process according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0034] With reference to 1, a substrate S of an embodiment comprises a base substrate 3, an electric charge trapping layer 2 (referred to as a "trapping layer" in the remainder of this description) arranged on the base substrate 3, a dielectric layer 4 arranged on and directly in contact with the trapping layer 2 and an upper layer 5 arranged on the dielectric layer 4. The base substrate 3 provided with the charge trapping layer and the dielectric layer 4 forms a support substrate 1 of the final substrate S.

[0035] The substrate S (and therefore the support substrate 1) can take the form of a wafer, for example in the form of a disc with a diameter of 300 mm. The substrate has a curvature of less than 60 micrometers, preferably less than 40 micrometers, to make it compatible with the subsequent stages of component manufacturing.

[0036] The base substrate 3 has a thickness of several hundred microns. Preferably, the base substrate 3 has a high resistivity, greater than 100 or 1000 ohms.cm, and more preferably still greater than 3000 ohms.cm. This limits the density of charges, holes or electrons, which are likely to move in the base substrate 3, and therefore deteriorate the radiofrequency performance of the final substrate S. However, the invention is not limited to a base substrate 3 having such a resistivity, and it also provides RF performance advantages when the base substrate 3 has a more conformal resistivity, less than 1000 ohms.cm, of the order of a few hundred ohms.cm, or 100 ohms.cm or less.

[0037] For reasons of availability and cost, the base substrate 3 is preferably made of silicon, and in particular monocrystalline silicon. It may, for example, be a CZ substrate with a low interstitial oxygen content which, as is well known per se, has a resistivity which may be greater than 1000 ohms.cm. The base substrate 3 may alternatively be formed from another material: it may, for example, be sapphire, silicon carbide, silicon-germanium, III-V materials, glass, etc. Alternatively, it may also be a more standard monocrystalline CZ substrate, the resistivity of which is less than 1000 ohms.cm, or a CZ substrate with a high or medium interstitial oxygen content, which may be n- or p-doped and which has a resistivity which may be of the order of 500 ohms.cm or less.

[0038] The support substrate 1 also comprises a trapping layer 2, arranged on and directly in contact with the base substrate 3. The trapping layer 2 has a resistivity greater than 500 ohm.cm and preferably 1000 ohm.cm, and even more preferably greater than 10 kohm.cm. As is well known per se, the trapping layer has the function of trapping the charge carriers that may be present in the support 1 and of limiting their mobility. This is particularly the case when the substrate S comprises a semiconductor structure emitting an electromagnetic field penetrating into the support substrate 1, and therefore capable of interacting and making these charges mobile. The trapping layer 2 has a thickness typically between 1 micron and 15 microns, or even 20 microns.

[0039] The trapping layer 2 may, in general, consist of a non-monocrystalline semiconductor layer having structural defects such as dislocations, grain boundaries, amorphous zones, interstices, inclusions, pores, etc. These structural defects form traps for charges likely to circulate in the material, for example at the level of incomplete or dangling chemical bonds. This prevents conduction in the trapping layer, which consequently has a high resistivity.

[0040] For the same reasons of availability and cost that have already been mentioned, the trapping layer 2 is preferably made of polycrystalline silicon. But it can be made of or comprise another semiconducting and polycrystalline material. It is of course possible to provide for forming this charge trapping layer 2 by a technique other than that providing a layer formed of polycrystalline silicon. This layer can also comprise carbon or be made of or comprise silicon carbide or an alloy of silicon and carbon, for example in the form of interlayers inserted into a thickness of polycrystalline silicon. When the trapping layer 2 is made of silicon carbide or an alloy of silicon and carbon, its thickness is preferably between a few nm (for example 2 nm) and a few tens of nm (for example 50 nm).Alternatively, it may involve producing the electrical traps in layer 2 by ion bombardment of relatively heavy species (for example argon) in a surface portion of the base substrate 3 in order to create crystalline defects therein capable of trapping electrical charges. It is also possible to provide a charge trapping layer 2 formed of a porous material, for example by porosification of a surface portion of the base substrate 3 when the latter is made of silicon. The trapping layer may also comprise a silicon-rich oxide comprising an atomic concentration of silicon of between 50% and 99.9%. This silicon-rich oxide may also comprise nitrogen. It may also comprise inclusions of crystalline silicon having a size of less than 10 nm, and preferably less than 5 nm. Alternatively, it may be in a polycrystalline form and comprise amorphous inclusions.

[0041] In any case, trapping layer 2 has a high resistivity greater than 500 ohm.cm. For this purpose, trapping layer 2 is not intentionally doped, i.e. it has a charge-carrying dopant concentration of less than 10 E14 atoms per cubic centimeter. It can be rich in nitrogen or carbon in order to improve its resistivity characteristic.

[0042] Returning to the general description of the, the support substrate 1 also comprises a dielectric layer 4 directly arranged on the trapping layer 2. For example, the dielectric layer 4 may be made of or comprise silicon dioxide or silicon nitride. It may also be a stack of these materials. The thickness of the dielectric layer 4 may usually be between 10 nm and 10 microns, but in the context of the present description, this layer has a significant thickness, greater than 200 nm, and preferably between 200 nm and 1000 nm.

[0043] The substrate S comprises an upper layer 5, on and in contact with the dielectric layer 4 of the support substrate 1. The thin layer is usually made of monocrystalline silicon, but it could be any other material depending on the nature of the device intended to be formed there. When the substrate S is intended to receive integrated semiconductor components in the fields of electronics or photonics, the thin layer 5 can thus be composed of monocrystalline silicon, or any other monocrystalline semiconductor material such as germanium, silicon germanium, silicon carbide.

[0044] In all cases, and whatever the nature of the upper layer, it is very slightly rough, and its exposed surface has a roughness of less than 0.3 nm in mean square measurement over a field of 30 micrometers by 30 micrometers.

[0045] The ability to have a substrate with a thick buried dielectric (more than 200 nm) having both low surface roughness and low curvature forms a very remarkable aspect of the present invention. Furthermore, this substrate has a low density of dislocation planes or lines. These dislocation planes or lines can be measured by inspection equipment using a deflectometry technique, as is for example presented in document US7812942. It is generally sought to minimize the cumulative length of these dislocation planes or lines, for example below the threshold value of 20 mm, which is indeed the case for a substrate according to the invention. Substrate preparation

[0046] A method of preparing the substrate shown in Figures 4a to 4d is now presented.

[0047] In a first preparation step shown in the, the support substrate 1 is prepared. The production of the trapping layer 2 on the base substrate 3, when it is made of polycrystalline silicon or formed of a silicon-rich oxide, can be carried out with standard deposition equipment in the industry. It can thus be a deposition of the RPCVD type (acronym for the English expression "Remote Plasma enhanced Chemical Vapor Deposition" or chemical vapor deposition assisted by remote plasma) or of the PECVD type (acronym for the English expression "Plasma Enhanced Chemical Vapor Deposition" or chemical vapor deposition assisted by plasma). It can also be an LPCVD deposition (acronym for the English expression "Low Pressure Chemical Vapor Deposition" or chemical vapor deposition at subatmospheric pressure).But, as seen previously, the formation of the trapping layer on or in the base substrate 3 can be achieved in many other ways, for example by implantation of heavy species or by porosification of a surface layer of the base substrate 3.

[0048] Optionally, during this preparation step, the formation of a thin dielectric layer on the base substrate 3 may be provided, for example by oxidation or deposition of a thickness of oxide, before forming the trapping layer 2 there.

[0049] In a second step of the preparation method shown in the, the dielectric layer 4 having a thickness greater than 200 nm is formed. In a very general manner, there are many possibilities for forming this dielectric layer 4 so that it is ultimately buried in the substrate S. It can be formed on the side of the support substrate 1 by deposition or by treatment (oxidation for example) of the trapping layer 2. It can also be formed on the side of a so-called “donor” substrate which provides the upper layer 5. According to the present invention, and for reasons which will be made apparent in the remainder of this description, the dielectric layer 4 is produced on the trapping layer 3, by high density plasma chemical vapor deposition (“High Density Plasma Chemical Vapor Deposition” according to the English expression).This technique simultaneously implements the deposition and ionic spraying ("sputtering" according to the English expression used in the trade) of this dielectric layer 4. It has the particular advantage of providing a thick and not very rough layer, so that its formation step can be devoid of any smoothing treatment such as polishing. At the end of this step of formation of the dielectric layer, the support substrate 1 is available. This support substrate can have a significant curvature, sometimes greater than 60 micrometers when the support substrate 1 is circular in shape and has a diameter of 300 mm.

[0050] It is noted that the method for preparing the support substrate 1 can also incorporate a step of annealing the dielectric layer 4. This annealing, called densification, is advantageously carried out in a neutral atmosphere. It is carried out at a temperature exceeding the deposition temperature of the dielectric layer 4, and preferably less than 1000°C, for a relatively short duration of less than 1 hour, such as for example 30 minutes.

[0051] Continuing the description of the method for manufacturing the final substrate S, this comprises, in a third step which follows the second step, the transfer of the upper layer 5 comprising a semiconductor material onto the dielectric layer 4. As is well known per se, this transfer can be carried out by assembling a free face of a donor substrate 1' to the support substrate 1, preferably by molecular adhesion. The dielectric layer 4 having been previously formed on the support substrate 1, it is not necessary for the donor substrate 1' to itself be provided with such a dielectric layer. It is nevertheless possible to provide for this donor substrate to be provided with a thin thickness of dielectric (for example less than 150 nm). Preferably, however, the donor substrate is devoid of any intentionally formed dielectric surface layer.The nature of the donor substrate 1' is chosen according to the desired nature of the upper layer 5, as this has already been described in a previous section of this presentation. It can therefore be a substrate formed from a monocrystalline semiconductor, for example silicon.

[0052] After this assembly step, the donor substrate is reduced in thickness to form the upper layer 5, as shown in the. This reduction step can be carried out by mechanical and / or chemical thinning. Preferably, however, the reduction in thickness of the donor substrate 1' is carried out by fracture at a previously introduced weakening plane, for example according to the principles of Smart Cut technology. TM. In accordance with the principles of this technology, the transfer of the upper layer 5 comprises a step of implanting so-called "light" species, for example hydrogen and / or helium ions, in the donor substrate 1' to form a fragile plane there. This fragile plane defines, with the free surface of the donor substrate, the upper layer 5 which will be transferred. After assembling the donor substrate 1' with the support substrate 1, the donor substrate is fractured at the fragile plane, by applying a force of mechanical or thermal origin.

[0053] After this thinning or, preferably, fracturing step, finishing steps of the thin layer 5, such as heat treatment under a reducing or neutral atmosphere, sacrificial oxidation can be linked to the thickness reduction step.

[0054] Very surprisingly, the applicant discovered that it was possible to obtain both a reduced curvature and a satisfactory surface condition when the dielectric layer 4 is formed by high plasma density chemical vapor deposition and when the finishing step includes annealing carried out in a neutral or reducing atmosphere at a temperature above 1050°C for a duration of more than 30 minutes.

[0055] Figures 5a and 5b thus show the measured characteristics of the curvature of the final substrate S () and the roughness of the exposed surface of the upper layer 5 (, this roughness measurement, expressed in nm, being obtained by atomic force over a measuring field of 30 micrometers by 30 micrometers) of a substrate prepared according to the method which has just been detailed. It can be seen that it is possible to reduce the curvature of the final substrate S by increasing the annealing temperature of the finishing step. When this annealing brings the substrate to 1050°C, this curvature is of the order of 55 micrometers, which is already very satisfactory. It is noted that the results at 1200°C obtained using rapid annealing also make it possible to reduce the curvature of the substrate, but can cause dislocation-type defects, as mentioned in the introduction to this application.

[0056] It is also observed, on the, and unexpectedly, that the measured roughness of the upper layer 5 after the application of the annealing of the finishing step is stable with the increase in this temperature and of a level lower than 0.3 nm in mean quadratic measurement, which is also very satisfactory, both at the edge of the substrate (mark "B") and in its center (mark "C"). It is recalled that the preparatory observations of the applicant, reported, showed an increasing roughness of the exposed surface of this upper layer 5 with the increase in temperature.

[0057] A preparation method in accordance with the invention therefore exploits these results to propose different finishing sequences for a finishing step. In all these possible sequences, there is at least one annealing, designated "first annealing", this first annealing being carried out in a neutral or reducing atmosphere at a temperature above 1050°C for a duration greater than 30 minutes. In all cases also, the dielectric layer 4, buried in the final substrate, was obtained by high-density plasma chemical vapor deposition on the charge trapping layer 2.

[0058] Thus, the finishing step may comprise at least one step of thinning the upper layer 5. This at least one thinning step may be carried out before and / or after the first annealing. The finishing sequence carried out during the finishing step may therefore correspond to a thinning-annealing or annealing-thinning or even thinning-annealing-thinning sequence. This thinning of the layer may in particular be carried out by sacrificial oxidation (i.e. the oxidation of a surface thickness of this layer, followed by the removal of this oxidized thickness) of the upper layer.

[0059] Furthermore, the finishing step may include other annealing operations than the first annealing already described. Thus, in an alternative embodiment, the finishing sequence may incorporate a second rapid annealing operation, this second annealing operation being carried out in a neutral or reducing atmosphere at a temperature above 1050°C for a duration of less than 2 minutes. The second annealing operation may be carried out before or after the first annealing operation.

[0060] Preferably, the neutral or reducing atmosphere used during the first annealing and, where appropriate, during the second annealing is composed mainly or exclusively of Argon.

[0061] The temperature of the first annealing may preferably be chosen in the range 1050°C to 1100°C, so as not to affect the quality of the trapping layer 2. Too large a thermal budget applied during the finishing step could actually lead to modifying its crystallinity and its electrical efficiency. To further improve the smoothing effect of this first annealing, even for the lower part of the preferred temperature range, the equipment in which this annealing is carried out may follow the teachings of document EP3011590B1.

[0062] To avoid generating dislocation-type defects in the final substrate, it is preferable to avoid introducing rapid annealing in the finishing sequence, although this cannot be entirely ruled out.

[0063] Illustrates the benefit of using a "long" anneal only in the finishing sequence, rather than a "fast" anneal in terms of dislocation-type defects. The left part of this figure shows a map of the dislocations present in a final substrate for which the finishing sequence including annealing is conducted in a neutral or reducing atmosphere at a temperature above 1050°C for a duration greater than 30 minutes, while being devoid of fast annealing. The absence or near absence of such defects can be observed on this left part.

[0064] The right part of this figure shows a map of the dislocations present in a final substrate that has received rapid heat treatment. The difference, in terms of defects, with the left part is clearly visible.

[0065] These dislocation maps can be prepared by inspection equipment implementing a deflectometry technique, as for example presented in document US7812942.

[0066] Regardless of the finishing sequence used, the preparation method which has just been described makes it possible to provide a final substrate comprising, successively in contact with each other, an upper layer 5 of semiconductor material, for example silicon, a dielectric layer having a thickness greater than 200 nm, an electric charge trapping layer and a base substrate. The dielectric layer may in particular have a thickness greater than or equal to 400 nm. The exposed surface of the upper layer of semiconductor material of this final substrate has a roughness of less than 0.3 nm in mean square measurement over a field of 5 micrometers by 5 micrometers and a curvature of less than 60 micrometers, preferably less than 40 micrometers. Advantageously, this final substrate has a cumulative length of planes or dislocation lines less than 20 mm.

[0067] Of course, the invention is not limited to the embodiments described and variant embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

A method for preparing a final substrate (S) comprising a thick buried dielectric layer (4), the method comprising: a step of preparing a support substrate (1) comprising an electric charge trapping layer (2) arranged on a base substrate (3); a step of forming the dielectric layer (4) having a thickness greater than 200 nm on the electric charge trapping layer (2); a step of transferring an upper layer (5) comprising a semiconductor material onto the dielectric layer (4); a step of finishing the exposed face of the upper layer (5); the preparation method being characterized in that the step of forming the dielectric layer (4) is carried out by high-density plasma chemical vapor deposition and in that the finishing step comprises a first annealing conducted in a neutral or reducing atmosphere at a temperature greater than 1050°C for a duration greater than 30 minutes. Preparation method according to the preceding claim in which the step of forming the dielectric layer (4) comprises, after the high density plasma chemical vapor deposition of the dielectric layer, a densification annealing of the support substrate. Preparation process according to the preceding claim in which the densification annealing is carried out in a neutral atmosphere at a temperature below 1000°C and for a duration of less than 1 hour. Preparation method according to one of the preceding claims in which the finishing step comprises, before and / or after the first annealing, a thinning of the upper layer (5). Preparation method according to one of the preceding claims in which the finishing step comprises a second annealing, the second annealing being carried out in a neutral or reducing atmosphere at a temperature above 1050°C for a duration of less than 2 minutes. Preparation process according to one of the preceding claims in which the neutral or reducing atmosphere of the first annealing comprises or consists of argon. Preparation method according to one of the preceding claims in which the step of forming the dielectric layer (4) is devoid of polishing the exposed face of the dielectric layer (4). Preparation method according to one of the preceding claims in which the semiconductor material of the upper layer (5) is silicon. Preparation method according to one of the preceding claims in which the dielectric layer (4) is made of silicon dioxide. Preparation method according to one of the preceding claims in which the dielectric layer (4) has a thickness greater than or equal to 400 nm. Method according to one of the preceding claims in which the step of transferring the upper layer comprises a step of implanting so-called "light" species in a donor substrate (1') to form a fragile plane there, the assembly of the donor substrate with the support substrate (1), and the fracture of the donor substrate at the fragile plane. Final substrate (S) comprising, successively in contact with each other, an upper layer (5) of semiconductor material, a dielectric layer (4) having a thickness greater than 200 nm, an electric charge trapping layer (2) and a base substrate (3), the final substrate (S) being characterized in that it has a curvature of less than 60 micrometers, preferably less than 40 micrometers, and in that an exposed surface of the upper layer (5) has a roughness of less than 0.3 nm in mean square measurement over a field of 30 micrometers by 30 micrometers. Final substrate (S) according to the preceding claim in which the upper layer (5) is made of silicon. Final substrate (S) according to one of the two preceding claims in which the dielectric layer (4) is made of silicon oxide. Final substrate (S) according to one of the 3 preceding claims having a cumulative length of planes or lines of dislocations, measured by deflectometry, less than 20 mm.

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