Arrangement of stacked capacitive memory components, in particular for weighted multiplication in artificial neural networks

Abstract

The invention relates to an arrangement of stacked capacitive memory components, in particular for the weighted multiplication in artificial neural networks. The invention also relates to a memory matrix comprising multiple arrangements according to the invention in a two-dimensional or three-dimensional matrix, and to a method for producing an arrangement and memory matrix according to the invention.

Description

[0001] Arrangement of stacked capacitive memory components, in particular for weighted multiplication in artificial neural networks

[0002] The invention relates to an arrangement of stacked capacitive memory components, in particular for weighted multiplication in artificial neural networks. The invention further relates to a memory matrix comprising a plurality of arrangements according to the invention in a two-dimensional or three-dimensional matrix.

[0003] EP 4 062 464 A1 discloses separated capacitive synaptic memory devices for weighted multiplication in artificial neural networks.

[0004] There is an increasing need to store more neural network parameters. This is primarily driven by the current trend toward large language models, such as GPT-3 or GPT-4.

[0005] It is obvious that the storage density can hardly be increased any further by scaling to smaller technology nodes, since technological limitations have been reached.

[0006] Therefore it is necessary to stack memory components three-dimensionally on top of each other.

[0007] US2021398593A1 describes a conventional arrangement of a 3D NAND flash memory with horizontal word lines, a channel (usually a semiconductor) which penetrates the word lines vertically and furthermore a back gate and an oxide which fills the channel. This invention describes a stack of field effect transistors, which are provided with a back electrode. The back electrode is intended to support programming and the bit line is connected to the channel in claim 15. US2010096682A1 describes a series connection of memory cells and word lines which are ground along an elevation, as well as a semiconductor layer which penetrates the word lines (first conductive layers). The semiconductor layer acts as the body of the memory cells.

[0008] US 8547741B2 describes series-connected memory cells via a channel material. Claim 6 describes an additional gate (assist gate) that fills the channel material from above.

[0009] US 9048329B2 describes stacked word lines in which a semiconductor channel is arranged on each side. Furthermore, source and drain regions are arranged at the ends of the semiconductor channels.

[0010] EP4062464A1 describes a capacitive synaptic component which consists of a layer structure comprising a gate electrode, a first dielectric layer connected to the gate electrode, a second dielectric layer and a readout electrode connected to the second dielectric layer, and a shielding layer arranged between the first dielectric layer and the second dielectric layer, which is designed as a layer with adjustable shielding behavior in an electric field, starting from the gate electrode in the direction of the readout electrode, and the shielding layer is provided with one or more of its own contacts which realize a charge inflow into or a charge outflow from the shielding layer.

[0011] The object of this invention is to enable a stacking of capacitive synaptic components.

[0012] The object is achieved according to the invention by an arrangement according to claim 1 or a memory matrix according to claim 19. Advantageous embodiments are disclosed in the dependent claims. The inventive arrangement of stacked capacitive memory components, in particular for weighted multiplication in artificial neural networks, comprises for each stacked capacitive memory component: a gate electrode as a word line; a readout electrode as a bit line; a first dielectric layer connected to the word line; a second dielectric layer connected to the bit line;and a shielding layer which is arranged between the first dielectric layer and the second dielectric layer, wherein the shielding behavior of the shielding layer can be adjusted by the electric field starting from the word line to the bit line, and wherein the shielding layer comprises one or more separate contacts for a charge inflow into or a charge outflow from the shielding layer; wherein the first dielectric layer and / or the second dielectric layer extend over all stacked capacitive memory components; and wherein the word lines of the stacked capacitive components are combined and the shielding layers and the bit lines of the stacked capacitive components are separated;or wherein the word lines and the shielding layers of the stacked capacitive components are combined and the bit lines of the stacked capacitive components are separated. The stacking is achieved according to the invention in that the word lines of the stacked capacitive components are combined and the shielding layers and the bit lines of the stacked capacitive components are separated or in that the word lines and the shielding layers of the stacked capacitive components are combined and the bit lines of the stacked capacitive components are separated. At the same time, the first dielectric layer and / or the second dielectric layer extend over all stacked capacitive memory components.;

[0013] The arrangement of stacked capacitive storage components according to the invention is not limited to a spatial extent and comprises in particular a horizontal and / or vertical stacking of capacitive storage components.

[0014] The elements combined or extending over all stacked capacitive components, such as word lines, bit lines, shielding layers, first dielectric layer and / or second dielectric layer, can be formed in one piece or in one piece or can be connected to one another by further means.

[0015] According to a variant of the invention, the shielding layer consists of polycrystalline silicon.

[0016] According to a further variant of the invention, the first dielectric layer and / or the second dielectric layer comprises a storage material with charge trapping sites.

[0017] In an advantageous variant of the invention, the arrangement of stacked capacitive memory components has the following layer structure: a. combined word lines; b. combined first dielectric layer; c. separate shielding layers; d. combined second dielectric layer; and e. separate bit lines.

[0018] According to an expedient variant, the separated shielding layers and / or the separated bit lines are separated from one another by insulators.

[0019] According to a further variant of the invention, the combined word lines are formed in a rod-shaped manner, wherein the combined first dielectric layer, the separated shielding layers, the combined second dielectric layer and the separated bit lines are each formed concentrically around the rod-shaped word lines in the order mentioned.

[0020] Rod-shaped in the sense of the invention refers to an elongated geometric shape with a larger longitudinal dimension compared to the diameter, wherein the cross-section can be round, oval, or square. In particular, the longitudinal dimension can be at least 2 times, at least 5 times, at least 7 times, or at least 10 times and / or at most 50 times, at most 100 times, at most 200 times, or at most 500 times.

[0021] Concentric in the sense of the invention refers to an outer layer which completely encloses an inner layer. For example, the combined first dielectric layer completely encloses the rod-shaped, combined word line and / or the separated shielding layers enclose the combined first dielectric layer and thus also the rod-shaped, combined word lines enclosed thereby and / or analogously the combined second dielectric layer and subsequently the separated bit lines each completely enclose all previous layers. In an alternative variant of the invention, the arrangement of stacked capacitive memory components has the following layer structure: a. combined bit lines; b. combined second dielectric layer; c. combined shielding layers; d. combined first dielectric layer; and e. separate word lines.

[0022] According to a variant of the invention, the separated word lines are separated from one another by insulators.

[0023] According to a further variant of the invention, the combined bit lines are formed in a rod-shaped manner, wherein the combined second dielectric layer, the combined shielding layers, the combined first dielectric layer and the separated word lines are each formed concentrically around the rod-shaped bit lines in the order mentioned.

[0024] According to the above variant, the combined second dielectric layer completely encloses the rod-shaped, combined bit lines and / or the combined shielding layers enclose the combined second dielectric layer and thus also the rod-shaped, combined bit lines enclosed thereby and / or the combined first dielectric layer encloses the combined shielding layers and subsequently the separated word lines enclose the combined first dielectric layer.

[0025] In a preferred variant of the invention, the arrangement is symmetrical in the plane of the stacking. According to a variant of the invention, the arrangement is symmetrical in the plane perpendicular to the stacking. When stacked in the vertical direction, the arrangement according to this variant is symmetrical in the horizontal plane. The axis of symmetry is formed, for example, by the combined word lines or the combined bit lines, and the other layers of the arrangement extend symmetrically to both sides in the horizontal direction. In the case of rod-shaped combined word lines or rod-shaped combined bit lines, these form, for example, a rotational axis of symmetry, and the other layers extend rotationally symmetrically around the rod-shaped combined word lines or rod-shaped combined bit lines.

[0026] According to an advantageous variant of the invention, the shielding layers comprise or consist of the following regions: i. p-doped region (6); ii. lightly doped region (7); and iii. n-doped region (8).

[0027] In a preferred variant of the invention, the bit lines and the second dielectric layer are arranged in the lightly doped region.

[0028] According to a variant of the invention, the shielding layers comprise one or two enhancement electrodes, by means of which the p-doped region and the n-doped region of the shielding layers are created. In particular, the p-doped region and the n-doped region can be created electrically by means of the two enhancement electrodes.

[0029] According to an expedient variant of the invention, the one or two enhancement electrodes are rod-shaped and preferably extend parallel to the rod-shaped combined word lines or the rod-shaped combined bit lines.

[0030] In a further variant according to the invention, the enrichment electrodes are each surrounded by a further dielectric layer, wherein the further dielectric layer is preferably formed identically to the second dielectric layer.

[0031] According to a variant of the invention, the further dielectric layers extend concentrically around the enhancement electrodes and preferably overlap with the second dielectric layer if the further dielectric layers are formed identically to the second dielectric layer.

[0032] According to an advantageous variant of the invention, the shielding layer comprises one or two contacts for the charge inflow into and / or the charge outflow from the shielding layer, wherein, in particular, one contact is arranged in the p-doped region and the other contact is arranged in the n-doped region. The contacts are not connected to the enhancement electrodes, but are arranged adjacent thereto.

[0033] In a variant according to the invention, the first dielectric layer, the second dielectric layer, the further dielectric layer and / or the shielding layers partially overlap in the region of the transition from the weakly doped region to the p-doped region and / or the n-doped region.

[0034] According to one variant of the invention, the lightly doped region and the p-doped region and / or the n-doped region comprise an extended region and a narrowed region, wherein the transition from the lightly doped region to the p-doped region and / or the n-doped region is arranged in the narrowed region. In one variant of the invention, the first dielectric layer is formed separately, analogous to the word lines, or extends over all stacked capacitive memory components.

[0035] According to a variant of the invention, the first dielectric layer, the second dielectric layer and / or the further dielectric layer is formed as a storage material.

[0036] According to one variant of the invention, the combined word lines, the combined bit lines, and / or the one or two combined enhancement electrodes consist of titanium, titanium nitride, or another metal that can be etched selectively with respect to silicon, silicon dioxide, and / or silicon nitride. As a result, structures already deposited during the manufacturing process, such as the combined word lines, the combined bit lines, and / or the one or two combined enhancement electrodes, can subsequently be selectively or completely removed by etching.

[0037] The invention further relates to a memory matrix comprising a plurality of arrangements according to the invention, wherein the plurality of arrangements are arranged in a two-dimensional or three-dimensional matrix. The individual layers of a two-dimensional memory matrix consist, for example, of Y x Z elements, where Y and Z comprise several hundred to several thousand elements. In particular, a two-dimensional memory matrix can comprise at least 100 elements, at least 200 elements, at least 400 elements, at least 800 elements, at least 1000 elements, at least 2000 elements, at least 4000 elements or at least 8000 elements and / or at most 10,000 elements. A three-dimensional memory matrix comprises, for example, several hundred layers of the aforementioned two-dimensional memory matrices.In particular, a three-dimensional storage matrix may comprise at least 50 layers, at least 100 layers, at least 150 layers or at least 200 layers, at least 400 layers, at least 600 layers, at least 800 layers or at least 1000 layers and / or at most 2000 layers of the aforementioned two-dimensional storage matrices.

[0038] The method according to the invention for producing an arrangement of stacked capacitive memory components or a memory matrix comprising several arrangements of stacked capacitive memory components comprises the steps:

[0039] Providing a substrate; alternately depositing word lines and stack insulations on the substrate; etching at least one hole or trench in the deposited word lines and stack insulations down to the substrate; sequentially depositing a first dielectric layer, a shielding layer, a second dielectric layer and a bit line on the sidewalls of the etched holes or trenches; or the steps:

[0040] Providing a substrate; alternately depositing bit lines and stack insulations on the substrate and alternately depositing shielding layers and stack insulations in predefined regions of the substrate; etching at least one hole or trench in the deposited bit lines, shielding layers and stack insulations down to the substrate;

[0041] Depositing a second dielectric layer, a first dielectric layer and a word line in predefined regions of the etched holes or trenches. By means of the first variant of the method, an arrangement of stacked capacitive memory components with the following layer structure is produced: a. combined bit lines; b. combined second dielectric layer; c. combined shielding layers; d. combined first dielectric layer; and e. separated word lines.

[0042] By means of the second variant of the method, an arrangement of stacked capacitive memory components with the following layer structure is produced: a. combined word lines; b. combined first dielectric layer; c. separate shielding layers; d. combined second dielectric layer; and e. separate bit lines.

[0043] In a variant of the invention, the etched hole comprises at least two widened regions and a narrowed region in the transition between the two widened regions.

[0044] According to a further embodiment of this variant, the narrowed region is closed by the sequential deposition of the first dielectric layer, the shielding layer, the second dielectric layer and / or a further dielectric layer.

[0045] According to one embodiment of this variant, by closing the narrowed region in the respective widened regions, at least one rod-shaped region is formed for the rod-shaped word line or the rod-shaped bit line or the rod-shaped enhancement electrode, in particular a region for a layer structure is formed comprising all remaining non-overlapping layers of the arrangement.

[0046] In a further embodiment of the variant, the remaining rod-shaped regions are optionally covered by means of a mask during a subsequent deposition of further layers of the layer structure or the rod-shaped word lines, bit lines, p-doped regions, n-doped regions or enhancement electrodes in order to fill the remaining rod-shaped regions differently.

[0047] According to a variant of the invention, the step of filling the remaining areas with a layer comprises a subsequent partial etching of the filled layer. The remaining areas can thus initially be completely filled with a specific layer, which is subsequently partially etched away again to provide an area for a further layer.

[0048] According to a variant of the invention, the filling and etching are repeated until the remaining holes are filled with the desired layer structure.

[0049] In one variant of the invention, the method comprises applying a voltage to the enrichment electrode to locally enrich the surrounding area with electrons or holes. This allows the p-doped regions or n-doped regions to be created.

[0050] According to one embodiment of this variant, the additional dielectric layer or second dielectric layer surrounding the enrichment electrode is designed as a storage material that can be locally enriched in a non-volatile manner using the enrichment electrode. The advantage of this embodiment is that a high voltage does not have to be continuously applied to the enrichment electrode during operation.

[0051] According to one variant of the invention, the method comprises a selective or complete etching of structures already deposited during the manufacturing process, such as the combined word lines, the combined bit lines, and / or the one or two combined enhancement electrodes. The combined word lines, the combined bit lines, and / or the one or two combined enhancement electrodes are made of titanium, titanium nitride, or another metal that can be etched selectively with respect to silicon, silicon dioxide, and / or silicon nitride.

[0052] The invention is explained in more detail below with reference to exemplary embodiments shown in the figures. They show:

[0053] Fig. 1 is a plan view and a sectional view of a first embodiment of an arrangement of stacked capacitive storage components according to the invention;

[0054] Fig. 2 is a plan view and a sectional view of a first embodiment of a memory matrix comprising several arrangements according to the invention from Fig. 1 in a two-dimensional matrix;

[0055] Fig. 3 is a plan view and a sectional view of a second embodiment of an arrangement of stacked capacitive storage components according to the invention;

[0056] Fig. 4 is a plan view and a sectional view of a third embodiment of an arrangement of stacked capacitive storage components according to the invention;

[0057] Fig. 5 shows a plan view and a sectional view of a fourth embodiment of an inventive arrangement of stacked capacitive storage components; Fig. 6 shows a plan view and a sectional view of a fifth embodiment of an inventive arrangement of stacked capacitive storage components;

[0058] Fig. 7 is a plan view and a sectional view of a second embodiment of a memory matrix comprising several arrangements according to the invention from Fig. 6 in a two-dimensional matrix;

[0059] Fig. 8 is a plan view and a sectional view of a sixth embodiment of an arrangement of stacked capacitive storage components according to the invention; and

[0060] Fig. 9 shows the implementation of a method according to the invention for producing an arrangement of stacked capacitive storage components.

[0061] Fig. 1 shows, in the upper region, a plan view of a first embodiment of an arrangement 10 according to the invention of stacked capacitive memory components, in particular for weighted multiplication in artificial neural networks. In the lower region, Fig. 1 shows a sectional view along the line AA' from the upper region.

[0062] The stacked capacitive components of the arrangement 10 of Fig. 1 each comprise: a gate electrode as word line 1; a readout electrode as bit line 5; a first dielectric layer 2 connected to the word line 1; a second dielectric layer 4 connected to the bit line 5; and a shielding layer 3 arranged between the first dielectric layer 2 and the second dielectric layer 4. As can be seen in particular from the sectional view, the stacked arrangement 10 of Fig. 1 comprises five stacked capacitive components.

[0063] The shielding behavior of the shielding layer 3 of each capacitive component can be adjusted by the electric field extending from the word line 1 to the bit line 5. Furthermore, the shielding layer 3 has one or more dedicated contacts for a charge inflow into or a charge outflow from the shielding layer 3. The shielding layer 3 is expediently made of polycrystalline silicon.

[0064] The first dielectric layer 2 and the second dielectric layer 4 extend over all stacked capacitive memory components, as can be seen from the sectional view in Fig. 1.

[0065] Furthermore, the sectional view of Fig. 1 shows that the bit lines 5 and the shielding layers 3 of the stacked capacitive components are combined, and the word lines 1 of the stacked capacitive components are separated. In particular, the word lines 1 are separated or electrically isolated from one another by means of insulators 11.

[0066] Thus, the arrangement 10 of stacked capacitive components from Fig. 1 has the following layer structure: a. combined bit lines 5; b. combined second dielectric layer 4; c. combined shielding layers 3; d. combined first dielectric layer 2; and e. separated word lines 1.

[0067] According to the first exemplary embodiment from Fig. 1, the combined bit lines are rod-shaped. The combined second dielectric layer 4, the combined shielding layers 3, the combined first dielectric layer 2 and the separated word lines 1 are each formed concentrically around the rod-shaped bit lines 5 in the stated order, as can be seen in particular from the plan view of Fig. 1. The plan view also shows that the arrangement 10 is symmetrical in the plane perpendicular to the stacking, in particular rotationally symmetrical, with the rod-shaped combined bit lines 5 forming the axis of symmetry.

[0068] Fig. 2 shows a first embodiment of a memory matrix comprising a plurality of inventive arrangements 10 from Fig. 1 in a two-dimensional matrix. Overall, the memory matrix from Fig. 2 comprises three inventive arrangements 10 from Fig. 1, which are arranged side by side on a common substrate 9. Otherwise, Fig. 2 corresponds to Fig. 1, in particular with a top view in the upper area and a sectional view in the lower area.

[0069] Fig. 3 shows a top view and a sectional view of a second embodiment of an inventive arrangement 10 of stacked capacitive memory components. This second embodiment of Fig. 3 differs from the first embodiment of Fig. 1 in that the shielding layers 8 comprise the following regions: i. p-doped region (6); ii. lightly doped region (7); and iii. n-doped region (8).

[0070] The bit lines 5 and the second dielectric layer 4 are arranged in the lightly doped region 7. The p-doped region 6 and the n-doped region 8 are each rod-shaped and extend parallel to the rod-shaped, combined bit lines 5.

[0071] Fig. 4 shows a plan view and a sectional view of a third embodiment of an arrangement 10 according to the invention of stacked capacitive storage components. This third embodiment of Fig. 4 differs from the second embodiment of Fig. 3 in that the shielding layers

[0072] 3 comprise two enhancement electrodes 12, by means of which the p-doped region 6 and the n-doped region 8 of the shielding layers 3 are produced. The enhancement electrodes 12 are rod-shaped and extend parallel to the rod-shaped combined bit lines 5. By applying a positive voltage, electrons are generated in the region of the shielding layer and by applying a negative voltage, holes are generated in the region of the shielding layer. The advantage of this arrangement is that the electrical generation creates more flexibility for producing a p- or n-doped region. Furthermore, the manufacturing process is simplified, as described in Fig. 9a-h.

[0073] The enhancement electrodes 12 are each surrounded by a further dielectric layer 13, wherein the further dielectric layers 13 according to the third embodiment of Fig. 4 are formed identically to the second dielectric layer 4.

[0074] As can be seen in particular from the top view of the upper part of Fig.

[0075] 4, the lightly doped region 7, the p-doped region 6 and the n-doped region 8 each comprise an extended region 15 and a narrowed region 14, the transitions between the lightly doped region 7, the p-doped region 6 and the n-doped region 8 lying in the narrowed regions 14. According to the embodiment from Fig. 4, the lightly doped region 7, the p-doped region 6 and the n-doped region 8 are formed by circular regions which partially overlap. The overlap forms the narrowed regions 14 and the extended regions 15 are formed by the remaining regions of the circular regions. In the narrowed regions 14, that is to say in the region of the transition from the lightly doped region 7 to the p-doped region 6 or According to the embodiment of Fig. 4, the first dielectric layer 2 and the shielding layer 3 partially overlap in the n-doped region 8.

[0076] Fig. 5 shows a plan view and a sectional view of a fourth embodiment of an arrangement 10 according to the invention of stacked capacitive memory components. This fourth embodiment from Fig. 5 differs from the third embodiment from Fig. 4 in that only one enhancement electrode 12 is provided, by means of which either the p-doped region 6 or the n-doped region 8 can be electrically generated. For example, when erasing the cells, the p-enriched region can be generated and when reading and writing, the n-enriched region can be generated, or vice versa. The advantage of this embodiment is that a higher storage density can be achieved because there are only two extended regions.

[0077] Fig. 6 shows, in the upper region, a plan view of a fifth embodiment of an arrangement 10 according to the invention of stacked capacitive memory components, in particular for weighted multiplication in artificial neural networks. In the lower region, Fig. 6 shows a sectional view along the line AA' from the upper region.

[0078] Like the first embodiment of Fig. 1, the stacked capacitive components of the arrangement 10 each comprise: a gate electrode as word line 1; a readout electrode as bit line 5; a first dielectric layer 2 connected to the word line 1; a second dielectric layer 4 connected to the bit line 5; and a shielding layer 3 arranged between the first dielectric layer 2 and the second dielectric layer 4.

[0079] As in the first embodiment of Fig. 1, in the fifth embodiment of Fig. 6, the shielding behavior of the shielding layer 3 of each capacitive component can be adjusted by the electric field extending from the word line 1 to the bit line 5. Furthermore, the shielding layer 3 has one or more dedicated contacts for a charge inflow into or a charge outflow from the shielding layer 3. The shielding layer 3 is expediently made of polycrystalline silicon.

[0080] The first dielectric layer 2 and the second dielectric layer 4 also extend over all stacked capacitive memory components in the fifth embodiment of Fig. 6, as can be seen from the sectional view of Fig. 6.

[0081] In contrast to the first embodiment of Fig. 1, in the fifth embodiment of Fig. 6, the word lines 1 of the stacked capacitive components are combined, and the shielding layers 3 and the bit lines 5 of the stacked capacitive components are separated. Furthermore, the individual elements of the layer structure are rectangular in plan view and not predominantly round, as in the embodiment of Fig. 1.

[0082] Fig. 7 shows a second embodiment of a memory matrix comprising a plurality of arrangements 10 according to the invention from Fig. 6 in a two-dimensional matrix. Overall, the memory matrix from Fig. 7 comprises three arrangements 10 according to the invention from Fig. 6, which are arranged next to one another on a common substrate 9. Otherwise, Fig. 7 corresponds to Fig. 6, in particular with a top view in the upper region and a sectional view in the lower region. Fig. 8 shows a top view and a sectional view of a sixth embodiment of an arrangement 10 according to the invention of stacked capacitive memory components. The sixth embodiment from Fig. 8 differs from the fifth embodiment from Fig. 6 in that the separate shielding layers 3 each comprise the following regions: i. p-doped region 6; ii. lightly doped region 7; and iii. n-doped region 8 .

[0083] The weakly doped region 7 is arranged between the p-doped region 6 and the n-doped region 8.

[0084] Otherwise, the sixth embodiment of Fig. 8 corresponds to the fifth embodiment of Fig. 6.

[0085] Fig. 9 shows the implementation of a method according to the invention for producing an arrangement 10 of stacked capacitive storage components using the method steps symbolized in Figs. 9a to 9h.

[0086] Fig. 9a to 9h show, like the previous figures, in the upper part a plan view of the arrangement 10 to be produced and in the lower part a sectional view along the line AA ' from the upper part.

[0087] Fig. 9a shows the manufacture of an arrangement 10 of stacked capacitive memory components after providing a substrate 9 and alternately depositing word lines 1 and stack insulations 11 on the substrate 9.

[0088] Furthermore, the subsequent step of etching a hole 16 in the deposited word lines 1 and stack insulation 11 down to the substrate 9 was prepared by applying a mask 17. The mask 17 covers the deposited word lines 1 and stack insulation 11 except for the region to be etched. Fig. 9b shows the arrangement 10 to be produced after the etching of the hole 16. The etched hole 16 comprises three widened regions 15 which are separated from one another by two narrowed regions 14. According to the plan view from the upper region of Fig. 9b, the widened regions 15 and the narrowed regions 14 are formed, for example, by three circles which partially overlap. The narrowed regions 14 are located in the region of the overlap and the widened regions 15 are in the remaining sections.

[0089] Fig. 9c shows the device 10 to be produced after deposition of a first dielectric layer 2 on the side walls of the hole 16 etched in the previous step. As can be seen from the upper part of Fig. 9c, the narrowed regions 14 were thereby further narrowed but not yet closed.

[0090] Fig. 9d shows the device 10 to be produced after deposition of a shielding layer 3 on the first dielectric layer 2. The deposited shielding layer 3 closed the narrowed regions 14, whereby a rod-shaped region was formed in each of the three expanded regions 15.

[0091] Fig. 9e shows the device 10 to be produced after deposition of a second dielectric layer 2 on the shielding layer 3 within the rod-shaped regions in the extended regions 15. As a result, the rod-shaped regions are further reduced in size, but are not yet closed.

[0092] Fig. 9f shows the device 10 to be produced after filling the rod-shaped regions with an electrode material such as titanium nitride or titanium, or a metal that can be selectively etched with respect to silicon, silicon dioxide, and silicon nitride. The electrode in the central, extended region 15 in Fig. F serves as a closed bit line 5. The electrodes in the two lateral, extended regions 15 can be used as an enhancement electrode 12.

[0093] Fig. 9g shows the arrangement 10 to be produced after etching away the electrode material from the two lateral extended regions 15, including the second dielectric layer 4 in these regions. For this purpose, in particular the central extended region 15 was covered with a mask 17, which covers or protects the combined bit line 5 and the second dielectric layer 4. Fig. 9h shows the finished arrangement 10. In the left-hand extended region 15, a p-doped material 6 was filled in the rod-shaped region, and an n-doped material 8 was filled in the right-hand rod-shaped region.

[0094] List of reference symbols

[0095] 1 word line

[0096] 2 first dielectric layer

[0097] 3 Shielding cable

[0098] 4 second dielectric layer

[0099] 5 bit lines

[0100] 6 p-doped region

[0101] 7 weakly endowed area

[0102] 8 n-doped region

[0103] 9 Substrat

[0104] 10 Arrangement of stacked capacitive storage components

[0105] 11 I insulation

[0106] 12 Enrichment electrode

[0107] 13 additional dielectric layer

[0108] 14 narrowed area

[0109] 15 extended area

[0110] 16 holes

[0111] 17 Mask

Claims

Claims 1. An arrangement of stacked capacitive memory components, in particular for weighted multiplication in artificial neural networks, comprising for each stacked capacitive memory component: a gate electrode as a word line (1); a readout electrode as a bit line (5); a first dielectric layer (2) connected to the word line (1); a second dielectric layer (4) connected to the bit line (5); and a shielding layer (3) arranged between the first dielectric layer (2) and the second dielectric layer (4), wherein the shielding behavior of the shielding layer (3) can be adjusted by the electric field starting from the word line (1) to the bit line (5), and wherein the shielding layer (3) comprises one or more dedicated contacts for a charge inflow into or a charge outflow from the shielding layer (3);wherein the first dielectric layer (2) and / or the second dielectric layer (4) extend over all stacked capacitive memory components; and wherein the word lines (1) of the stacked capacitive components are combined and the shielding layers (3) and the bit lines (5) of the stacked capacitive components are separated; or wherein the bit lines (5) and the shielding layers (3) of the stacked capacitive components are combined; and the word lines (1) of the stacked capacitive Components are separated.

2. An arrangement of stacked capacitive memory components according to claim 1, wherein the shielding layer (3) consists of polycrystalline silicon.

3. An arrangement of stacked capacitive memory components according to claim 1 or claim 2, wherein the first dielectric layer (2) and / or second dielectric layer (4) comprises a memory material with charge trapping sites.

4. An arrangement of stacked capacitive memory components according to one of claims 1 to 3, wherein the arrangement of stacked capacitive memory components has the following layer structure: a. combined word lines (1); b. combined first dielectric layer (2); c. separate shielding layers (3); d. combined second dielectric layer (4); and e. separate bit lines (5).

5. An arrangement of stacked capacitive storage components according to claim 4, wherein the separated shielding layers (3) and / or the separated bit lines (5) are separated from one another by insulators (11).

6. An arrangement of stacked capacitive memory components according to claim 4 or claim 5, wherein the combined word lines (1) are rod-shaped and wherein the combined first dielectric layer (2), the separated shielding layers (3), the combined second dielectric layer (4) and the separated bit lines (5) are each formed concentrically around the rod-shaped word lines (1) in the stated order.

7. An arrangement of stacked capacitive memory components according to one of claims 1 to 3, wherein the arrangement of stacked capacitive memory components has the following layer structure: a. combined bit lines (5); b. combined second dielectric layer (4); c. combined shielding layers (3); d. combined first dielectric layer (2); and e. separated word lines (1).

8. Arrangement of stacked capacitive memory components according to claim 7, wherein the separated word lines (1) are separated by insulators (11) are separated from each other.

9. An arrangement of stacked capacitive memory components according to claim 7 or claim 8, wherein the combined bit lines (5) are rod-shaped and wherein the combined second dielectric layer (4), the combined shielding layers (3), the combined first dielectric layer (2) and the separated word lines (1) are each formed concentrically around the rod-shaped bit lines (5) in the order mentioned.

10. An arrangement of stacked capacitive memory components according to any one of claims 1 to 9, wherein the arrangement is symmetrical in the plane perpendicular to the stack.

11. An arrangement of stacked capacitive memory components according to one of claims 1 to 10, wherein the shielding layers (8) consist of or comprise the following regions: i. p-doped region (6); ii. lightly doped region (7); and iii. n-doped region (8).

12. An arrangement of stacked capacitive memory components according to claim 11, wherein the bit lines (5) and the second dielectric layer (4) are arranged in the lightly doped region (7).

13. An arrangement of stacked capacitive memory components according to claim 11 or claim 12, wherein the shielding layers (3) comprise one or two enhancement electrodes (12) by means of which the p-doped region (6) and / or the n-doped region (8) of the shielding layers (3) are produced.

14. An arrangement of stacked capacitive memory components according to claim 13, wherein the one or two enhancement electrodes (12) are rod-shaped and preferably extend parallel to the rod-shaped combined word lines (1) or the rod-shaped combined bit lines (5).

15. An arrangement of stacked capacitive memory components according to claim 13 or claim 14, wherein the enhancement electrodes (12) are each surrounded by a further dielectric layer, wherein the further dielectric layer is preferably formed identically to the second dielectric layer (4).

16. An arrangement of stacked capacitive memory components according to claim 15, wherein the further dielectric layers extend concentrically around the one or two enhancement electrodes and preferably overlap with the second dielectric layer (4) when the further dielectric layers are formed identically to the second dielectric layer (4).

17. Arrangement according to one of claims 11 to 16, wherein the shielding layer comprises one or two contacts for the charge inflow into and / or the charge outflow from the shielding layer (3), wherein in particular one contact is arranged in the p-doped region (6) and the other contact in the n-doped region (8).

18. Arrangement according to one of claims 11 to 17, wherein the lightly doped region (7) and the p-doped region (6) and / or the n-doped region (8) comprise an extended region and a narrowed region, wherein the transition from the lightly doped region (7) to the p-doped region (6) and / or the n-doped region (8) is arranged in the narrowed region.

19. Arrangement according to claim 18, wherein in the region of the transition from the lightly doped region (7) to the p-doped region (6) and / or the n-doped region (8), the first dielectric layer (2), the second dielectric layer (4), the further dielectric layer (13) and / or the shielding layers (3) partially overlap.

20. Arrangement according to one of claims 1 to 19, wherein the first dielectric layer (2) is formed separately analogously to the word lines (1) or extends over all stacked capacitive memory components.

21. Arrangement according to one of claims 1 to 20, wherein the first dielectric layer (2), the second dielectric layer (4) and / or the further dielectric layer (13) is formed as a storage material.

22. Arrangement according to one of claims 1 to 20, wherein the combined word lines (1), the combined bit lines (5) and / or the one or two combined enhancement electrodes (12) consist of titanium, titanium nitride or another metal which is selective to silicon, silicon dioxide and / or Silicon nitride can be etched.

23. A memory matrix comprising a plurality of arrays according to any one of claims 1 to 22, wherein the plurality of arrays are arranged in a two-dimensional or three-dimensional matrix.

24. A method for producing an arrangement of stacked capacitive memory components or a memory matrix comprising a plurality of arrangements of stacked capacitive memory components, in particular according to one of claims 1 to 23, comprising the steps: Providing a substrate (9); alternately depositing word lines (1) and stack insulations (11) on the substrate (9); etching at least one hole (16) or trench in the deposited word lines (1) and stack insulations (11) down to the substrate (9); sequentially depositing a first dielectric layer (2), a shielding layer (3), a second dielectric layer (4) and a bit line (5) on the sidewalls of the etched holes (15) or trenches; or, comprising the steps: Providing a substrate (9); alternately depositing bit lines (5) and stack insulations (11) on the substrate (9) and alternately depositing shielding layers (3) and stack insulations (11) in predefined regions of the substrate (9); etching at least one hole (16) or trench in the deposited bit lines (5), shielding layers (3) and stack insulations (11) down to the substrate (9); Depositing a second dielectric layer (4), a first dielectric layer (2) and a word line (1) in predefined regions of the etched holes (15) or trenches.

25. The method according to claim 24, wherein the etched hole (16) comprises at least two enlarged regions (15) and one narrowed region (14) in the transition between the two enlarged regions (15).

26. The method according to claim 25, wherein the narrowed region (14) is closed by the sequential deposition of the first dielectric layer (2), the shielding layer (3), the second dielectric layer (4) and / or a further dielectric layer (13).

27. The method according to claim 26, wherein by closing the narrowed region (14) in the respective widened regions (15) at least one rod-shaped region is formed for the rod-shaped word line (1) or the rod-shaped bit line (5) or the rod-shaped enhancement electrode (12), in particular a region for a layer structure is formed comprising all remaining non-overlapping layers of the arrangement.

28. The method according to claim 27, wherein the remaining rod-shaped regions are optionally covered by means of a mask (17) during a subsequent deposition of further layers of the layer structure or the rod-shaped word lines (1), bit lines (5), p-doped regions (6), n-doped regions (8) or enhancement electrodes (12) in order to fill the remaining rod-shaped regions differently.

29. A method according to claim 27 or claim 28, comprising the step of filling the remaining areas with a layer and subsequently partially etching the filled layer.

30. The method of claim 29, repeating the filling and etching until the remaining holes are filled with the desired layer structure.

31. Method according to one of claims 27 to 30, comprising applying a voltage to the enrichment electrode (12) for locally enriching the environment with electrons or holes.

32. The method according to claim 31, wherein the further dielectric layer (13) or second dielectric layer (4) surrounding the enhancement electrode (12) is formed as a storage material, which by means of the Enrichment electrode (12) cannot be volatile locally enriched.

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