HETEROJUNCTION ELECTRONIC COMPONENT WITH AN IMPROVED BURIED BARRIER LAYER

Abstract

The invention relates to an electronic component (3), comprising: - a substrate (10); - a stack of two layers (14, 16) of different semiconductor materials, configured to form an electron gas layer (17) at or near their interface; - a buried barrier (2) forming a separation between the substrate (10) and said stack; - the buried barrier (2) comprises: - a first layer (23) of a ternary alloy of type III-N semiconductor material, having an increasing concentration of one of the chemical species of the ternary alloy of the first layer as it approaches the substrate; - a second layer (22) of a ternary alloy of type III-N semiconductor material, formed beneath the first layer and having a decreasing concentration of one of the chemical species of the ternary alloy of the first layer as it approaches the substrate. Fig. 5

Description

Title of the invention: HETE-JUNCTION ELECTRONIC COMPONENT PROVIDED WITH AN IMPROVED BURIED BARRIER LAYER

[0001] The invention relates to heterojunction electronic components provided with a buried barrier layer separating them from their substrate, and in particular to high electron mobility components provided with such a buried barrier layer.

[0002] Many electronic applications now require improved performance, especially in on-board electronics for automobiles and land transport, in aeronautics, in medical systems or in home automation solutions, for example. These applications mostly require high-power switches operating in frequency ranges frequently above one megahertz.

[0003] An alternative for power switches, particularly at high frequencies, is the use of heterostructure field effect transistors, and in particular high electron mobility field effect transistors.

[0004] A high electron mobility transistor includes the superposition of two semiconductor layers having different band gaps which form a quantum well at their interface. Electrons are confined in this quantum well to form a two-dimensional gas of electrons. For reasons of high voltage and temperature resistance, these transistors are chosen so as to have a wide energy band gap.

[0005] Among the wide energy gap HEMT transistors, gallium nitride-based transistors are very promising. Their wide energy gap induces a higher critical electric field compared to conventional electronic materials, a high carrier saturation speed and good thermal and chemical stabilities. The breakdown field of gallium nitride can thus be higher than 2x106 V / cm, which easily allows the realization of compact transistors with breakdown voltages higher than 600 V. With a lateral conduction transistor, the gate / drain breakdown voltage can easily be controlled by an appropriate distance between gate and drain. In addition, such transistors allow very high current densities due to the very high electron mobility and the high electron density in the interface electron gas.

[0006] Such transistors are subject to the phenomenon of current collapse. This phenomenon degrades the performance of the transistor following an overvoltage. The degradation may be characterized by an increase in the on-state resistance or by a shift in the transistor threshold voltage. The collapse phenomenon is due to the trapping of carriers under an electric field, which can occur for different energies and in different locations of the transistor. In particular, such transistors tend to trap electrons in deep layers, such as the buffer layer. Such trapped electrons act as parasitic gates by their electrostatic effect. These uncontrolled parasitic gates contribute to the depletion of the electron gas layer and therefore degrade its performance.

[0007] A known solution to reduce the electron trapping phenomenon is to insert a buried barrier layer between the layers forming the heterojunction and the substrate or buffer layer of the transistor. The paper published by Yu et al entitled 'improvement of breakdown characteristics in AlGaN / GaN / AlxGaN HEMT based on a grading AlxGabxN buffer layer' in the journal Physica Status Solidi A 207, No. 11, 2593-2596 / DOI 10.1002 / pssa.201026270, describes a horizontally conductive heterojunction transistor. The transistor comprises a stack of a GaN layer and a layer of AlN and AlGaN, at the interface of which an electron gas layer is formed. A buried barrier layer of AlxGaN is formed under the GaN layer. This buried barrier layer thus separates the GaN layer from an AlN buffer layer. Such a buried barrier layer forms a potential barrier at the conduction band, under the quantum well containing the electron gas.Thus, for an electron present in the electron gas layer, a potential barrier of more than 3eV is formed, thus limiting their injection to deeper layers. Such a structure allows both to increase the confinement of carriers in the quantum well and thus allow an increased threshold, to reduce their injection to the deep layers and thus reduce the current collapse effect, and also allows to increase the breakdown voltage of the transistor.

[0008] Such a buried barrier layer can however, by its design or its doping, trap carriers and participate in the depletion of the quantum well.

[0009] The invention aims to resolve one or more of these drawbacks. The invention thus relates to an electronic component, comprising:

[0010] -a substrate;

[0011] -a stack of two layers of different semiconductor materials, configured to form a layer of electron gas at or near their interface;

[0012] -a buried barrier forming a separation between the substrate and said stack;

[0013] - the buried barrier comprises:

[0014] -a first layer of a ternary alloy of III-N type semiconductor material, having an increasing concentration of one of the chemical species of the ternary alloy of the first layer as it approaches the substrate;

[0015] -a second layer of a ternary alloy of III-N type semiconductor material, formed under the first layer and having a decreasing concentration of one of the chemical species of the ternary alloy of the first layer as it approaches the substrate.

[0016] The invention also relates to the following variants. Those skilled in the art will understand that each of the features of the following variants can be independently combined with the above features, without constituting an intermediate generalization.

[0017] According to a variant, said first layer has an average concentration at most equal to 5% of its chemical species having an increasing concentration and said second layer has an average concentration at most equal to 5% of its chemical species having a decreasing concentration.

[0018] According to another variant, the chemical species having an increasing concentration in the first layer is aluminum, and the chemical species having a decreasing concentration in the second layer is aluminum.

[0019] According to another variant, the minimum concentration of aluminum in the first layer is at most 1% and in which the maximum concentration of aluminum in the first layer is at least equal to 2% and at most equal to 10%.

[0020] According to yet another variant, the maximum concentration of aluminum in the first layer is at most 5%.

[0021] According to a variant, said first and second layers are made of AlGaN.

[0022] According to another variant, the product of the maximum aluminum concentration of the first layer by its thickness is between 1 * 109 m and 3 * 109 m.

[0023] According to another variant, the first and second layers are of the non-intentionally doped type.

[0024] According to another variant, the buried barrier is positioned at a distance of less than 100 nm from the interface between the two layers of semiconductor materials forming the layer of electron gas.

[0025] According to yet another variant, the buried barrier has a thickness at least equal to 100 nm.

[0026] According to a variant, the buried barrier has an alternation of several first and second layers.

[0027] According to another variant, said first and second layers each have a thickness at most equal to 60 nm.

[0028] According to another variant, said first and second layers are sufficiently thin so as not to accumulate electrons in the buried barrier.

[0029] According to yet another variant, said buried barrier is in contact with the stack of the two layers of semiconductor materials forming the layer of electron gas.

[0030] According to a variant, the electronic component further comprises a layer of P-type doped semiconductor material arranged between the buried barrier and the substrate.

[0031] Other characteristics and advantages of the invention will emerge clearly from the description given below, for information purposes only and in no way limiting, with reference to the appended drawings, in which:

[0032] [Fig. 1] is a schematic sectional view of a stack of layers of semiconductor materials to form an electronic component provided with a barrier layer according to a first embodiment;

[0033] [Fig.2] is a diagram representing the concentration of a chemical component in the thickness of a barrier layer according to a first variant;

[0034] [Fig.3] is a diagram representing the concentration of a chemical component in the thickness of a barrier layer according to a second variant;

[0035] [Fig.4] is a schematic sectional view of a stack of layers of semiconductor materials to form an electronic component provided with a barrier layer according to a second embodiment;

[0036] [Fig.5] is a diagram illustrating different concentrations of a chemical component in the alloy layers of the buried barrier for different configurations, as a function of depth;

[0037] [Fig.6] is a diagram illustrating the valence and conduction band energies for the different configurations of [Fig.5], as a function of depth;

[0038] [Fig.7] is a diagram illustrating the decimal logarithm of the electron concentration for the different configurations of [Fig.5], as a function of depth

[0039] [Fig.8] is a diagram illustrating the valence and conduction band energies for other configurations, as a function of depth;

[0040] [Fig.9] is a diagram illustrating the decimal logarithm of the electron concentration for the configurations of [Fig.8], as a function of depth;

[0041] [Fig. 10] is a schematic sectional view of an application of the first embodiment to a normally open type high electron mobility field effect transistor.

[0042] [Fig.l] is a schematic sectional view of a stack 1 of layers of semiconductor materials to form an electronic component provided with a barrier layer according to a first embodiment.

[0043] The stack 1 of semiconductor materials comprises from bottom to top: a substrate 10, possibly one or more nucleation layers 11, possibly one or several transition layers 12, a semiconductor buffer layer 13, a buried barrier 2, a channel layer 14 of semiconductor material, possibly an adaptation layer 15, and an upper layer 16 of semiconductor material.

[0044] The layers of semiconductor material 14 and 16 are superimposed in a manner known per se to form a layer of electron gas 17 at the interface or close to the interface between these layers 14 and 16.

[0045] The substrate 10 may be an insulator or a semiconductor of intrinsic or doped silicon type. The substrate 10 may for example be of the silicon type with a (111) mesh orientation. The substrate 10 may also be silicon carbide, or sapphire. The substrate 10 may have a thickness of the order of 650 μm, typically between 500 μm and 2 mm.

[0046] The nucleation layer 11 is typically formed from a semiconductor material, for example of the IILN type, for example AIN, in order to allow subsequent epitaxy of a semiconductor material of the IILN type above the substrate 10.

[0047] The transition layer 12 deposited in a manner known per se on the nucleation layer 11 serves as an intermediary between the AlN and another IILN type semiconductor material. The transition layer 12 in particular allows a mesh adaptation between the AlN of the layer 11 and the layer 13 (typically GaN). Such a mesh adaptation makes it possible to manage the mechanical stresses in the layers. The transition layer (or layers) 12 may typically be made of a ternary aluminum nitride alloy such as an AlGaN alloy.

[0048] The buffer layer 13 typically has a thickness of between 100nm and 5pm, typically 1pm. Such a layer is for example a GaN layer of the non-intentionally doped type, or having Carbon doping making it more insulating.

[0049] The layer of semiconductor material 14 (for example of type IILV, for example of element III nitride, typically GaN) has for example a thickness of between 30 and 500nm, for example 100nm. The adaptation layer 15 is typically made of AIN, with for example a thickness typically of between 0.5nm and 1.5nm.

[0050] The layer of semiconductor material 16 is made of a material other than that of the layer 14 (for example of type IILV, for example made of ternary nitride of element III, typically AlGaN or InAlN) and has for example a thickness of between 10 and 40nm, for example 25nm. The material of the layer 16 is chosen to have a band gap greater than that of GaN.

[0051] In the examples, the layers are deposited by epitaxy with a Ga-face orientation.

[0052] The buried barrier 2 comprises an alternation:

[0053] -layers 21, 23 and 25 of semiconductor materials in ternary alloy of type IILN having an increasing concentration (with depth) of one of the components of the alloy as it approaches the substrate 10 or in other words an increasing concentration in the depth of the layer;

[0054] -layers 22, 24 and 26 of semiconductor materials in ternary alloy of type IILN having a decreasing concentration (with depth) of one of the components of the alloy when approaching the substrate 10 or in other words a decreasing concentration in the depth of the layer.

[0055] Layers 21 to 26 are for example made of AlGaN, but other materials such as InAlN or InAlGaN can also be considered. In the example illustrated, an alternation of three layers with increasing concentration of one of the components of the alloy, and three layers with decreasing concentration of one of the components of the alloy are used. A different number of such layers in the buried barrier 2 can of course be used.

[0056] The chemical bonds of the IILN materials form dipoles due to the shift of the barycenters of the positive and negative charges of the bond. While these dipoles neutralize each other two by two in the volume of a layer of IILN material of homogeneous composition, according to the invention, polarization volume charges are generated due to the continuous variation of the composition in the buried barrier 2.

[0057] With the alternation of layers of ternary IILN alloy semiconductor materials having an increasing / decreasing concentration of one of the materials of the alloy, a network is produced whose layers accumulate respectively negative and positive volume polarization charges. This forms a network of junctions that can be described as head-to-tail pn, without extrinsic doping. This network of pn junctions has a tendency to block electrons independently of the polarization direction. Due to the absence of need for extrinsic doping, it is not necessary to manage doping profiles, there is no risk of extrinsic contamination of the active layers for the electronic component, and parasitic lateral conduction is avoided because the buried barrier is depleted.The idea is therefore to create a network of junctions forming potential barriers whose height is adjustable with the composition gradient, the whole being able to be dimensioned to avoid any accumulation of carriers in the network, in particular electrons. For example, with a Ga-face type IILN crystal and with a satisfactory orientation of Al gradients in layers 21 to 26 in AlxGai_xN, such a network of head-to-tail pn junctions can be created.

[0058] Such a buried barrier 2 preferably has a thickness at least equal to 100nm, advantageously at least equal to 200nm, making the injection and trapping of majority carriers in the deeper layers (e.g. buffer layer 13) more difficult.

[0059] The barrier 2 is advantageously directly attached to the lower face of the layer 14.

[0060] With such a configuration of buried barrier 2, it has a high potential barrier under the electron gas layer 17, to reduce the current collapse phenomenon, one of the components of which comes from electrons injected into the deep layers (for example with a potential barrier greater than eV). Furthermore, such a buried barrier 2 can be fully depleted in order to avoid any parasitic lateral conduction under the electron gas layer 17. The potential barrier can be maintained at a relatively high level (for example at most 2 eV), without the buried barrier 2 inducing excessive depletion of the electron gas layer 17. In particular, even with a layer 14 of reduced thickness (typically at most 50 nm), the confinement of the electron gas layer 17 is improved and the depletion in the channel layer 14 due to this barrier 2 is particularly reduced.In particular, such a buried barrier 2 proves to be particularly advantageous with a buffer layer 13 in GaN doped with Carbon, having a tendency to trap electrons.

[0061] For example, the concentration of Aluminum in the different layers of the buried barrier 2 can be modulated. In particular, according to one variant, the concentration of Aluminum can have an alternation of layers having an Aluminum concentration with a linear increase in thickness and layers having an Aluminum concentration with a linear decrease in thickness, as illustrated in the diagram of [Fig.2].

[0062] In another variant, the concentration of Aluminum may experience an alternation of layers having an Aluminum concentration with a step-like growth in the thickness and layers having an Aluminum concentration with a step-like decrease in the thickness, as illustrated in the diagram of [Fig.3].

[0063] Different configurations of layers of the buried barrier 2 will be detailed later.

[0064] [Fig.4] is a schematic sectional view of a stack 1 of layers of semiconductor materials to form an electronic component provided with a barrier layer according to a second embodiment.

[0065] The stack 1 of the second embodiment has the same configuration as the stack of the first embodiment, and differs from it only by the presence of a layer 18 of P-doped semiconductor material, interposed between the buffer layer 13 and the buried barrier 2. The layer 18 is here made of P-doped GaN. layer 18 may for example have P-type doping with an acceptor concentration of between 5*1016 cm3 and 5*1017 cm3, for example 1017 cm3. P-type doping may be achieved with Magnesium.

[0066] The layer 18 may for example have a thickness of between 50 and 250nm, for example 200nm.

[0067] Such a configuration makes it possible to create an additional potential barrier under the buried barrier 2, and also makes it possible to promote the total depletion of electrons in the buried barrier 2. The greater the thickness of the layer 18, the higher the potential barrier provided by it. Such a layer 18 can also be used to compensate for electrons that could be accumulated at the bottom of the buffer layer 13.

[0068] The influence of different parameters on the operation of the buried barrier 2 will be studied. Simulations were thus carried out with different configurations of the second embodiment. Layer 14 is here made of GaN, layer 16 of AlGaN, and layers 21 to 26 are made of AlGaN.

[0069] [Fig.5] is a diagram illustrating different concentrations of a chemical component in the alloy layers of the buried barrier for different configurations, as a function of depth. [Fig.6] is a diagram illustrating the valence and conduction band energies as a function of depth, for the different configurations of [Fig.5]. [Fig.7] is a diagram illustrating the electron concentration as a function of depth, for the different configurations of [Fig.5].

[0070] The zero depth on the diagrams corresponds to the upper face of the GaN layer 14. This layer 14 here has a thickness of 100nm for the different configurations.

[0071] The solid line curves correspond to a state-of-the-art configuration, with a buried barrier consisting of an AlGaN layer having a homogeneous concentration of 2.5% over its entire thickness (300nm).

[0072] The dashed-dotted curves correspond to a configuration with layers 21, 23 and 25 whose aluminum concentration increases linearly between 0 and 2.5% in their thickness, when approaching the substrate 10, and with layers 22, 24 and 26 whose aluminum concentration decreases linearly between 2.5% and 0% in their thickness, when approaching the substrate 10.

[0073] The dotted curves correspond to a configuration with layers 21, 23 and 25 whose aluminum concentration increases linearly between 0 and 5% in their thickness, when approaching the substrate 10, and with layers 22, 24 and 26 whose aluminum concentration decreases linearly between 5% and 0% in their thickness, when approaching the substrate 10.

[0074] The broken line curves correspond to a configuration with layers 21, 23 and 25 whose aluminum concentration increases linearly between 0 and 10% in their thickness, when approaching the substrate 10, and with layers 22, 24 and 26 whose aluminum concentration decreases linearly between 10% and 0% in their thickness, when approaching the substrate 10.

[0075] In the different configurations according to the invention, the layers 21 to 26 have respective thicknesses of 50nm.

[0076] As illustrated in [Fig.6], the different configurations according to the invention make it possible to have a relatively high conduction band energy, with in particular a potential barrier at least equal to 2 eV at the upper part of the buried barrier. The configuration illustrated in dashed-dotted lines makes it possible in particular to have a potential barrier value of approximately 2 eV, at the upper part of the buried barrier. Such a configuration also makes it possible to maintain a relatively high potential barrier value over the entire thickness of the buried barrier, which promotes its complete depletion of electrons.Thus, one can either keep a high average concentration of the material of the chosen alloy (here Aluminum) to maximize the potential barrier, or reduce the average concentration of this material to maintain the level of the potential barrier, while favoring epitaxial growth of the layers of the buried barrier: a lower concentration of the chosen material makes it possible to reduce the mechanical constraints linked to the differences in lattice parameters of the ternary alloy presenting a variable composition.

[0077] As illustrated in [Fig.7], the different configurations make it possible to maintain a high concentration of electrons in the electron gas layer 17. The buried barrier according to the invention thus disturbs the electron gas layer 17 very little. Furthermore, only the configuration according to the invention corresponding to the broken line curve shows a significant concentration of electrons in the buried barrier. For the other configurations according to the invention, the concentration of electrons in the buried barrier is very reduced, or even the buried barrier is completely depleted. Advantageously, the minimum concentration of Aluminum in the layers 21 to 26 is at most equal to 1%. Advantageously, the maximum concentration of Aluminum in the layers 21 to 26 is at least equal to 2%, and preferably at most equal to 10%, advantageously at most 5%.

[0078] Advantageously, the product of the maximum aluminum concentration of one of the layers 21 to 26 by its thickness is between 1 * 109 m and 3 * 109 m. Such a range favors a complete depletion of the buried barrier 2.

[0079] Advantageously, the layers 21 to 26 each have a thickness of at most 60nm, preferably 50nm.

[0080] [Fig. 8] is a diagram illustrating the energies of the valence and conduction bands as a function of depth, for another configuration according to the invention. [Fig. 9] is a diagram illustrating the electron concentration as a function of depth, for the configuration according to the invention of [Fig. 8]. The solid line curve corresponds to a reference configuration of the state of the art, with a buried barrier made of AlGaN having a homogeneous Aluminum concentration of 5%. The broken line curve corresponds to a configuration with layers 21 to 26 having Aluminum concentrations varying between 0 and 10%, with an average concentration of 5%. The dotted line curve corresponds to a configuration with layers 21 to 26 having Aluminum concentrations varying between 0 and 5%, with an average concentration of 2.5%.

[0081] The zero depth on the diagrams corresponds to the upper face of the GaN layer 14. Compared to the configurations of [Fig.5], the layer 14 here has a thickness of 50nm. The layer 14 is therefore less thick than for the configurations of [Fig.5]. The buried barrier for the two configurations illustrated in [Fig.8] has a thickness of 300nm. From the diagram of [Fig.8], it can be seen that for the same average quantity of Aluminum as according to the state of the art, a configuration according to the invention makes it possible to raise the barrier level by 1.6 eV. It can also be seen that for an average quantity half that of the state of the art, a configuration according to the invention makes it possible to maintain the barrier at the same level.

[0082] From the diagram in [Fig.9], it can be deduced that for the same average quantity of Aluminum as according to the state of the art, a configuration according to the invention makes it possible to have the same concentration of electrons. It is also noted that for an average quantity half that of the state of the art, a configuration according to the invention makes it possible to obtain almost a depletion of electrons under the layer of electron gas 17. Such a barrier then disturbs the layer of electron gas 17 little.

[0083] Such a stack 1 of semiconductor materials including a buried barrier 2 can be used for many types of electronic components. Such a stack 1 can in particular be used for the formation of horizontally conductive electronic components. With reference to [Fig. 10], the application of such a stack 1 is illustrated for forming a horizontally conductive high electron mobility field effect transistor 3.

[0084] The transistor 3 comprises, in a manner known per se, conduction electrodes 31 and 32 arranged on the semiconductor layer 16. One of these electrodes will be designated as the source, the other electrode will be designated as the drain of the transistor 3. A control gate 33 is positioned between the conduction electrodes 31 and 32. The Control gate 33 is here formed in a recess passing through layer 16. Transistor 3 is therefore here of the normally open type. In the on state, the conduction under gate 33 is of the MOS type, in layer 14. Source 31, drain 32 and control gate 33 are illustrated only schematically, their dimensions and structures being able to differ considerably from the illustration of [Fig.5].

[0085] The application of the invention to such a transistor 3 makes it possible in particular to shift its threshold voltage towards positive values ​​due to the increased confinement of the electrons in the layer 17. The on-resistance of such a transistor 3 is particularly reduced under the gate, for a normally open recessed type transistor. Indeed, the buried barrier 2 is close to the electron gas layer 17, which makes it possible to reduce the depth of the gate recess. Furthermore, the static disorder under the gate 33 is also reduced in the absence of extrinsic doping that could contaminate the MOS channel formed in the on-state.

Claims

Claims

1. Electronic component (3), comprising: - a substrate (10); - a stack of two layers (14, 16) of different semiconductor materials, configured to form an electron gas layer (17) at or near their interface; - a buried barrier (2) forming a separation between the substrate (10) and said stack; Characterized in that the buried barrier (2) comprises: - a first layer (23) of a ternary alloy of III-N type semiconductor material, having an increasing concentration of one of the chemical species of the ternary alloy of the first layer as it approaches the substrate, the chemical species having an increasing concentration in the first layer (23) is aluminum, the minimum aluminum concentration in the first layer (23) is at most 1% and the maximum aluminum concentration in the first layer is at least 2% and at most 10%;-a second layer (22) of a ternary alloy of III-N type semiconductor material, formed under the first layer and having a decreasing concentration of one of the chemical species of the ternary alloy of the first layer as it approaches the substrate, the chemical species having a decreasing concentration in the second layer (22) being aluminum.;

2. Electronic component (3) according to claim 1, wherein said first layer has an average concentration at most equal to 5% of its chemical species having an increasing concentration and said second layer has an average concentration at most equal to 5% of its chemical species having a decreasing concentration.

3. An electronic component (3) according to claim 1 or 2, wherein the maximum aluminum concentration in the first layer (23) is at most 5%.

4. Electronic component (3) according to any one of claims 1 to 3, wherein said first and second layers (23, 22) are made of AlGaN.

5. An electronic component (3) according to claim 4, wherein the product of the maximum aluminum concentration of the first layer (23) by its thickness is between 1 * 109 m and 3 * 109 m.

6. Electronic component (3) according to any one of the preceding claims, in which the first and second layers (23,22) are of the non-intentionally doped type.

7. Electronic component (3) according to any one of the preceding claims, wherein the buried barrier (2) is positioned at a distance of less than 100 nm from the interface between the two layers (14, 16) of semiconductor materials forming the electron gas layer (17).

8. Electronic component (3) according to any one of the preceding claims, in which the buried barrier (2) has a thickness at least equal to 100nm.

9. Electronic component (3) according to any one of the preceding claims, in which the buried barrier (2) has an alternation of several first and second layers.

10. Electronic component (3) according to claim 8, wherein said first and second layers each have a thickness at most equal to 60nm.

11. An electronic component (3) according to any preceding claim, wherein said first and second layers (23, 22) are thin enough not to accumulate electrons in the buried barrier.

12. Electronic component (3) according to any one of the preceding claims, wherein said buried barrier (2) is in contact with the stack of the two layers of semiconductor materials forming the layer of electron gas (17).

13. Electronic component (3) according to any one of the preceding claims, further comprising a layer of P-type doped semiconductor material (18) disposed between the buried barrier (2) and the substrate (10).

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