Semiconductor substrate holder for PECVD processing with high substrate loading capacity

Abstract

Support for semiconductor substrates for PECVD processing with high substrate loading capacity The present description relates to a support (54) for semiconductor substrates (56) comprising a set of trays (58A, 58B, 58C, 58D) on which the semiconductor substrates rest. Each tray is made of an electrically conductive material and has at least one substantially vertical face having locations arranged in at least two horizontally oriented rows and two vertically oriented columns. Each location receives a semiconductor substrate oriented with an inclination relative to a vertical direction varying from 1° to 10°. Each tray comprises, at each location, a recess or an imprint covered by the substrate (56). The trays of each pair of trays facing each other are separated by electrically insulating spacers (60). Figure for abstract: Fig. 4

Description

Title of the invention: Support for semiconductor substrates for PECVD processing with high substrate loading capacity Technical field

[0001] The present application relates to a support for semiconductor substrates, in particular semiconductor substrates intended for the manufacture of photovoltaic cells. Prior art

[0002] A method of manufacturing a photovoltaic cell may comprise a step of depositing an electrically insulating layer on one face of a semiconductor substrate, in particular a silicon substrate, for example using a plasma-assisted chemical vapor deposition (PECVD) method.

[0003] [Fig.l] represents, in a partial and schematic manner, a side view with partial section of an example of a device 10 for processing semiconductor substrates suitable for implementing a PECVD process.

[0004] The device 10 comprises an enclosure 12 whose axis is substantially horizontal and in which a reduced pressure is maintained. The device 10 further comprises a support 13 on which are arranged trays 14 oriented substantially vertically and arranged next to each other, a single tray 14 being shown in [Fig.l]. The trays 14 can be introduced into the enclosure 12 or removed from the enclosure 12 by a door 15 for example provided at one end of the enclosure 12. Each tray 14, for example made of graphite, can receive at least one semiconductor substrate 16. The semiconductor substrates 16 are arranged substantially vertically in the enclosure 12.

[0005] [Fig.2] is a side view of a tray 14 comprising a row of semiconductor substrates 16.

[0006] The device 10 comprises reservoirs 18 of precursor gases and possibly of a neutral gas. The reservoirs 18 are connected to a control panel 20 adapted to produce a mixture of the precursor gases and possibly of the neutral gas. The control panel 20 is connected to the enclosure 12 by a valve 22 which, when open, allows the introduction of the gas mixture into the enclosure 12 via a supply nozzle 23. The device 10 comprises a vacuum pump 24 connected to the enclosure 12 by a valve 26 which, when open, allows the enclosure 12 to be evacuated and the gas mixture present in the enclosure 12 to be sucked out via a suction port 25.

[0007] The device 10 further comprises heating elements 28 surrounding the enclosure 12 and allowing the temperature of the trays 14 and of the gas mixture in the enclosure 12 to be controlled. The device 10 further comprises a generator 30 of an alternating voltage which is electrically connected to the trays 14 in the enclosure 12.

[0008] The PECVD process is a dry deposition technique, i.e. from a gaseous phase. It uses precursor gases which are injected into the enclosure 12 and the deposition results from the decomposition of these gases by a chemical reaction on the surface of the substrates 16. In the PECVD process, the chemical reaction is assisted by a radiofrequency (RF) electrical discharge which ionizes the gases and forms a plasma. Each plate 14 acts as a thermal conductor and radiofrequency contact with the associated semiconductor substrate 16. The plates 14 are connected to the generator 30 so as to form an alternation of cathodes and anodes and a plasma is generated between each pair of adjacent plates 14. The precursor gases will decompose to form a thin layer deposit on the face of each substrate 16 opposite the face in contact with the plate 14.

[0009] It would be desirable to increase the processing capacity of the device 10, i.e. the number of semiconductor substrates 16 that can be processed simultaneously. With the device 10, this can be achieved by increasing the number of trays 14 and / or by increasing the number of semiconductor substrates 16 per row and / or by increasing the number of rows per tray 14.

[0010] However, it may be difficult to increase the number of substrates per row since handling the semiconductor substrates 16 to place them on the tray 14 and to remove them from the trays 14 may become complex if not impossible in the horizontal configuration of the device 10. Indeed, loading the substrates 16 is only possible from the top down and perpendicular to the tray 14 arranged horizontally. Furthermore, increasing the number of trays 14, and increasing the number of rows per tray 14, results in a significant increase in the length of the enclosure 12 and the floor space occupied by the device 10, which is not desirable for use on an industrial scale. Summary of the invention

[0011] An object of an embodiment aims to overcome all or part of the drawbacks of the treatment devices described previously.

[0012] An object of an embodiment is that the floor space occupation of the processing device is reduced.

[0013] An object of an embodiment is that the capacity of the processing device can be increased.

[0014] One embodiment provides a support for semiconductor substrates comprising a set of trays on which the semiconductor substrates rest. conductors, each tray being made of an electrically conductive material and having at least one substantially vertical face having locations arranged in at least two horizontally oriented rows and two vertically oriented columns, each location receiving a semiconductor substrate oriented with an inclination relative to a vertical direction varying from 1° to 10°, each tray comprising, at each location, a recess or an imprint covered by the substrate, the trays of each pair of trays facing each other being separated by electrically insulating spacers.

[0015] According to one embodiment, said face of each tray has locations arranged in at least three horizontally oriented rows and two vertically oriented columns, each location receiving a semiconductor substrate oriented with an inclination relative to a vertical direction varying from 1° to 10°.

[0016] According to one embodiment, said face of each tray has locations arranged in at least five horizontally oriented rows and two vertically oriented columns, each location receiving a semiconductor substrate oriented with an inclination relative to a vertical direction varying from 1° to 10°.

[0017] According to one embodiment, said face of each tray has locations arranged in five to ten horizontally oriented rows and two vertically oriented columns, each location receiving a semiconductor substrate oriented with an inclination relative to a vertical direction varying from 1° to 10°.

[0018] According to one embodiment, the support comprises from 10 to 40 trays.

[0019] According to one embodiment, the set of trays comprises trays in interiors sandwiched between two outer trays, each inner tray having two substantially vertical parallel faces each having locations arranged in at least two horizontally oriented rows and two vertically oriented columns, each location on each face receiving a semiconductor substrate oriented with an inclination relative to a vertical direction varying from 1° to 10°.

[0020] According to one embodiment, the two outer plates each comprise a single substantially vertical face having locations arranged in at least two horizontally oriented rows and two vertically oriented columns, each location receiving a semiconductor substrate oriented with an inclination relative to a vertical direction varying from 1° to 10°.

[0021] According to one embodiment, each inner plate comprises, at each location, a through recess and covered on each of the two faces of the inner plate by one of the substrates.

[0022] According to one embodiment, each outer plate comprises, at each location, a non-through imprint in said face of the outer plate and covered by the substrate.

[0023] According to one embodiment, each tray comprises at least one leg, the support comprising at least a first electrically conductive rod connected to the legs of first trays of said set of trays and a second electrically conductive rod connected to the legs of second trays of said set of trays, said set comprising an alternation of the first and second trays.

[0024] According to one embodiment, each plate comprises, for each location, pads projecting from said face and which are in contact with the semiconductor substrate present at said location.

[0025] An embodiment also provides a device for processing semiconductor substrates, the device comprising an enclosure with a substantially vertical axis and at least one circuit for supplying a gas mixture into the enclosure, the device further comprising, in the enclosure, at least one support for the semiconductor substrates as defined previously, the processing device further comprising at least one radiofrequency generator of an alternating voltage electrically connected to several of said plates.

[0026] According to one embodiment, the device comprises a vacuum pump connected to the enclosure.

[0027] According to one embodiment, the enclosure is made of stainless steel.

[0028] According to one embodiment, the device is used for the treatment of substrates semiconductors intended for the manufacture of photovoltaic cells. Brief description of the drawings

[0029] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0030] [Fig-1] [Fig.l], described previously, represents, in a partial and schematic, an example of a PECVD processing device for semiconductor substrates;

[0031] [Fig.2] [Fig.2], described previously, represents, in a partial and schematic manner, an example of a tray provided with semiconductor substrates of the processing device of [Fig.l];

[0032] [Fig.3] [Fig.3] is a partial and schematic sectional side view of an embodiment of a device for PECVD processing of semiconductor substrates;

[0033] [Fig.4] [Fig.4] represents, in a partial and schematic manner, an embodiment of a support for semiconductor substrates of the processing device of [Fig.3];

[0034] [Fig.5] [Fig.5] represents, in a partial and schematic way, a mode of rea lisation of a first tray provided with semiconductor substrates of the support of [Fig.4], the tray comprising two columns and six rows;

[0035] [Fig.6] [Fig.6] represents, in a partial and schematic way, a mode of rea lisation of a second tray provided with semiconductor substrates of the support of [Fig.4];

[0036] [Fig.7] [Fig.7] is a partial and schematic sectional top view of the PECVD processing device for semiconductor substrates of [Fig.3] with an embodiment of the semiconductor substrate support; and

[0037] [Fig.8] [Fig.8] is a figure similar to [Fig.7] with a variant of the support of semiconductor substrates. Description of the embodiments

[0038] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In the following description, when reference is made to relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., reference is made to the vertical direction. Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of", when associated with a direction, mean to within 10°. Furthermore, the terms "insulator" and "conductor" are considered here to mean "electrically insulating" and "electrically conducting", respectively.

[0039] [Fig. 3] represents a side view with section, partial and schematic, of a mode for producing a device 50 for processing parts suitable for implementing a PECVD process.

[0040] The device 50 comprises a sealed enclosure 52, for example made of stainless steel or quartz, oriented vertically, in which a reduced pressure can be maintained. In the case where the enclosure 52 is made of stainless steel, a treatment of the internal wall of the enclosure 52 can be carried out. The specifications to be met in terms of mechanical and thermal resistance can, advantageously, be less restrictive when the enclosure 52 is made of stainless steel compared to the case where the enclosure 52 is made of quartz. The enclosure 52 can have a substantially cylindrical shape with a vertical axis. The device 50 further comprises a support 54, also called a nacelle, for semiconductor substrates 56. The nacelle 54 comprises an al alternation of inner plates 58A and 58B made of an electrically conductive material. The alternation of inner plates 58A and 58B is sandwiched between two outer plates 58C and 58D. Each plate 58A, 58B, 58C, 58D is made of a conductive material, for example graphite. The plates of each pair of adjacent plates 58A, 58B, 58C, and 58D, are separated by spacers 60 made of an electrically insulating material. The spacers 60 are for example ceramic.

[0041] [Fig. 4] is a side view with section, partial and schematic, of an embodiment of the nacelle 54. Figures 5 and 6 are side views, partial and schematic, respectively of the inner trays 58A and 58B loaded with semiconductor substrates 56, the views of Figures 5 and 6 being in a horizontal direction and orthogonal to the direction of the view of [Fig. 4]. [Fig. 7] is a top view with section, partial and schematic, of the device 50, and [Fig. 8] is a view similar to [Fig. 7] of a variant of the device 50. The spacers 60 are not shown in Figures 7 and 8.

[0042] The plates 58A, 58B, 58C, 58D are rigidly connected to each other. According to one embodiment, the nacelle 54 comprises rods 62 made of an electrically insulating material, for example ceramic. Each plate 58A, 58B, 58C, 58D comprises through holes 64 for the passage of the rods 62. Similarly, each spacer 60 comprises a through hole 66 for the passage of a rod 62. Each rod 62 therefore extends through the holes 64 and 66, passing alternately through one of the plates 58A, 58B, 58C, 58D and one of the spacers 60. For each rod 62, nuts 68, made of an electrically insulating material, for example ceramic, screwed to the ends of the rod 62 hold the assembly of the plates 58A, 58B, 58C, 58D and the spacers 62 in compression. According to one embodiment, the rods 62 are substantially parallel.

[0043] The nacelle 54 comprises a pedestal 70, made of an electrically insulating material, on which the trays 58A, 58B, 58C, 58D rest. According to one embodiment, the outer trays 58C and 58D comprise feet 72 coming into contact with the pedestal 70, the inner trays 58A and 58B not coming into contact with the pedestal 70. The pedestal 70 may comprise guides 74 adapted to cooperate with the feet 72 when placing the trays 58A, 58B, 58C, 58D on the pedestal 70.

[0044] The inner trays 58A are electrically connected to each other and to the outer tray 58C. The inner trays 58B are electrically connected to each other and to the outer tray 58D. For this purpose, each tray 58A, 58B, 58C, 58D comprises at least one tab 76 crossed by a hole 78. In Figures 3 to 8, the trays 58A, 58B, 58C, 58D are shown with two tabs 76, one in the upper part of the tray and the other in the lower part of the tray. As can be seen in Figures 5 and 6, the trays 58A and 58B have substantially the same structure and differ in the leg positions 76.

[0045] According to one embodiment, the nacelle 54 comprises first rods 80 made of an electrically conductive material, for example graphite, passing through the holes 78 of the inner plates 58A and the outer plate 58C while being in contact with the inner plates 58A and the outer plate 58C. For each first conductive rod 80, nuts 82, made of an electrically conductive material, for example graphite, fixed to the ends of the rod 80 ensure the maintenance of the rod 80. According to one embodiment, the nacelle 54 comprises second rods 84 made of an electrically conductive material, for example graphite, passing through the holes 78 of the inner plates 58B and the outer plate 58D while being in contact with the inner plates 58B and the outer plate 58D.For each second conductive rod 84, nuts 86, made of an electrically conductive material, for example graphite, fixed to the ends of the rod 84 ensure the maintenance of the rod 84. According to one embodiment, the first and second rods 80, 84 are substantially parallel.

[0046] Each tray 58A, 58B, 58C, 58D comprises a substantially flat plate 90, oriented substantially vertically, from which the tabs 76 project, and on which are provided locations each intended to receive a semiconductor substrate 56. Each inner tray 58A, 58B comprises two opposite, substantially vertical faces, each face of the inner tray 58A, 58B comprising locations each intended to receive a semiconductor substrate 56. The face of the semiconductor substrate 56 intended to be treated is that oriented towards the space between two adjacent trays. Each outer tray 58C, 58D comprises locations each intended to receive a semiconductor substrate 56 on a single, substantially vertical face of the tray 58C, 58D located opposite one of the inner trays 58A, 58B.

[0047] The semiconductor substrates 56 are arranged substantially vertically on the trays 58A, 58B, 58C, 58D. According to one embodiment, the substrates 56 are installed vertically on the trays 58A, 58B, 58C, 58D with a slight inclination relative to the vertical ensuring their stability relative to their center of gravity. The angle of inclination relative to the vertical varies from 1° to 10°, preferably from 2° to 6° depending on the size of the substrates 56. On each tray 58A, 58B, 58C, 58D, the semiconductor substrates 56 are arranged in rows and columns. According to one embodiment, each tray 58A, 58B, 58C, 58D comprises locations for at least one column of semiconductor substrates 56, preferably for two columns of semiconductor substrates 56. According to one embodiment, each tray 58A, 58B, 58C, 58D comprises locations for at least two rows of semiconductor substrates 56, preferably for at least four rows.of semiconductor substrates 56, more preferably at least eight rows of semiconductor substrates 56. The number of trays 58A, 58B, 58C, 58D may be between 5 and 100, preferably between 10 and 40. In particular, the number of trays 58A, 58B, 58C, 58D depends on the diameter of the enclosure 52 receiving the nacelle 54. In Figures 3, 4, 7, and 8, the nacelle 54 shown comprises ten trays 58A, 58B, 58C, 58D, and each inner tray 58A, 58B comprises locations for two rows and two columns of semiconductor substrates 56 on each face and each outer tray 58C, 58D comprises locations for two rows and two columns of semiconductor substrates 56. In Figures 5 and 6, each tray Interior 58A and 58B shown includes locations for two columns and six rows of semiconductor substrates 56 on each face.For example, a nacelle of thirty trays with two columns and seven rows each can contain 812 semiconductor substrates. Generally, an increase in the diameter of the enclosure 52 can make it possible to increase the number of trays 58A, 58B of the nacelle 54 and an increase in the height of the enclosure 52 can make it possible to increase the number of rows of the nacelle 54.

[0048] According to one embodiment, each plate 58A, 58B, 58C, 58D comprises, for each location, pads or pins 92 intended to come into abutment against the semiconductor substrate 56. At least some of the pads 92 are adapted to keep the substrate 56 pressed against the plate 58A, 58B, 58C, 58D. In FIGS. 5 and 6, each plate 58A, 58B, 58C, 58D comprises three pads 92 for each location. Each pad 92 may have a conical or truncated cone shape projecting from the face of the plate 90. Each pad 92 may project in relief relative to the face of the plate 90 over a height for example between 0.5 mm and 2 mm, for example of the order of 1 mm.

[0049] According to one embodiment, each inner tray 58A, 58B comprises, for each location, a recess or an imprint 94 intended to be covered by the semiconductor substrate 56. The outline of the recesses 94 is indicated in dashed lines in FIGS. 3, 4, 5 and 6. The recesses 94 may preferably be through-holes. This advantageously makes it possible, in particular, to reduce the weight of the tray, in order to reduce the thermal inertia of the nacelle 54 as well as its electrical resistance. According to one embodiment, the outer trays 58C, 58D do not comprise a through-hole for each location, but may comprise, for each location, a non-through-hole, also called an imprint, intended to be covered by the semiconductor substrate 56.The dimensions of each recess 94 are chosen so that, when the semiconductor substrate 56 is in position on the inner plate 58A, 58B, it substantially completely covers the underlying recess and is in contact with the plate 90 only around its periphery.

[0050] According to one embodiment, the spacing between two adjacent plates 58A, 58B, 58C, 58D is substantially constant, for example between 10 mm and 20 mm, preferably between 10 mm and 12 mm. The maximum thickness of each plate 58A, 58B, 58C, 58D is between 1 mm and 10 mm, preferably between 2 mm and 5 mm, for example of the order of 5 mm. Each semiconductor substrate 56 may have a thickness of between 100 μm and 200 μm. Each substrate 56 may, in the side view of FIGS. 5 and 6, have a substantially square shape, possibly with rounded corners, the side of which is between 100 mm and 220 mm. Generally, each substrate 56 may, in the side view of Figures 5 and 6, have a square or substantially square (commonly known as a full square or pseudosquare), rectangular, or circular shape.

[0051] The device 50 comprises means, not shown, for moving the nacelle 54, in particular to introduce it into the enclosure 52 or to remove it from the enclosure 52. The moving means may comprise an articulated arm. The enclosure 52 comprises a door 96, for example located at the base of the enclosure 52, which when open allows the introduction or removal of the nacelle 54 into the enclosure 52 (arrow 98 in [Fig. 3]). As a variant, the door 96 may be connected to the nacelle 54 and may hermetically close the enclosure 52 when the nacelle 54 is introduced into the enclosure 52.

[0052] The device 50 comprises reservoirs 100 of precursor gases and possibly at least one neutral gas and possibly a vaporization and vapor regulation system for supplying a precursor gas from a reservoir of a liquid precursor. The reservoirs 100 are connected, in particular via mass flow regulators, to a control panel 102 adapted to produce a gas mixture, containing precursor gases and possibly at least one neutral gas, which depends on the treatment to be carried out. The control panel 102 is connected to the enclosure 52 by a valve 104 which, when open, allows the introduction of the gas mixture into the enclosure 52 via a supply line 106. As a variant, certain gases or liquids in the vapor phase may optionally be regulated and introduced into the enclosure independently of a mixer.

[0053] The device 50 comprises a vacuum pump 108 connected to the enclosure 52 by one or more valves 110. By way of example, a single valve 110 is shown in [Fig. 3] which, when open, allows the gas mixture present in the enclosure 52 to be pumped through a pumping channel 112. According to one embodiment, the pumping channel 112 is located at the top of the enclosure 52 and the connections between the supply circuits 100 and 102 and the enclosure 52 are located at the base of the enclosure 52. As a variant, the pumping channel 112 may be located at the base of the enclosure 52 and the connections between the supply circuits 100 and 102 and the enclosure 52 may be located at the top of enclosure 52.

[0054] The device 50 further comprises at least one heating element 114 surrounding the enclosure 52, for example electrical resistors, making it possible to control the temperature of the plates 58A, 58B, 58C, 58D and of the gas mixture in the enclosure 52. According to one embodiment, the heating elements 114 can be controlled independently of each other.

[0055] The device 50 further comprises at least one generator 116 of an alternating voltage connected to the plates 58A, 58B, 58C, 58D. The inner plates 58A and the outer plate 58C are connected to a first terminal of the generator 116 of the alternating voltage and the inner plates 58B and the outer plate 58D are connected to a second terminal of the generator 116. Two adjacent plates 58A, 58B, 58C, 58D are electrically insulated from each other by the spacers 60.

[0056] The pedestal 70 may comprise a base 118 having a flat face on which the nacelle 54 rests and feet 120, corresponding, for example, to ceramic rods, extending from the base 118 and allowing the pedestal 70 to be manipulated. For example, the nacelle 54 may be installed on the pedestal 70, which is fixed to the door 96 by means of the feet 120. [Fig. 7] represents a pedestal 70 whose base 118 has, in top view, a shape complementary to the internal shape of the enclosure 52, for example in the form of a disc. [Fig. 8] represents a pedestal 70 whose base 118 has, in top view, a rectangular shape. This version facilitates the installation of systems 106 for injecting reactive gases depending on the height of the deposition enclosure.

[0057] The operation of the device 50 will now be described in the case of a PECVD process.

[0058] According to one embodiment, the nacelle 54 is mounted by assembling the plates 58A, 58B, 58C, 58D and the spacers 60. The nacelle 54 can be used for several successive deposition operations. A maintenance operation of the nacelle 54 can be planned after several deposition operations and include the disassembly of the nacelle 54 and the cleaning of the plates 58A, 58B, 58C, 58D.

[0059] According to another embodiment, the nacelle 54 can be manipulated using an articulated arm which ensures its movement into and out of the enclosure. In this configuration the nacelle is used for a certain number of deposits before being replaced by a new clean nacelle. Consequently, the used nacelle can be cleaned in masked time and be ready for reuse at a later date.

[0060] The semiconductor substrates 56 are placed on the trays 58A, 58B, 58C, 58D. According to one embodiment, the placement of the substrates 56 on the trays 58A, 58B, 58C, 58D is carried out using a robot equipped with a gripper, for example a Bernoulli effect gripper. The dimensions of the gripper are adapted so as to allow the insertion of the gripper equipped with one or more substrates 56 substrates 56 in the space between two adjacent trays 58A, 58B, 58C, 58D. A multiple gripper makes it possible to load one tray face on a row and a column and then move on to the second tray face of the same row and column. The same operation is carried out on the other rows. The loading of the second column is done either by turning the cradle 180° at the loading robot station or by means of a second robot located on the opposite side. In the latter case, the loading of the two columns can be done simultaneously at the substrate loading station.

[0061] The nacelle 54 loaded with the semiconductor substrates 56 is then introduced into the enclosure 52.

[0062] In operation, the gas mixture is introduced into the enclosure 52 via the supply lines 106. Each plate 58A, 58B, 58C, 58D acts as a thermal conductor and as a radiofrequency contact element with the semiconductor substrates 56 which rest thereon. The plates 58A, 58B, 58C, 58D are connected to the generator 116 so as to form an alternation of cathodes and anodes and a plasma is generated between each pair of adjacent plates 58A, 58B, 58C, 58D. For example, the frequency of the plasma controlled by the generator 116 is between 40 kHz and 2.45 GHz, for example of the order of 50 KHz. According to one embodiment, the generator 116 applies the alternating voltage to the plates 58A, 58B, 58C, 58D in a pulsed manner, that is to say by periodically alternating a phase Ln of application of the alternating voltage and a phase toff of absence of application of the alternating voltage. The period of the pulses can vary between 10 ms and 200 ms.The duty cycle of the pulsations, i.e. the ratio between the duration of the tone phase and the period of the pulsations, can be about 10%.

[0063] The heating elements 114 can be controlled to obtain a uniform temperature in the enclosure 52 or to obtain a temperature gradient in the enclosure 52, for example in the vertical direction. Depending on the treatment carried out, the temperature in the enclosure 52 can be regulated between 200°C and 600°C.

[0064] According to one embodiment, each substrate 56 is a monocrystalline or polycrystalline silicon substrate and the device 50 is used for depositing a thin layer, for example an electrically insulating layer, on each substrate 56. As a variant, the processing device can be used to carry out etching operations on semiconductor substrates, in particular plasma etching operations. The insulating layer can be a layer of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon carbide (SiC), silicon carbonitride (SiCN), aluminum oxide (A1OX), boron silicate glass, phosphorus silicate glass, or boron-doped or phosphorus-doped or intrinsic amorphous silicon. The gases introduced into the enclosure 52 can be chosen in the group comprising silane (SiH4), ammonia (NH3), trimethylaluminum (TMA), nitrous oxide (N2O), nitrogen trifluoride (NF3), methane (CH4), boron trichloride (BC13), dioxygen (O2), nitrogen (N2), argon (Ar), diborane (B2 H6), phosphine (PH3), trimethylborate (TMB), trimethylphosphate (TMP), and triethylorthosilicate (TEOS). The thickness of the deposited layer may be between 5 nm and 150 nm, preferably between 10 nm and 100 nm, for example of the order of 40 nm.

[0065] The vacuum pump 108 is started so as to maintain a pressure in the enclosure 52 of between 67 Pa (approximately 0.5 Torr) and 667 Pa (approximately 5 Torr). According to one embodiment, the vacuum pump 108 can operate continuously. An isolation valve, provided between the vacuum pump 108 and the pumping channel 112, makes it possible to interrupt the pumping carried out by the vacuum pump and a regulating valve, provided between the vacuum pump 108 and the pumping channel 112, makes it possible to control the pressure in the enclosure 52 according to the pumping flow rate.

[0066] The precursor gases will decompose to form a deposit of a thin layer on the exposed face of the substrates 56.

[0067] At the end of the treatment, the nacelle 54 is removed from the enclosure 52 and the treated substrates 56 are removed from each tray 5 8A, 58B, 58C, 58D.

[0068] Advantageously, the distance between two adjacent trays 58A, 58B, 58C, 58D of the nacelle 54 is substantially constant. The design of the nacelle 54 is then simplified and the placement of the semiconductor substrates 56 on the trays 58A, 58B, 58C, 58D, for example in an automated manner, is also simplified.

[0069] The recesses 94 allow the free circulation of air under the substrate 56, which is favorable to the proper functioning of a Bernoulli effect gripper, in particular when the substrate 56 is removed from the plate 58A, 58B, 58C, 58D and avoids the risk of adhesion of the substrate 56 to the plate 58A, 58B, 58C, 58D which could result from direct contact of too large a surface area between the substrate 56 and the plate 58A, 58B, 58C, 58D.

[0070] The device 50 advantageously has a reduced floor space. Furthermore, an increase in the processing capacity of the device 50 can be achieved by increasing the number of rows per tray 58A, 58B, 58C, 58D, and therefore advantageously without causing any change in the floor space of the device 50. The height of the nacelle is limited by the ceiling height after opening the device 50. The ceiling height of photovoltaic cell production lines is generally set at approximately 4 meters.

[0071] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. profession. In particular, although examples of thin film deposition processing have been described, the processing device may be used to carry out etching operations of semiconductor substrates or silicon-based thin films, in particular plasma etching operations.

[0072] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A support (54) for semiconductor substrates (56) comprising a set of trays (58A, 58B, 58C, 58D) on which the semiconductor substrates rest, each tray being made of an electrically conductive material and having at least one substantially vertical face having locations arranged in at least two horizontally oriented rows and two vertically oriented columns, each location being configured to receive a semiconductor substrate oriented with an inclination relative to a vertical direction varying from 1° to 10°, each tray comprising, at each location, a recess (94) or an imprint covered by the substrate (56), the trays of each pair of trays facing each other being separated by electrically insulating spacers (60), wherein the set of trays comprises inner trays (58A, 58B) sandwiched between two outer trays (58C, 58D),each inner tray having two substantially vertical parallel faces each having locations arranged in at least two horizontally oriented rows and two vertically oriented columns, each location of each face receiving a semiconductor substrate (56) oriented with an inclination relative to a vertical direction varying from 1° to 10°.,

2. A support according to claim 1, wherein said face of each tray (58A, 58B, 58C, 58D) has locations arranged in at least three horizontally oriented rows and two vertically oriented columns.

3. A support according to claim 2, wherein said face of each tray (58A, 58B, 58C, 58D) has locations arranged in at least five horizontally oriented rows and two vertically oriented columns.

4. A support according to claim 3, wherein said face of each tray (58A, 58B, 58C, 58D) has locations arranged in five to ten horizontally oriented rows and two vertically oriented columns.

5. A support according to any one of claims 1 to 4, comprising from 10 to 40 trays (58A, 58B, 58C, 58D).

6. A support according to any one of claims 1 to 5, wherein the two outer plates each comprise a single sen- ably vertical having locations arranged in at least two horizontally oriented rows and two vertically oriented columns, each location receiving a semiconductor substrate (56) oriented with an inclination relative to a vertical direction varying from 1° to 10°.

7. Support according to any one of claims 1 to 5, in which each inner plate (58A, 58B) comprises, at each location, a recess (94) passing through and intended to be covered on each of the two faces of the inner plate by one of the substrates (56).

8. Support according to any one of claims 1 to 5, in which each outer plate (58A, 58B) comprises, at each location, a non-through imprint (94) in said face of the outer plate and intended to be covered by the substrate (56).

9. Support according to any one of claims 1 to 6, in which each tray (58A, 58B, 58C, 58D) comprises at least one leg (76), the support (54) comprising at least a first rod (80) electrically conductive and connected to the legs of first trays (58C, 58A) of said set of trays and a second rod (84) electrically conductive and connected to the legs of second trays (58D, 58B) of said set of trays, said set comprising an alternation of the first and second trays.

10. Support according to any one of claims 1 to 7, in which each plate (58A, 58B, 58C, 58D) comprises, for each location, pads (92) projecting relative to said face and which are configured to be in contact with the semiconductor substrate (56) present at said location.

11. Device (50) for processing semiconductor substrates (56), the device comprising an enclosure (52) with a substantially vertical axis and at least one circuit (100, 102) for supplying a gas mixture into the enclosure, the device further comprising, in the enclosure, at least one support (54) for the semiconductor substrates according to any one of claims 1 to 10, the processing device further comprising at least one radiofrequency generator (116) of an alternating voltage electrically connected to several of said plates.

12. Device according to claim 11, comprising a vacuum pump (108) connected to the enclosure (52).

13. A device according to claim 11 or 12, wherein the enclosure (52) is made of stainless steel.

14. Device according to any one of claims 11 to 13, for the treatment of semiconductor substrates (56) intended for the manufacture of photovoltaic cells.

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