Semiconductor chip manufacturing process

Abstract

Semiconductor Chip Fabrication Method This description relates to a method for manufacturing a semiconductor chip, comprising the following steps: a) providing a substrate (101) of doped single-crystal silicon; b) forming by epitaxy, on and in contact with the upper surface of the substrate (101), a layer (103) of doped single-crystal silicon; c) before or after step b), and before any other heat treatment step at a temperature between 600°C and 900°C, applying a stripping heat treatment to the substrate at a temperature of 1000°C or higher for several hours. Figure for the abstract: Fig. 2

Description

Title of the invention: Method for manufacturing semiconductor chips Technical field

[0001] The present description relates generally to the field of semiconductor chip manufacturing processes. Prior art

[0002] We are particularly interested here in the manufacture of semiconductor chips in BCD (BIPOLAR-CMOS-DMOS) technology, that is to say chips comprising both bipolar transistors, CMOS transistors (from the English "Complementary Metal Oxide Semiconductor" - complementary metal oxide semiconductor) and DMOS transistors (from the English "Double Diffused Metal Oxide Semiconductor" - double diffusion metal oxide semiconductor).

[0003] The known methods for manufacturing semiconductor chips using BCD technology have various drawbacks that it would be desirable to overcome in whole or in part. Summary of the invention

[0004] An object of an embodiment overcomes all or part of the drawbacks of known methods for manufacturing semiconductor chips in BCD technology.

[0005] One embodiment provides a method of manufacturing a semiconductor chip, comprising the following steps: a) providing a doped monocrystalline silicon substrate; b) forming by epitaxy, on and in contact with the upper face of the substrate, a layer of doped monocrystalline silicon; c) before or after step b), and before any other heat treatment step at a temperature between 600°C and 900°C, apply a stripping heat treatment to the substrate, at a temperature greater than or equal to 1000°C for several hours.

[0006] According to one embodiment, the substrate is P-type doped and the monocrystalline silicon layer is P-type doped.

[0007] According to one embodiment, the substrate has a first doping level, and the monocrystalline silicon layer has a second doping level lower than the first level.

[0008] According to one embodiment, the substrate has a doping level greater than 5*10 atoms / cm , for example greater than 10 atoms / cm .

[0009] According to one embodiment, the substrate is doped with boron.

[0010] According to one embodiment, the epitaxial layer has a doping level of less than 1016 atoms / cm3, for example of the order of 1015 atoms / cm3.

[0011] According to one embodiment, in step c), the substrate is maintained at a temperature greater than or equal to 1100°C for at least four hours.

[0012] According to one embodiment, the method comprises, after steps b) and c), a step of forming vertical isolation trenches crossing the epitaxial layer and opening into the substrate.

[0013] According to one embodiment, the method comprises a step of forming an insulating layer on the side walls and at the bottom of the trenches, and a step of filling the trenches with an electrically conductive material, for example polycrystalline silicon.

[0014] Another embodiment provides a method of manufacturing a semiconductor substrate, comprising the following steps: a) providing a first doped monocrystalline silicon substrate; b) forming by epitaxy, on and in contact with the upper face of the first substrate, a layer of doped monocrystalline silicon; c) before or after step b), and before any other heat treatment step at a temperature between 600°C and 900°C, applying a stripping heat treatment to the first substrate, at a temperature greater than or equal to 1000°C for several hours.

[0015] Another embodiment provides a device comprising a doped monocrystalline silicon substrate and, on and in contact with the upper face of the substrate, an epitaxial layer of doped monocrystalline silicon, in which the substrate comprises a stripped upper layer having an interstitial oxygen concentration lower than the interstitial oxygen concentration of a lower part of the substrate, said stripped layer extending from the upper face of the substrate and having a thickness greater than or equal to 15 μm.

[0016] According to one embodiment, the substrate is P-type doped and the monocrystalline silicon layer is P-type doped.

[0017] According to one embodiment, the substrate has a first doping level, and the monocrystalline silicon layer has a second doping level lower than the first level.

[0018] According to one embodiment, the stripped layer has a BMD density lower than the BMD density of the lower part of the substrate.

[0019] According to one embodiment, the device comprises a lateral isolation trench, said trench extending vertically through the epitaxial layer and opening into the stripped layer of the substrate.

[0020] According to one embodiment, a distance greater than or equal to 10 μm separates the bottom of the lateral insulation trench from the lower face of the stripped layer.

[0021] According to one embodiment, the device comprises transistors formed in and on the epitaxial layer.

[0022] According to one embodiment, the transistors comprise bipolar transistors, CMOS transistors, and DMOS transistors. Brief description of the drawings

[0023] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0024] [Fig.l] is a sectional view schematically showing a portion of an example of a semiconductor chip;

[0025] [Fig.2] is a sectional view schematically showing a portion of an example of a semiconductor chip according to one embodiment;

[0026] [Fig. 3] is a diagram illustrating the evolution, as a function of depth, of the interstitial oxygen concentration in the substrate of a semiconductor chip according to one embodiment;

[0027] [Fig.4] is a diagram illustrating the evolution, as a function of depth, of the density of micro defects in the substrate of a semiconductor chip according to one embodiment;

[0028] [Fig.5] is a block diagram showing an example of a method for manufacturing a semiconductor chip according to one embodiment; and

[0029] [Fig. 6] is a block diagram showing another example of a method for manufacturing a semiconductor chip according to one embodiment. Description of the embodiments

[0030] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0031] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, only certain steps for producing the semiconductor chips have been detailed. The complete production of the semiconductor chips is within the reach of those skilled in the art using known steps of the semiconductor chip manufacturing process.

[0032] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when we refer to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0033] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0034] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0035] [Fig.l] is a sectional view schematically showing a portion of an example of a semiconductor chip using BCD technology.

[0036] The chip comprises a substrate 101 made of heavily doped P-type (P++) monocrystalline silicon. The substrate 101 has, for example, an electrical resistivity of the order of 10 mΩ.cm or greater. For example, the substrate 101 has a doping level greater than 5*10 atoms / cm, for example of the order of 10 atoms / cm or greater. The substrate 101 is, for example, doped with boron.

[0037] The chip further comprises, on and in contact with the upper face of the substrate 101, an epitaxial layer 103 of lightly doped P-type monocrystalline silicon (P-). The epitaxial layer 103 has, for example, an electrical resistivity of the order of 50 Q.cm or lower, for example of the order of 10 Q.cm. By way of example, the epitaxial layer 103 has a doping level of less than 1016 atoms / cm3, for example of the order of 1015 atoms / cm3. The thickness of the epitaxial layer 103 is, for example, between 3 and 15 pm, for example of the order of 20 pm.

[0038] The chip of [Fig.l] comprises for example electronic components, in particular transistors, not detailed, formed in and on the epitaxial layer 103.

[0039] The chip further comprises vertical isolation trenches 105, laterally isolating different portions of the chip. For the sake of simplification, a single trench 105 has been shown in [Fig.l]. The trench 105 extends vertically from the upper face of the epitaxial layer 103, passes entirely through the epitaxial layer, and is interrupted in an upper portion of the substrate 101. In this example, the side walls of the trench 105 are coated with an insulating layer 107, for example made of silicon oxide, and the trench is filled with an electrically conductive region 109, for example made of polycrystalline silicon, preferably doped polycrystalline silicon, for example boron-doped polycrystalline silicon. In the example shown, the insulating layer 107 is interrupted at the bottom of the trench 105. Thus, the conductive region 109 is in contact with the substrate 101 at the bottom of the trench 105, and laterally insulated from the epitaxial layer 103 by the insulating layer 107. As a variant, the insulating layer 107 is not interrupted at the bottom of the trench, insulating the conductive region 109 from the substrate 101. In another variant, the trench 105 is entirely filled with an insulating material, for example silicon oxide. The trench 105 has for example a depth of between 15 and 35 pm, for example of the order of 27 pm.

[0040] As shown schematically in [Fig.l], the substrate 101 comprises micro-defects 111 also called BMD (from the English "Bulk Micro Defect" - substrate micro-defect). The micro-defects 111 are linked to the presence of interstitial oxygen in the substrate 101, resulting from the substrate manufacturing process. During the various stages of manufacturing the chip, certain heat treatments, typically at temperatures between 600°C and 900°C, for example between 600 and 800°C, for example between 700°C and 800°C, lead to the formation of silicon dioxide (SiO2) nuclei, which develop into BMD. The dimensions of the BMD are for example of the order of a few nanometers to 1 micrometer. The BMD density is particularly high in a heavily boron-doped substrate, as used for the fabrication of semiconductor chips in BCD technology.

[0041] As has been schematically shown in [Fig.l], an upper surface portion 101a of the substrate does not contain or contains a reduced density of BMDs. The BMDs are concentrated mainly in a lower portion 101b of the substrate 101 located under the portion 101a. The absence or reduced density of BMDs in the upper portion 101a of the substrate is linked to the fact that at the beginning of the chip manufacturing process, before the nucleation of the BMDs, the substrate is subjected to high temperatures, for example above 1000°C or even above 1100°C. Such a high-temperature heat treatment occurs for example during the formation of the epitaxial layer 103. At this temperature, the nucleation of the BMDs does not occur. On the other hand, an exo-diffusion of the interstitial oxygen present in the upper portion 101a of the substrate occurs.In other words, the upper part 101a of the substrate, called the denuded zone, becomes depopulated of interstitial oxygen. The upper part 101a of the substrate thus has a relatively low interstitial oxygen concentration. As a result, in the rest of the process, BMDs do not form in the upper part 101a of the substrate.

[0042] In the example shown in [Fig.l], the trench 105 is interrupted in the stripped area 101a of the substrate 101, before reaching the lower part 101b containing the BMDs. However, the distance between the bottom of the trench 105 and the lower (non-stripped) part 101b of the substrate is relatively small. For example, the thickness of the stripped area 101a is less than 10 μm, and the distance between the bottom of the trench 105 and the lower (non-stripped) part 101b of the substrate 101 is less than 5 pm, for example less than 2 pm. In this configuration, the stress induced by the trenches 105 can cause dislocations having as starting points BMDs located in the vicinity of the bottom of the trenches 105 and which can extend to the upper face of the epitaxial layer 103. An example of such a dislocation 113 has been shown schematically in [Fig.l]. Such dislocations can lead to malfunctions of the chip, and in particular to current leaks. In other examples (not shown), the trench 105 can reach the lower part 101b containing the BMDs, in which case the situation is even worse.

[0043] [Fig.2] is a sectional view schematically showing a portion of an example of an embodiment of a semiconductor chip using BCD technology.

[0044] The chip of [Fig. 2] differs from the chip of [Fig. l] essentially in that, in the chip of [Fig. 2], the thickness of the stripped area 101a of the substrate 101 is greater than that of the chip of [Fig. l]. Thus, in the chip of [Fig. 2], the distance between the bottom of the trench 105 and the lower part 101b (not stripped of the substrate) is greater than that of the chip of [Fig. l].

[0045] For example, in the chip of [Fig.2], the thickness of the stripped area 101a is greater than or equal to 15 μm, for example greater than or equal to 20 μm, for example between 15 and 40 μm. The distance between the bottom of the trench 105 and the lower (non-stripped) part 101b of the substrate is for example greater than or equal to 10 μm, for example between 10 and 20 μm.

[0046] Increasing the distance between the bottom of the trenches 105 and the BMDs makes it possible to avoid the formation of dislocations under the effect of the stress induced by the trenches 105.

[0047] According to one aspect of an embodiment, and as will be described in more detail below in relation to FIGS. 5 and 6, to obtain a stripped zone 101a sufficiently deep to avoid dislocations, there is provided, before or after a step of forming the epitaxial layer 103, and before any other heat treatment step of significant duration, for example of duration greater than 30 minutes or greater than 60 minutes, at a temperature between 600 and 900°C, for example between 600 and 800°C (nucleation range of the BMDs), a specific heat treatment step called stripping treatment, during which the substrate 101 is brought to a temperature greater than or equal to 1000°C, for example greater than or equal to 1100°C, for example greater than or equal to 1150°C, for a duration of several hours, for example for more than four hours, for example for a duration of the order of six hours.

[0048] The stripping heat treatment makes it possible, before the nucleation of the BMDs, to diffuse the interstitial oxygen of the substrate outside an upper layer 101a of relatively high thickness, for example between 15 and 40 μm. During the nucleation of the BMDs, the latter then form essentially under the denuded zone 101a, in the lower part 101b of the substrate.

[0049] [Fig. 3] is a diagram illustrating the evolution, as a function of the depth (on the abscissa in micrometers), of the interstitial oxygen concentration, (on the ordinate, in atoms / cm3), in the stack formed by the substrate 101 and the epitaxial layer 103.

[0050] As shown in the curve of [Fig. 3], the interstitial oxygen concentration is relatively low in layers 103 and 101a, and relatively high in the lower portion 101b of the substrate 101, and exhibits a steep step at the interface between the stripped area 101a and the lower portion 101b of the substrate 101.

[0051] [Fig.4] is a diagram illustrating the evolution, as a function of the depth (on the abscissa in micrometers), of the BMD density (on the ordinate, in cm3) in the stack formed by the substrate 101 and the epitaxial layer 103.

[0052] As shown in the curve of [Fig.4], the BMD density is zero or negligible in the epitaxial layer 103 and in the stripped area 101a of the substrate, and relatively high in the lower part 101b of the substrate 101, and has a steep step at the interface between the stripped area 101a and the lower part 101b of the substrate 101.

[0053] [Fig.5] is a diagram representing, in block form, an example of a method for manufacturing a semiconductor chip in BCD technology according to one embodiment.

[0054] The method of [Fig. 5] comprises a step 151 of providing or supplying the substrate 101. At this stage, the substrate 101 is for example a bare substrate of heavily doped P-type monocrystalline silicon. The thickness of the substrate 101 is for example in the range from 720 to 780 μm. The substrate 101 has for example a generally circular shape with a diameter of the order of 200 or 300 mm.

[0055] During step 151, substrate preparation steps may be implemented, for example a step of double-sided polishing of the substrate, i.e. a step of polishing the lower and upper faces of the substrate, followed by a step of depositing a low-temperature oxide on the rear surface of the substrate. Optionally, a layer of polycrystalline silicon may be formed between the low-temperature oxide and the substrate.

[0056] After step 151, a heat treatment step 153 is implemented, this step corresponding to the heat treatment step of stripping the substrate 101. During step 153, the substrate 101 is maintained at a temperature greater than or equal to 1000°C, for example greater than or equal to 1100°C, for example greater than or equal to 1150°C, for example of the order of 1200°C, for a duration of several hours, for example for more than four hours, for example for a duration of the order of six hours. This step is carried out before any other heat treatment step of the substrate 101 of significant duration, for example of duration greater than 30 minutes or greater than 60 minutes, at a temperature between 600 and 900°C, for example between 600 and 800°C, (nucleation range of the BMDs). The stripping heat treatment can be carried out in a neutral atmosphere, for example in an atmosphere consisting mainly of argon or nitrogen (N2), and, optionally, a small amount of oxygen (O2), for example less than 5% oxygen. Alternatively, pure hydrogen, at atmospheric pressure or at a pressure below atmospheric pressure, can be used. During this step, all or part of the interstitial oxygen initially present in the upper part 101a of the substrate 101 diffuses outside said part 101a, so as to obtain an upper part 101a devoid of interstitial oxygen.

[0057] After step 153, a step 155 of forming a lower part of the epitaxial layer 103 is implemented. For example, during this step, an epitaxial layer of lightly doped P-type monocrystalline silicon, for example with a thickness of the order of 15 μm, is formed on and in contact with the upper face of the substrate 101.

[0058] In this example, after step 155, a step 157 is implemented for implanting an N-type doping element, for example antimony, in an upper surface part of the epitaxial silicon layer formed in step 155. After this surface implantation, an activation annealing of the doping elements can be implemented, for example at a temperature in the range from 1100 to 1200°C.

[0059] After step 157, a step 159 of forming an upper part of the epitaxial layer 103 is implemented. During this step, an epitaxial layer of lightly doped P-type monocrystalline silicon, for example with a thickness of the order of 4 μm, is formed on and in contact with the upper face of the epitaxial layer formed in step 155. The layer 103 is formed by the stacking of the epitaxial layers formed in steps 155 and 159.

[0060] In [Fig. 5], a step 161 subsequent to step 159 has been shown. This step schematically represents the remainder of the semiconductor chip manufacturing process, including in particular the formation of transistors in and on the epitaxial layer 103, and the formation of the isolation trenches 105. This process includes in particular heat treatment steps at temperatures between 600°C and 900°C, for example between 600 and 800°C, for example of the order of 800°C, leading to the nucleation of the BMDs in the lower part 101b of the substrate 101.

[0061] Alternatively, steps 157 and 159 may be omitted. In this case, layer 103 is formed in a single epitaxy step (step 155), after the stripping heat treatment step.

[0062] [Fig.6] is a diagram representing, in block form, another example of a method of manufacturing a semiconductor chip in BCD technology according to one embodiment.

[0063] The method of [Fig. 6] differs from the method of [Fig. 5] essentially in that, in the method of [Fig. 6], the stripping heat treatment step 153 is carried out after the first epitaxy step 155, and before any other heat treatment step of the substrate 101 of significant duration, for example of duration greater than 30 minutes or greater than 60 minutes, at a temperature between 600 and 900°C, for example between 600 and 800°C (nucleation range of the BMDs).

[0064] Steps 157, 159 and 161 are successively implemented after step 153.

[0065] As a variant, steps 157 and 159 can be omitted. In this case, layer 103 is formed in a single epitaxy step (step 155), before the stripping heat treatment step.

[0066] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to those skilled in the art. In particular, although an example of application to semiconductor chips in BCD technology has been described above, the described embodiments are not limited to this particular case. In particular, the described embodiments apply to the production of any chip comprising a substrate made of P-type doped monocrystalline silicon with a first doping level, coated with an epitaxial layer of P-type doped monocrystalline silicon with a second doping level lower than the first level. More generally, the described embodiments apply regardless of the type of dopant and the doping level of the substrate 101 and the epitaxial layer 103.For example, the described embodiments apply to a P-type substrate 101 coated with an N-type epitaxial layer 103, or to an N-type substrate 101 coated with an N-type epitaxial layer 103, or to an N-type substrate 101 coated with a P-type epitaxial layer 103. In addition, the embodiments apply to the case where the substrate 101 has a doping level lower than that of the epitaxial layer 103. The described embodiments are particularly advantageous in the case of chips comprising vertical isolation trenches entirely passing through the epitaxial layer and opening into the substrate.

[0067] Furthermore, the described embodiments are not limited to the dimension examples mentioned above.

Claims

Claims

1. Method for manufacturing a semiconductor chip, comprising the following steps: a) providing a substrate (101) of doped monocrystalline silicon; b) forming by epitaxy, on and in contact with the upper face of the substrate (101), a layer (103) of doped monocrystalline silicon; c) before or after step b), and before any other heat treatment step at a temperature between 600°C and 900°C, applying to the substrate a stripping heat treatment, at a temperature greater than or equal to 1000°C for several hours, the method comprising, after steps b) and c), a step of forming vertical isolation trenches (105) passing through the epitaxial layer (103) and opening into the substrate (101).

2. The method of claim 1, wherein the substrate (101) is P-type doped and the monocrystalline silicon layer (103) is P-type doped.

3. The method of claim 2, wherein the substrate (101) has a first doping level, and the monocrystalline silicon layer (103) has a second doping level lower than the first level.

4. A method according to any one of claims 1 to 3, wherein the substrate (101) has a doping level greater than 5*1017 atoms / cm3, for example greater than 1018 atoms / cm3.

5. A method according to any one of claims 1 to 4, wherein the substrate (101) is doped with boron.

6. Method according to any one of claims 1 to 5, in which the epitaxial layer (103) has a doping level of less than 10 16 atoms / cm3, for example of the order of 1015 atoms / cm3.

7. A method according to any one of claims 1 to 6, wherein, in step c), the substrate (101) is maintained at a temperature greater than or equal to 1100°C for at least four hours.

8. A method according to any one of claims 1 to 7, comprising a step of forming an insulating layer (107) on the side walls and at the bottom of the trenches (105), and a step of filling the trenches (109) with an electrically conductive material, for example polycrystalline silicon.

9. A method of manufacturing a semiconductor substrate, comprising the following steps: a) providing a first substrate (101) made of doped monocrystalline silicon; b) forming by epitaxy, on and in contact with the upper face of the first substrate (101), a layer (103) of doped monocrystalline silicon; c) before or after step b), and before any other heat treatment step at a temperature between 600°C and 900°C, applying a stripping heat treatment to the first substrate, at a temperature greater than or equal to 1000°C for several hours, the method comprising, after steps b) and c), a step of forming vertical insulation trenches (105) passing through the epitaxial layer (103) and opening into the substrate (101).

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