Power switch

Abstract

Power Supply Switch This description relates to a device (1) comprising a first terminal (200) for connection to a source of a first supply potential (Vbat), a second terminal (202) configured to provide a second supply potential (Vsw), and a third terminal (204) for connection to a second source of a third supply potential (Vdd). The device (1) comprises a first PMOS transistor (T1) having a source connected to the second terminal (202) and a drain connected to the third terminal (204), a second PMOS transistor (T2) having a source connected to the second terminal (202), and a third PMOS transistor (T3) having a source connected to the first terminal (200) and a drain connected to the drain of the second transistor (T2). Figure for the abstract: Fig. 1

Description

Description Title of the invention: Power switch Technical field This description relates generally to electronic circuits, and more particularly to switches. Prior art Switches are circuit elements, for example integrated circuits, receiving several signals and providing, on an output terminal of the switch, a signal selected from among the received signals. The signal selected from among the received signals is determined on the basis of at least one control signal supplied to the switch. Power switches receive supply potentials and provide a supply potential selected from the received supply potentials. Known power switches suffer from various drawbacks. Summary of the Invention There is a need to overcome at least some of the disadvantages of known power switches. One embodiment overcomes all or part of the disadvantages of known power switches. For example, it would be desirable to have a power switch that is less bulky than known power switches. For example, it would be desirable to have a power switch implemented with MOS (Metal Oxide Semiconductor) transistors configured to withstand a maximum gate-source voltage lower than the supply potentials received by the power switch and the supply potential supplied by the power switch. For example, it would also be desirable to have a power switch and a switch control circuit that is powered by the power supply potentials received by the power switch and the power supply potential supplied by the power switch, and that is implemented with MOS transistors configured to withstand a maximum gate-source voltage substantially equal to, or even equal to, the maximum gate-source voltage that the MOS transistors of the switch can withstand, the latter being lower than at least one of the voltages received and supplied by the switch. For example, it would be desirable to have a power switch and of a switch control circuit which allows to reduce current leaks in the switch. One embodiment provides a device comprising: - a first terminal intended to be connected to a first voltage source providing a first supply potential referenced to ground; - a second terminal configured to provide a second supply potential referenced to ground: - a third terminal intended to be connected to a second voltage source providing a third supply potential referenced to ground; - a first PMOS transistor having a source connected to the second terminal and a drain connected to the third terminal: - a second PMOS transistor having a source connected to the second terminal; and - a third PMOS transistor having a source connected to the first terminal and a drain connected to the drain of the second PMOS transistor. According to one embodiment, the device further comprises a control circuit for the first, second and third transistors, the control circuit being configured to receive the first, second and third supply potentials. According to one embodiment, the control circuit is configured to receive a first binary signal, and to control the first, second and third transistors at least on the basis of the first signal, a first binary state of the first signal corresponding to a request to the control circuit to turn on the second and third transistors and turn off the first transistor, and a second binary state of the first signal corresponding to a request to the control circuit to turn off the second and third transistors and turn on the first transistor. According to one embodiment, the control circuit is further configured to condition a switching on of the second and third transistors on the fact that the first potential is non-zero. According to one embodiment, the control circuit is further configured to compare the third supply potential to ground, and to force the third transistor to be turned on if the third supply potential is zero. According to one embodiment, the control circuit comprises: a first circuit configured to provide a first high reference potential equal to A times the first supply potential and a first low reference potential equal to B times the first supply potential, with A and B positive numbers strictly less than 1, A being greater than B; and a second circuit configured to provide a second high reference potential equal to C times the second supply potential and a second low reference potential equal to D times the second supply potential, with C and D positive numbers strictly less than 1, C being greater than D. According to one embodiment, a maximum potential difference that can be applied between the gate and the source of each of the first, second and third transistors determines the numbers A, B, C and D. According to one embodiment, the control circuit comprises: a third circuit configured to receive a second binary signal between ground and the first high reference potential and to provide, to the gate of the third transistor, a third binary signal determined by the second signal and between the first low reference potential and the first supply potential; a fourth circuit configured to receive a fourth binary signal between ground and the second high reference potential and to provide, to the gate of the second transistor, a fifth binary signal determined by the fourth signal and between the second low reference potential and the second supply potential; and a fifth circuit configured to receive a sixth binary signal between ground and the second high reference potential and to provide, to the gate of the first transistor, a seventh binary signal determined by the sixth signal and between the second low reference potential and the second supply potential. According to one embodiment, the control circuit comprises: a sixth circuit configured to be powered between the second high reference potential and ground, to receive the first binary signal, to provide the fourth and sixth signals; a seventh circuit configured to be powered between the first high reference potential and ground, to receive a binary signal from the sixth circuit between the second high reference potential and ground, and to provide the second binary signal at least from the binary signal received from the sixth circuit. According to one embodiment, the sixth circuit is configured to determine the state of the fourth and sixth signals and the binary signal that the sixth circuit provides to the seventh circuit at least based on the first signal. According to one embodiment: the control circuit further comprises an eighth circuit configured to receive the first high reference potential, to detect when the first high reference potential is strictly positive, and to provide the sixth circuit with an eighth binary signal between the second high reference potential and ground and having a binary state determined by said detection, and the sixth circuit is configured to determine the state of the fourth and sixth signals and the binary signal that the sixth circuit provides to the seventh circuit at least on the basis of the first signal and the eighth signal. According to one embodiment, the seventh circuit comprises a ninth circuit configured to receive the binary signal received from the sixth circuit and provide a ninth binary signal determined by the received binary signal and comprised between ground and the first high reference potential, the seventh circuit being configured to determine the state of the second binary signal at least on the basis of the ninth binary signal. According to one embodiment: the control circuit comprises a tenth circuit configured to provide a third high reference potential equal to E times the third supply potential, with E a positive number strictly less than 1 determined by the maximum potential difference that can be applied between the gate and the source of each of the first, second and third transistors; the control circuit comprises an eleventh circuit configured to receive the third high reference potential, to detect when the third high reference potential is strictly positive, and to provide the seventh circuit with a tenth binary signal between the first high reference potential and ground and having a binary state determined by said detection; and the seventh circuit is configured to determine the state of the second binary signal at least the basis of the binary signal received from the sixth circuit and the tenth signal. According to one embodiment, the first, second and third PMOS transistors are extended drain. According to one embodiment, the device further comprises the first and second voltage sources. Brief description of the drawings These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: [Fig.1] shows an embodiment of a device comprising a power switch and a switch control circuit; [Fig.2] represents an example of an embodiment of a method for controlling the switch of [Fig.1]; [Fig.3] shows another embodiment of the switch of [Fig.1]; [Fig.4] represents, in block form and in more detail, an embodiment of the control circuit of the switch of [Fig.3]; and [Fig.5] illustrates one embodiment of a method of providing a control signal to the control circuit of [Fig.4]. Description of the embodiments The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed. In particular, the various usual electronic circuits and systems in which a power switch may be provided have not been detailed, the embodiments described being compatible with these usual circuits and systems. Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements. In the following description, when reference is made to absolute position qualifiers, such as the terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or relative position qualifiers, such as the terms “above”, “below”, “upper”, “lower”, etc., or to orientation qualifiers, such as the terms “horizontal”, “vertical”, etc., reference is made unless otherwise specified to the orientation of the figures. Unless otherwise specified, the expressions 'about', 'approximately', 'substantially', and 'of the order of' mean to within 10%, preferably to within 5%. [Fig. 1] represents an embodiment of device 1] comprising a power switch 2 and a circuit 3 for controlling the switch 2. Switch 2, delimited by dotted lines in [Fig.1], comprises a terminal 200, a terminal 202 and a terminal 204. Terminal 200 is intended to receive a supply potential Vbat, for example referenced to ground GND and positive. In other words, terminal 200 is intended to be connected to a voltage source 4 supplying the potential Vbat to terminal 200. For example, the voltage source 4 is a battery. For example, the potential Vbat has values up to 3.6 V. For example, the value of the potential Vbat may vary during operation of the device 1, for example between a zero value and a maximum value, for example equal to 3.6 V. Terminal 204 is intended to receive a power supply potential Vdd, for example referenced to ground GND and positive. In other words, terminal 204 is intended to be connected to a voltage source 5 providing the potential Vdd to terminal 204. For example, voltage source 5 is a main power source of a system comprising the device 1. For example, the potential Vdd has a nominal value of 3.6 V. For example, the value of the potential Vdd may vary during the operation of the device 1, for example between a zero value and a maximum value, for example equal to 3.6 V. For example, the potential Vdd has a maximum value when the device 1 is connected to the main power supply, and a zero value otherwise. Terminal 202 is configured to provide a power supply potential Vsw, for example referenced to ground GND and positive. For example, potential Vsw is generated from potentials Vbat and Vdd received by switch 2. For example, potential Vsw is the power supply potential of one or more electronic circuits coupled to terminal 202, or, in other words, terminal 202 is coupled to one or more electronic circuits configured to be powered by potential Vsw. Switch 2 includes a transistor T1. Transistor T1 is a P-channel MOS transistor, or PMOS. Transistor T1 couples terminal 202 to terminal 204. Switch 2 includes a single transistor, namely transistor T1, between its terminals 202 and 204. For example, transistor T1 has its source S1 connected to terminal 202 and its drain D1 connected to terminal 204. The source S1 of transistor T1 is connected to the body region, or channel-forming region, of transistor T1. The intrinsic diode Dil of transistor T1 therefore has its anode on the terminal 204 side, and its cathode on the terminal 202 side. Switch 2 includes a transistor T2 and a transistor T3 in series between terminals 202 and 200. Transistors T2 and T3 are P-channel MOS transistors, or PMOS. Transistors T2 and T3 couple terminal 202 to terminal 200. Between terminals 202 and 200, switch 2 includes only two transistors, namely transistors T2 and T3. For example, transistor T2 has its source S2 connected to terminal 202. The source S2 of transistor T2 is connected to the body region of transistor T2. The intrinsic diode Di2 of transistor T2 therefore has its anode on the terminal 200 side, and its cathode on the terminal 202 side. For example, transistor T3 has its source S3 connected to terminal 200 and its drain D3 connected to the drain D2 of transistor T2. The source S3 of transistor T3 is connected to the body region of transistor T3. The intrinsic diode Di3 of transistor T3 therefore has its anode on the side of terminal 202, and its cathode on the side of terminal 200. Switch 2 is controlled by signals cmdl, cmd2 and cmd3 applied respectively to gate G1 of transistor T1, gate G2 of transistor T2 and gate G3 of transistor T3. For example, depending on the control signals cemdl, cmd2 and cmd3, the potential Vsw on terminal 202 of switch 2 is selectively derived from the potential Vbat or the potential Vdd. In other words, depending on the control signals emd1, cmd2 and cmd3, the potential Vsw is equal to the potential Vbat (neglecting the voltage drops in transistors T2 and T3) or at potential Vdd (neglecting the voltage drop in transistor T1). Compared to known power switches, switch 2 comprises only one PMOS transistor between its terminals 202 and 204, namely transistor T1, hence switch 2 is less bulky than known switches. Preferably, transistor T1 is half the size of each of transistors T2 and T3, so that the impedance seen at terminal 202 when transistors T2 and T3 are off and transistor T1 is on is the same as when transistors T2 and T3 are on and transistor T1 is off. For example, switch 2 makes it possible to supply circuits with the potential Vsw derived from the potential Vdd when the potential Vdd is greater than a threshold Vth, and with the potential Vsw derived from the potential Vbat when the potential Vdd is less than the threshold Vth, for example when the potential Vdd is zero. For example, source 5 delivers a potential Vdd greater than the threshold Vth if device 1 is connected to a main power supply and a potential Vdd less than the threshold Vth, or even zero, otherwise. For example, source 4 is a battery of device 1. Switch 2 then makes it possible to maintain a non-zero power supply potential Vsw when device 1 is disconnected from the main power supply 5 and the potential Vdd becomes zero, by coupling terminals 200 and 202 (power supply to battery 4), and, conversely, to save battery 4 when device 1 is coupled to the main power supply and the potential Vdd is greater than the threshold Vth, by coupling terminals 204 and 202 (power supply to main power supply 5). According to one embodiment, the device | comprises a circuit 6 (block “RST” in [Fig.1]) configured to provide a binary signal EN to a first binary state when the potential Vdd is lower than the threshold Vth and to a second binary state when the potential Vdd is lower than the threshold Vth. As an example, the circuit 6 comprises a terminal configured to provide the signal EN and a terminal configured to receive the potential Vdd. For example, when the potential Vdd increases and exceeds the threshold Vth, the signal EN switches from its first binary state to its second binary state. For example, circuit 6 is powered by the potential Vsw, and then includes a power supply terminal receiving the potential Vsw and a power supply terminal connected to ground GND. Preferably, the first binary state of the EN signal is a low state corresponding to the potential of the GND ground and the second binary state of the EN signal is a high state corresponding to the Vsw potential. Thus, when the Vsw potential is zero, the EN signal is by default in the low state, i.e. at the GND ground. Control circuit 3 is configured to control transistors T1, T2 and T3. Circuit 3 receives the potentials Vdd, Vsw and Vbat. According to one embodiment, the signal cmd1 is a binary signal whose high state corresponds to the potential Vsw, and whose low state corresponds to the ground potential GND, the signal cmd2 is a binary signal whose high state corresponds to the potential Vsw and whose low state corresponds to the ground potential GND, and the signal cmd3 is a binary signal whose high state corresponds to the potential Vbat and whose low state corresponds to the ground potential GND. According to one embodiment, the circuit 3 is configured to control the transistors T1, T2 and T3 at least on the basis of the signal EN. The first binary state, for example the low state, of the signal EN indicates to the circuit 3 that it must control the transistors T1, T2 and T3 so as to electrically couple the terminals 200 and 202 and to electrically isolate the terminals 204 and 202, and the second binary state, for example the high state, of the signal EN indicates to the circuit 3 that it must control the transistors T1, T2 and T3 so as to electrically couple the terminals 204 and 202 and to electrically isolate the terminals 200 and 202. In other words, the first binary state of the signal EN corresponds to a request to the circuit 3 to turn on the transistors T2 and T3 and turn off the transistor T1, and the second binary state of the signal EN corresponds to a request to the circuit 3 to turn off the transistors T2 and T3 and turn on the transistor T1, As an example, we consider the case where the potential Vdd is greater than the threshold Vth and the potential Vsw is non-zero. In this case, when the signal EN is in its second binary state, the circuit 3 applies, for example, the low state of the signal cmd! to the gate G1 of the transistor T1 which is then in the on state, the high state of the signal cmd2 to the gate G2 of the transistor T2 which is then in the off state, and the high state of the signal cemd3 to the gate of the transistor T3 which is then in the off state. As an example, we consider the case where the potential Vbat is non-zero, the potential Vsw is non-zero and the potential Vbat is lower than the threshold Vth. In this case, the signal EN is in its first binary state and the circuit 3 applies, for example, the high state of the signal cmd1 to the gate Gl of the transistor T1 which is then blocked, the low state of the signal cmd2 to the gate G2 of the transistor T2 which is then conducting, and the low state of the signal cemd3 to the G3 of the transistor T3 which is then conducting. As another example, when the potentials Vsw and Vbat are zero, the low state of the signal cmdl, when applied to the gate G1 of the transistor T1, does not allow the transistor T1 to be switched on. However, the application of a non-zero potential Vdd to terminal 204 causes a current to flow from terminal 204 to terminal 202, via the diode Di1, which allows the potential Vsw to increase. The signal cmd1l is maintained in its low state, and the increase in the potential Vsw causes the voltage between the gate G1 and the source SI, or gate-source voltage of the transistor T1, to become sufficient for the transistor T1 to switch to the on state and thus couple the terminals 204 and 202. Preferably, during this operating phase, circuit 3 applies the high state of signal emd2 to gate G2 of transistor T2, so that the gate-source voltage of transistor T2 remains zero and transistor T2 remains in the off state, which prevents current leaks from terminal 204 to terminal 200, via diode Dil or transistor T1 passing, transistor T2 and diode Di3. As another example, when the potentials Vsw and Vdd are zero, applying the low level of the signal cmd3 to the gate G3 of the transistor T3 allows, when the potential Vbat is sufficiently high, to turn on the transistor T3. On the other hand, the low state of the signal cmd2, when applied to the gate G2 of the transistor T2, does not allow the transistor T2 to be turned on. However, because the transistor T3 is on, a current flows from terminal 200 to terminal 202, via the transistor T3 on and the diode Di2, and the potential Vsw increases. Increasing the potential Vsw and maintaining the signal cmd2 in the low state causes the voltage between the gate G2 and the source S2, or gate-source voltage of the transistor T2, to become sufficient for the transistor T2 to switch to the on state. The two transistors T2 and T3 in the on state then couple terminals 204 and 202, and the potential Vsw is then substantially equal to the potential Vbat.Preferably, during this operating phase, circuit 3 applies the high state of the signal cmd] to the gate G1 of transistor T1, so that transistor T1 remains in the off state, which prevents current leaks from terminal 200 to terminal 204 via transistors T3, T2 and T1. [Fig.2] represents an example of an embodiment of a method for controlling the switch 2 of [Fig.1], for example implemented by the circuit 3. At a step 200 (block "EN?"), circuit 3 observes the binary state of the signal EN. In step 200, if the signal EN is in its second binary state (output Vdd of block 200), for example the high state, this means that circuit 3 must electrically couple terminals 204 and 202, and electrically isolate terminals 202 and 200. Step 200 is then followed by a step 202 (block "T1 ON T2, T3 OFF") In step 202, circuit 3 controls the switching on of transistor T1 by applying the low state of signal cmd1 to gate G1 of transistor T1, and a switching off of transistors T2 and T3 by applying the high state of signal cmd2 to gate G2 of transistor T2 and the high state of signal emd3 to gate G3 of transistor T3. For example, in step 202, if the potential Vsw is zero, as soon as the potential Vdd is greater than the threshold of the diode Dil, a current flows from terminal 204 to terminal 202, via the diode Dil as described in relation to [Fig. 1]. Thus, the potential Vsw increases until the transistor T1 is switched to the on state by the circuit 3. At the same time, preferably, the circuit 3 maintains the transistors T2 and T3 in the off state, for example, by maintaining the signal cmd2 in its high state (potential Vsw) and the signal cmd3 in its high state (potential Vbat). At step 200, if the signal EN is in its first binary state (Vbat output of block 200), for example the low state, this means that circuit 3 must electrically couple terminals 200 and 202, and electrically isolate terminals 204 and 202. Step 200 is then followed by a step 204 (block "Vbat > 0"). In step 204, circuit 3 checks whether the potential Vbat is zero, for example by comparing the potential Vbat to the ground GND. At step 204, if the potential Vbat is non-zero (output YŸ of block 204), and, more precisely, strictly positive, the process continues at step 206 (block "T1 OFF T2, T3 ON"). In step 206, circuit 3 controls the switching on of transistor T2 by applying the low state of signal cmd2 to gate G2 of transistor T2, the switching on of transistor T3 by applying the low state of signal emd3 to gate G3 of transistor T3 and a switching off of transistor T1 by applying the high state of signal cmd1l to gate G1 of transistor T1. For example, in step 206, if the potential Vsw is zero, as soon as the potential Vbat is high enough for the transistor T3 to switch to the on state, a current flows from terminal 200 to terminal 202, via the on transistor T3 and the diode Di2 as described by way of example in relation to [Fig. 1]. Thus, the potential Vsw increases until the transistor T2 is switched to the on state by the circuit 3. At the same time, preferably, the circuit 3 maintains the transistor T1 in the off state, for example, by maintaining the signal cmd! at its high state (potential Vdd). At step 204, if the potential Vbat is zero (output N of block 204), it is then preferable not to electrically couple terminals 200 and 202 together. The process then continues at step 208 (block "T1 ON T2, T3 OFF"). Step 208 is identical to step 202. Thus, in step 204, if the potential Vdd is non-zero, for example lower than the threshold Vth but non-zero, and the potential Vbat is zero, the implementation of step 208 makes it possible to maintain a non-zero potential Vsw. When circuit 3 implements step 204, circuit 3 is configured to condition the setting to the on state of transistors T2 and T3 and, preferably, the setting to the off state of transistor T1, on the fact that potential Vbat is non-zero. In other words, circuit 3 is configured to control the on state of transistors T2 and T3, for example following the reception of the first binary state of signal EN, only if, in addition, potential Vbat is non-zero. According to an alternative embodiment, steps 204 and 208 can be omitted, step 200 then being directly followed by step 208 when the signal EN is in its first binary state during step 200. In this alternative, the circuit 3 is not configured to condition the setting to the on state of the transistors T2 and T3 on the fact that the potential Vbat is non-zero. Preferably, although not shown in [Fig.2], each of steps 202, 206 and 208 is followed by step 200, so that the implementation of these steps is carried out continuously or repeatedly. According to one embodiment, the method further comprises a step 210 (block “Vdd > 0?”). In step 210, the circuit 3 checks whether the potential Vdd is zero, for example by comparing it to the ground GND. In step 210, if the potential Vdd is zero (output N of block 210), the method continues at step 212 (block "T3 ON"). Otherwise (branch Y of block 210) step 210 is implemented again. In step 212, circuit 3 forces transistor T3 to turn on, for example by applying the low state of the signal cmd3 to the gate G3 of transistor 3. Thus, if the potential Vbat is sufficient, transistor T3 is turned on. This allows, when the potentials Vsw and Vdd are zero but the potential Vbat is non-zero, to increase the potential Vsw by electrically coupling terminals 200 and 202 via the transistor T3 being on and the diode Di2. Although not shown in [Fig.2], preferably, step 212 is followed by step 210, such that step 210 is performed continuously or repeatedly. Preferably, the setting to the on state of the transistor T3 resulting from the implementation of step 212 prevails over the setting to the off state of the transistor T3 resulting from the implementation of step 208, or, in other words, has priority over the setting to the off state of the transistor T3 resulting from the implementation of step 208. In an alternative embodiment, steps 210 and 212 are omitted. In such an alternative, circuit 3 is not configured to force transistor T3 to be switched on when potential Vdd is zero. We have described above in relation to figures 1 and 2 the case where the maximum values of gate-source voltage that the transistors T1, T2 and T3 can withstand are greater than the maximum values of the potentials Vbat and Vdd. It would be desirable to be able to realize the switch 2 with transistors having maximum gate-source voltages of values lower than the maximum values of potentials Vbat and Vdd. For example, this makes it possible to realize an integrated circuit comprising the device 1, which is entirely implemented with MOS transistors having maximum gate-source voltages lower than the maximum values of potentials Vbat and Vdd. This results in a reduction of the surface area of the integrated circuit compared to the case where it would be implemented with larger MOS transistors, having maximum gate-source voltages greater than or equal to the maximum values of potentials Vbat and Vdd. [Fig.3] shows another embodiment of switch 2 of [Fig.1]. In [Fig.3], transistors T1, T2 and T3 are extended drain PMOS transistors ("drift PMOS" in English). The provision of extended drain transistors T1, T2, T3 allows each transistor T1, T2, T3 to withstand a maximum voltage between its source and its drain, or maximum drain-source voltage, and a maximum voltage between its gate and its drain, or maximum gate-drain voltage, greater than or equal to the maximum values of the potentials Vbat and Vdd. On the other hand, we consider here that transistors T1, T2 and T3 each support a maximum gate-source voltage lower than the maximum values of potentials Vbat and Vdd. Thus, according to one embodiment, the control circuit 3 (not shown in [Fig.3]) then comprises: - a circuit configured to provide a high reference potential VrefHB equal to À times the supply potential Vbat and a low reference potential VrefLB equal to B times the supply potential Vbat, with À and B positive numbers strictly less than 1, À being greater than B; and - a circuit configured to provide a high reference potential VrefHS equal to C times the supply potential Vsw and a low reference potential VrefLS equal to D times the supply potential Vsw, with C and D positive numbers strictly less than 1, C being greater than D. According to one embodiment, the numbers A, B, C and D are determined by the maximum gate-source voltage supported by each of the transistors T1, T2 and T3. Preferably, the numbers A, B, C and D are determined so that the difference between the potentials Vbat and VrefLB, the difference between the potentials VrefHB and GND, the difference between the potentials Vsw and VrefLS and the difference between the potentials VrefHS and GND are each less than the maximum gate-source voltage supported by each of the transistors T1, T2 and T3. In this way, the circuit 3 manipulates binary signals whose low and high states are equal to the potentials GND and VrefHB, GND and VrefHS, VrefLS and Vsw, and / or VrefLB and Vbat. These binary signals are compatible with the voltage withstand properties of the transistors T1, T2 and T3, and, for example, of the MOS transistors of the device 1 such as, in particular, the transistors implementing the circuit 3. According to one embodiment, the circuit 3 further comprises a circuit configured to provide a high reference potential VrefHM equal to E times the potential Vdd and a low reference potential VrefLM equal to F times the potential Vdd, with E and F positive numbers strictly less than 1. Furthermore, the number E is greater than the number F. Similar to the numbers A, B, C and D, the numbers E and F are de- terminated by the maximum potential difference that can be applied between the gate and the source of each of the transistors T1, T2 and T3. In other words, the numbers E and F are determined by the maximum gate-source voltage supported by each of the transistors T1, T2 and T3. Preferably, the numbers E and F are determined so that the difference between the potentials Vdd and VrefLM, and the difference between the potentials VrefHM and GND are each less than the maximum gate-source voltage supported by each of the transistors T1, T2 and T3. In this way, the circuit 3 can also manipulate binary signals whose low and high states are equal to the potentials GND and VrefHM, and / or to the potentials VrefLM and Vdd. These binary signals are compatible with the voltage withstand properties of the transistors T1, T2 and T3, and, for example, of the MOS transistors of the device 1 such as, in particular, the transistors implementing the circuit 3. Although not illustrated in [Fig. 3], in such an embodiment, preferably, the circuit 6 ([Fig. 1]) is preferably powered by the difference between the potentials VrefHS and GND. In other words, preferably, the low state of the signal EN is then the ground potential GND and the high state of the signal EN is then the potential VrefHS. Furthermore, preferably, in such an embodiment, the circuit 6 determines whether the potential Vdd is greater than the threshold Vth by comparing the potential VrefHM to a threshold Vth', the comparison of the potential VrefHM to the threshold Vth' being equivalent to the comparison of the potential Vdd to the threshold Vth. In the embodiment of [Fig.3], according to one embodiment, the high state of the signal cmdl corresponds to the potential Vsw, the low state of the signal cmd1 corresponds to the potential VrefLS, the high state of the signal cmd2 corresponds to the potential Vsw, the low state of the signal cmd2 corresponds to the potential VrefLS, the high state of the signal cmd3 corresponds to the potential Vbat and the low state of the signal cmd3 corresponds to the potential VrefLB. According to one embodiment, the operation of circuit 3, and preferably the operation of circuit 6, are identical to what has been described in relation to figures 1 and 2, with the only difference that the low levels of signals cmdl, cmd2 and cmd3 no longer correspond to potential GND, but instead correspond respectively to potential VrefLS, potential VrefLS and potential VrefLB. The implementation of circuit 3 in the case described in relation to [Fig.3] is within the reach of the person skilled in the art from the functional and structural indications given above. In particular, the person skilled in the art can implement the circuit 3 by means of the circuits configured to generate the potentials VrefHB, VrefLB, VrefHS and VrefLS, and, for example, the circuit configured to generate the potentials VrefHM and VrefLM. These circuits are commonly called reference voltage generators. Examples of reference voltage generators are described in the paper by Kumar et al. entitled "Power Sequence free 400Mbps 90uW 6000um° 1.8V-3.3V Stress Tolerant I / O Buffer in 28nm CMOS" presented in 2013 at the ESSCIRC conference. The person skilled in the art will be able to find other examples of such circuits in the literature. Furthermore, to implement circuit 3, and preferably circuit 6, the person skilled in the art may use level shifter circuits (or splitters) configured to receive a binary signal having a low level corresponding to a first potential and a high level corresponding to a second potential, and to provide a binary signal having a low level corresponding to a third potential different from the first potential and a high level corresponding to a fourth potential, for example, different from the second potential. For example, circuit 3 may comprise circuits configured to receive a binary signal between the potentials (or levels) VrefHS and GND, VrefHB and GND, and VrefHS and GND, and to provide a binary signal between the potentials (or levels) respectively VrefHB and GND, Vbat and VrefLB, and Vsw and VrefLS.Examples of such circuits are also described in the aforementioned article, although the person skilled in the art will be able to find other examples of such circuits in the literature. [Fig.4] represents, in block form and in more detail, an embodiment of the control circuit 3 of the switch 2 of [Fig.3]. For example, the signal EN is in its first binary state when the potential Vdd is lower than the threshold Vth, and in its second binary state when the potential Vdd is higher than the threshold Vth. Preferably, the first binary state of the signal EN corresponds to the potential GND and the second binary state of the signal EN corresponds to the potential VrefHS. In this embodiment, the circuit 3 comprises a circuit 400, of the type described previously, configured to provide the potential VrefHB and the potential VrefLB. By way of example, the circuit 400 is configured to provide the potentials VrefHB and VrefLB from the potential Vbat, preferably from the difference between the potentials Vbat and GND. By way of example, the circuit 400 receives the potentials Vbat and GND, for example on power supply terminals of the circuit 400. In this embodiment, the circuit 3 further comprises a circuit 402, of the type described previously, configured to provide the potential VrefHS and the potential Vre[LS. By way of example, the circuit 402 is configured to provide the potentials VrefHS and VrefLS from the potential Vsw, preferably from the difference between the potentials Vsw and GND. By way of example, the circuit 402 receives the potentials Vsw and GND, for example on power supply terminals of the circuit 402. According to one embodiment, the control circuit 3 comprises circuits 404, 406 and 408, of the type described previously. The circuit 404 is configured to receive a binary signal cmd3' between the ground GND and the potential VrefHB and to supply, to the gate G3 of the transistor T3 (not shown in [Fig.4]), the binary signal cmd3. The signal cmd3 is determined by the signal cmd3' and is between the potential Vbat and the potential VrefLB. In other words, the signal cmd3 corresponds to the signal emd3' with the difference that the signal cmd3 is between the potentials Vbat and VrefLB while the signal cemd3' is between the potentials VrefHB and GND. Preferably, the signal emd3 is in the low state, respectively high, when the signal cmd3' is in the low state, respectively high. For example, the circuit 404 receives the difference between the potentials Vbat and VrefLB and the difference between the potentials VrefHB and GND, for example on four respective power supply terminals. The circuit 406 is configured to receive a binary signal cmd2" between the ground GND and the potential VrefHS and to supply, to the gate G2 of the transistor T2 (not shown in [Fig.4]), the binary signal cmd2. The signal cmd2 is determined by the signal cmd2' and is between the potential Vsw and the potential VrefLS. In other words, the signal cmd2 corresponds to the signal emd2' with the difference that the signal cmd2 is between the potentials Vsw and VrefLS while the signal emd2' is between the potentials VrefHS and GND. Preferably, the signal emd2 is in the low state, respectively high, when the signal cmd2" is in the low state, respectively high. For example, the circuit 406 receives the difference between the potentials Vsw and VrefLS and the difference between the potentials VrefHS and GND, for example on four respective power supply terminals. The circuit 408 is configured to receive a binary signal cemdl' between the ground GND and the potential VrefHS and to supply, to the gate G1 of the transistor T1 (not shown in [Fig.4]), the binary signal emdl. The signal cmd1 is determined by the signal cmdl' and is between the potential Vsw and the potential VrefLS. In other words, the signal cmd1 corresponds to the signal emdl' with the difference that the signal cmdl is between the potentials Vsw and VrefLS while the signal cmdl' is between the potentials VrefHS and GND. Preferably, the signal cmd1 is in the low state, respectively high, when the signal cmd1' is in the low state, respectively high. For example, the circuit 408 receives the difference between the potentials Vsw and VrefLS and the difference between the potentials VrefHS and GND, for example on four respective power supply terminals. In the same way as the signals emd1l, cdm2 and cmd3, the signals emdl', emd2" and cmd3' are at least partly determined by the signal EN, i.e. by the binary state or potential level of the signal EN. More particularly, according to one embodiment, the control circuit 3 comprises a circuit 410 and a circuit 412. The circuit 410 is configured to receive the signal EN, and to provide the signals emd2' and cmdl'. The circuit 410 is further configured to provide a binary signal emd3" determining, at least in part, the state of the signal cmd3'. The signal emd3" is included, like the signals emdl', emd2' and EN, between the potentials VrefHS and GND. The circuit 410 is powered by the difference between the potentials VrefHS and GND, and receives, for example, the potentials VrefHS and GND on two respective supply terminals. The power supply of the circuit 410 by the potential VrefHS results from the fact that the signals EN, cmdl' and cmd2' are between the potentials VrefHS and GND, and allows, for example, that the maximum voltage that the MOS transistors of the circuit 410 can withstand between two of their terminals (gate, source, drain) is lower than the maximum values of the potentials Vbat and Vsw. The circuit 412 is configured to receive the signal cmd3", and to provide the signal cmd3'. The circuit 412 is powered by the difference between the potentials VrefHB and GND, and receives, for example, the potentials VrefHB and GND on two respective supply terminals. This allows, for example, that the maximum voltage that the MOS transistors of the circuit 412 can withstand between two of their terminals (gate, source, drain) is lower than the maximum values of the potentials Vbat and Vsw. According to one embodiment, to determine the signal cemd3' at least in part from the signal emd3", the circuit 412 comprises a circuit 414. The circuit 414 is configured to receive the signal cmd3" between the potentials VrefHS and GND and to provide a binary signal cmd3"”" between the potentials VrefHB and GND. The signal cmd3”" is determined by the signal cmd3". In other words, the signal cmd3"“ corresponds to the signal cmd3" with the difference that the signal cmd3” is between the potentials VrefHB and GND while the signal cmd3" is between the potentials VrefHS and GND. Preferably, the signal cmd3”" is in the low state, respectively high, when the signal cmd3" is in the low state, respectively high. For example, the circuit 414 receives the difference between the potentials VrefHB and GND, for example on two respective power supply terminals. In the embodiment illustrated by [Fig.4], circuit 3 is configured to condition a switching on of transistors T2 and T3, when this is required by signal EN, on the fact that potential Vbat is non-zero. Circuit 3 then comprises a circuit 418. Circuit 418 is configured to provide a binary signal cmd4 of which a first binary state, for example the low state, indicates that the potential Vbat is strictly positive, therefore non-zero, and of which a second binary state, for example the high state, indicates that the potential Vbat is zero. For this, circuit 418 preferably receives the signal VrefHB. The cmd4 signal is between the VrefHS and GND potentials. In other words, the low state of the cmd4 signal corresponds to the GND potential and the high state of the cmd4 signal corresponds to the potential VrefHS. The circuit 418 is powered by the difference between the potentials VrefHS and GND and receives, for example, the potentials VrefHS and GND on respective supply terminals. For example, the circuit 418 comprises a comparator circuit, preferably powered by the difference between the potentials VrefHS and GND, configured to compare the potential VrefHB to the potential GND. Indeed, because the potential VrefHB is equal to × the potential Vbat, the potential VrefHB is strictly positive, respectively zero, when the potential Vbat is strictly positive, respectively zero. The signal emd4 is received by the circuit 410, or, in other words, provided by the circuit 418 to the circuit 410. In such an embodiment, the circuit 410 is configured to provide the signals emdl', emd2' and cmd3" from the signals EN and cmd4. For example, when the circuit receives the first binary state of the signal EN, indicating a request to turn on transistors T2 and T3, and the signal cmd4 indicates that the potential Vbat is strictly positive, the circuit 410 provides the signals emd3", cemdl' and cmd2' so as to command a turning on of transistors T2 and T3 and a turning off of transistor T1. On the other hand, if the circuit 410 receives the second binary state of the signal EN and / or the signal cmd4 indicates that the potential Vbat is zero, the circuit 410 provides the signals cmd3", emdl' and emd2” so as to command a turning off of transistors T2 and T3 and a turning on of transistor T1. For example, the circuit 410 is implemented by combinational logic gates made by MOS transistors, the logic gates preferably being powered by the difference between the potentials VrefHS and GND. The logic gates are configured to provide the signals cmd3", cmdl' and emd2' from the signals EN and cmd4. In an alternative embodiment not illustrated, the circuit 3 is not configured to condition a switching on of the transistors T2 and T3, when this is required by the signal EN, on the fact that the potential Vbat is non-zero. In this variant, circuit 418 may be omitted. For example, circuit 410, for example the combinational logic gates that implement it, is then configured to determine the signals cmd3", cmd2' and cmdl' only from the signal EN. In the embodiment illustrated by [Fig.4], circuit 3 is further configured to force transistor T3 to be switched on when potential Vdd is zero. Circuit 3 then includes a circuit 420 and a circuit 422. The circuit 420, of the type previously described in relation to [Fig. 3], is configured to provide the potential VrefHM and the potential VrefLM. As an example, the circuit 420 is configured to provide the potentials VrefHM and VrefLM from the potential Vdd, preferably from the difference between the potentials Vdd and GND. For example, the circuit 420 receives the potentials Vdd and GND, for example on power supply terminals of the circuit 420. The circuit 422 is configured to provide a binary signal cmd5 of which a first binary state, for example the high state, indicates that the potential Vdd is strictly positive, therefore non-zero, and of which a second binary state, for example the low state, indicates that the potential Vdd is zero. For this, the circuit 418 preferably receives the signal VrefHM. The signal emd5 is between the potentials VrefHB and GND. In other words, the low state of the signal cmd5 corresponds to the potential GND and the high state of the signal emd5 corresponds to the potential VrefHB. The circuit 422 is powered by the difference between the potentials VrefHB and GND and receives, for example, the potentials VrefHB and GND on respective supply terminals. For example, the circuit 422 comprises a comparator circuit, preferably powered by the difference between the potentials VrefHB and GND, configured to compare the potential VrefHM to the potential GND. Indeed, because the potential VrefHM is equal to E times the potential Vdd, the potential VrefHM is strictly positive, respectively zero, when the potential Vdd is strictly positive, respectively zero. The signal emd5 is received by the circuit 412, or, in other words, provided by the circuit 422 to the circuit 412. In such an embodiment, the circuit 412 is configured to provide the signals cmd3' from the signals emd3" and cmd5, or, in other words, from the signals cmd3" and cmd5. For example, when the signals cmd5 and cmd3" received by the circuit 412 respectively indicate that the potential Vdd is strictly positive and that the transistor T3 must be put in the off state, the circuit 412 provides the signal cmd3' so as to command a setting in the off state of the transistor T3. On the other hand, if the signal cmd5 indicates that the potential Vdd is zero and / or if the signal emd3" indicates that the transistor T3 must be put in the on state, the circuit 412 provides the signal cmd3' so as to command a setting in the on state of the transistor T3. For example, circuit 412, with the exception of its circuit 414, is implemented by combinational logic gates made by MOS transistors, the logic gates being preferably powered by the difference between the potentials VrefHB and GND. The power supply of circuit 412 by the potential VrefHB results from the fact that the two signals cmd3" and cmd5 are between the potentials VrefHB and GND. The logic gates of circuit 412 are configured to provide the signal cmd3' from the signals ecmd5 and cmd3"". In an alternative embodiment not illustrated, circuit 3 is not configured to force transistor T3 to be switched on when potential Vdd is zero. In this variant, circuits 420 and 422 may be omitted from circuit 3, although circuit 420 may still be provided in circuit 6 ([Fig. 1]). For example, circuit 412, for example the combinational logic gates that implement it, is then configured to determine signal emd3' only from signal emd3", hence from signal cmd3". According to one embodiment, the circuit 3 implements the embodiment or one of the variant embodiments of the method described in relation to [Fig.2]. [Fig.5] illustrates an embodiment of a method of providing the control signal EN to circuit 3 of [Fig.1] or 4. As an example, this method is implemented by circuit 6 ([Fig.1]). At step 500 (block "Vdd>Vth?"), the potential Vdd is compared to the threshold Vth. According to an embodiment where the transistors T1, T2, and T3 are configured to support a maximum source-gate voltage greater than or equal to the potentials Vdd and Vbat, the circuit 6 ([Fig.1]) comprises a comparator circuit configured to compare the potential Vdd to the threshold Vth. The comparator circuit is then powered by the difference between the potentials Vsw and GND, so that the signal EN is between the potentials Vsw and GND. According to an embodiment where the transistors T1, T2, and T3 are configured to withstand a maximum source-gate voltage lower than the potentials Vdd and Vbat, the circuit 6 ([Fig.1]) comprises a comparator circuit configured to compare the potential VrefHM to a threshold Vth' determined by the threshold Vth, so that the comparison of the potential VrefHM to the threshold Vth' amounts to comparing the potential Vdd to the threshold Vth. The comparator circuit is then powered by the difference between the potentials VrefHS and GND, so that the signal EN is between the potentials VrefHS and GND. If the potential Vdd is greater than the threshold Vth (output Y of block 500), the method continues at a step 502 (block "Vdd"). At step 502, the signal EN is switched to its second binary state, or, in other words, the circuit 3 receives a request to turn on the transistor T1 and to turn off the transistors T2 and T3. Step 502 is followed by step 500. According to an embodiment where the transistors T1, T2, and T3 are configured to support a maximum source-gate voltage greater than or equal to the potentials Vdd and Vbat, the second binary state of the signal EN corresponds to the potential Vsw. According to an embodiment where the transistors T1, T2, and T3 are configured to support a maximum source-gate voltage lower than the potentials Vdd and Vbat, the second binary state of the signal EN corresponds to the potential VrefHS. If the potential Vdd is lower than the threshold Vth (output N of block 500), the method continues at a step 504 (block "Vbat"). At step 504, preferably immediately after the potential Vdd becomes lower than the threshold Vth, the signal EN is switched to its first binary state, or, in other words, the circuit 3 receives a request to set the transistor T1 to the blocked state and to set the transistors T2 and T3 to the conducting state. Step 504 is followed by step 500. According to one embodiment, the first binary state of the signal EN corresponds to the potential GND. Although this has not been detailed above, preferably, when the potential Vsw is not sufficient for the circuit 6 to implement the comparison of the potential Vdd to the threshold Vth, that is to say when the potential Vsw is not sufficient to power the circuit 6, for example at the start of operation of the device 1 when the potential Vsw is still zero, the signal EN is by default maintained in the low state, that is to say at the potential GND. In other words, when the potential Vsw is not sufficient to correctly power the circuit 6, the signal EN is by default in the low state indicating to the circuit 3 a request to put the transistor T1 in the blocked state and to put the transistors T2 and T3 in the conducting state. According to one embodiment, the transistors T1, T2 and T3 and the transistors of the circuit 3 and, preferably, of the circuit 6, are MOS transistors having a gate oxide whose thickness is substantially equal, for example equal, to 3.2 nm, the channel length of these transistors being for example substantially equal, preferably equal, to 28 nm. By way of example, these transistors are configured to support a maximum drain-source voltage, a maximum source-gate voltage and a maximum drain-gate voltage substantially equal to 1.8 V when they are not extended drain, and to support a maximum drain-source voltage and a maximum drain-gate voltage higher than 1.8 V when they are extended drain although the maximum gate-source voltage that they support remains substantially equal to 1.8 V. Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will be apparent to those skilled in the art. In particular, although a circuit 420 configured to provide not only the VrefHM potential, but also the VrefLM potential has been described, in alternative embodiments the circuit 420 is configured to provide the VrefHM potential without providing the VrefLM potential. Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, the implementation of the circuits described, in particular circuits 410 and 412, is within the reach of the person skilled in the art from the functional and structural indications given previously.

Claims

Demands

1. Device (1) comprising: - a first terminal (200) intended to be connected to a first voltage source (4) providing a first supply potential (Vbat) referenced to ground (GND); - a second terminal (202) configured to provide a second supply potential (Vsw) referenced to ground (GND); - a third terminal (204) intended to be connected to a second voltage source (5) providing a third supply potential (Vdd) referenced to ground (GND); - a first PMOS transistor (T1) having a source connected to the second terminal (202) and a drain connected to the third terminal (204); - a second PMOS transistor (T2) having a source connected to the second terminal (202); and - a third PMOS transistor (T3) having a source connected to the first terminal (200) and a drain connected to the drain of the second PMOS transistor (T2).

2. Device according to claim 1 further comprising a circuit control (3) of the first, second and third transistors (T1, T2, T3), the control circuit being configured to receive the first, second and third supply potentials (Vsw, Vdd, Vbat).

3. Device according to claim 2, wherein the control circuit (3) is configured to receive a first binary signal (EN), and to control the first, second and third transistors (T1, T2, T3) at least on the basis of the first signal (EN), a first binary state of the first signal (EN) corresponding to a request to the circuit of command (3) to turn on the second and third transistors (T2, T3) and blocked the first transistor (T1), and a second binary state of the first signal (EN) corresponding to a request to the circuit of command (3) to block the second and third transistors (T2, T3) and passing the first transistor (T1).

4. Device according to claim 3, wherein the control circuit (3) is further configured to condition a passing state of second and third transistors (T2, T3) due to the fact that the first potential (Vbat) is non-zero.

5. Device according to claim 2 or 3, wherein the circuit of command (3) is further configured to compare the third supply potential (Vdd) to ground (GND), and to force a the third transistor (T3) is switched on if the third potential supply voltage (Vdd) is zero.

6. Device according to any one of claims 2 to 5, in which The control circuit includes: a first circuit (400) configured to provide a first potential of high reference (VrefHB) equals A times the first potential power supply (Vbat) and a first low reference potential (VrefLB) equal to B times the first supply potential (Vbat), with A and B of positive numbers strictly less than 1, where A is greater than B; and a second circuit (402) configured to provide a second potential high reference (VrefHS) equal to C times the second potential power supply (Vsw) and a second low reference potential (VrefLS) equals D times the second supply potential (Vsw), with C and D are positive numbers strictly less than 1, with C being greater than 1. to D.

7. Device according to claim 6, wherein a maximum difference potentials that can be applied between the grid and the source of each the first, second and third transistors (T1, T2, T3) determines the numbers A, B, Cet D.

8. Device according to claim 6 or 7, wherein the circuit of Order (3) includes: a third circuit (404) configured to receive a second signal binary (emd3") included between ground (GND) and the first potential of high reference (VrefHB) and to provide, to the grid (G3) of the third transistor (T3), a third binary signal (cmd3) determined by the second signal (Cmd3") and included between the first potential of low reference (VrefLB) and the first supply potential (Vbat); a fourth circuit (406) configured to receive a fourth signal binary (emd2") included between ground (GND) and the second potential high reference (VrefHS) and to provide, to the grid (G2) of the second transistor (T2), a fifth binary signal (cmd2) determined by the fourth signal (emd2”) and included between the second potential of low reference (VrefLS) and the second supply potential (Vsw); And a fifth circuit (408) configured to receive a sixth signal binary (emd1l") included between ground (GND) and the second potential high reference (VrefHS) and to provide, to the grid (G1) of the first transistor (T1), a seventh binary signal (cmd!) determined by the sixth signal (emdl”) and included between the second potential of reference low (VrefLS) and the second supply potential (Vsw).

9. Device according to any one of claims 8, wherein the control circuit (3) includes: a sixth circuit (410) configured to be powered between the second high reference potential (VrefHS) and ground (GND), to receive the first binary signal (EN), to provide the fourth (cmd2”) and sixth (cdml') signals; a seventh circuit (12) configured to be powered between the first high reference potential (VrefHB) and ground (GND), to receive a binary signal (emd3”) from the sixth circuit (10) included between the second high reference potential (VrefHS) and ground (GND), and to provide the second binary signal (cmd3") at least from the binary signal (cmd3”) received from the sixth circuit (410).

10. Device according to claim 9, wherein the sixth circuit (410) is configured to determine the state of the fourth (cmd2”) and sixth (emdl') signals and binary signal (emd3”) than the sixth circuit (410) provides to the seventh circuit (412) at least on the basis of the first signal (IN).

11. Device according to claim 9 or 10, wherein: the control circuit (3) further includes an eighth circuit (418) configured to receive the first high reference potential (VrefHB), to detect when the first high reference potential (VrefHB) is strictly positive, and to provide the sixth circuit (410) with a eighth binary signal (cmd4) included between the second potential of high reference (VrefHS) and ground (GND) and having a binary state determined by said detection, and the sixth circuit (410) is configured to determine the state of the fourth (cmd2") and sixth (cmd1l") signals and binary signal (cmd3”) that the sixth circuit (410) supplies to the seventh circuit (412) at less on the basis of the first signal (EN) and the eighth signal (Cmd4).

12. Device according to any one of claims 9 to 11, wherein the seventh circuit (412) includes a ninth circuit (414) configured to receive the binary signal (cmd3”) received from the sixth circuit (410) and provide a ninth binary signal (cmd3"") determined by the signal binary (cmd3”) received and understood between ground (GND) and the first high reference potential (VrefHB), the seventh circuit (412) being configured to determine the state of the second binary signal (cmd3') at less on the basis of the ninth binary signal (emd3"").

13. Device according to any one of claims 9 to 12, in which the control circuit (3) includes a tenth circuit (420) configured to provide a third high reference potential (VrefHM) equal to E times the third supply potential (Vdd), with E a number positive strictly less than 1 determined by the maximum difference of potentials that can be applied between the grid and the source of each the first, second and third transistors; the control circuit (3) includes an eleventh circuit (422) configured to receive the third high reference potential (VrefHM), to detect when the third high reference potential (VrefHM) is strictly positive, and to supply the seventh circuit (412) a tenth binary signal (cmd5) between the first high reference potential (VrefHB) and ground (GND) and having a state binary determined by said detection, and the seventh circuit (412) is configured to determine the state of the second binary signal (emd3') at least the base of the binary signal (cmd3”) received from the sixth circuit (410) and the tenth signal (cmd5).

14. | Device according to any one of claims 1 to 13, wherein the first, second and third PMOS transistors (T1, T2, T3) are at extended drain.

15. Device according to any one of claims 1 to 14, comprising in addition the first and second sources of tension.