Integrated circuit with stacked chips and capacitive connection

Abstract

Stacked Chip Integrated Circuit with Capacitive Connection. Integrated circuit (1) comprising a first chip (10) and a second chip (20) stacked one on top of the other, the first chip being electrically connected to the second chip by a coupling capacitor (C) located in an inter-chip junction zone (30) between the first and second chips, the coupling capacitor comprising a first conductive plate (100) in electrical contact with the first chip, and a second conductive plate (200) in electrical contact with the second chip, at least a portion of the first plate being formed by one or more electrically conductive micro-poles (110) extending from the first chip towards the second chip. Figure to be published with the abbreviation: Figure 3

Description

Title of the invention: Integrated circuit with stacked chips and capacitive connection Technical field

[0001] Generally speaking, the technical field is that of microelectronics, in particular that of integrated circuits produced in the form of stacks of several chips assembled together and electrically connected together. TECHNOLOGICAL BACKGROUND

[0002] In the field of microelectronics, it is common to assemble together several chips having different functions, in particular chips obtained by different manufacturing techniques. The integrated circuit thus obtained then has the structure of a three-dimensional stack.

[0003] Such a circuit is shown schematically in [Fig. 1]. This circuit 5 comprises a first chip 10 and a second chip 20, assembled one on top of the other. The first chip is electrically connected to the second chip by means of micropillars 4 which each extend from the first chip to the second chip, through a junction layer 3 (for example made of oxide, or of polymer), which links the chips together. Such a micropillar generally comprises two half-micropillars, that is to say two microposts (often called "post", in English, one made on the first chip, and the other on the second chip) connected to each other by a solder microball (formed for example from a tin-based material). Such a micropillar has for example a total height of about ten microns.Such an electrical connection is essentially equivalent to a resistor R in series with an inductance L (self-inductance of the pillar; pillar which forms a sort of portion of conductive electrical wire). At high frequencies, the total impedance associated with this connection becomes significant because of this inductive component (as illustrated in [Fig.l]), which can hinder the transmission of signals from one chip to another by causing unwanted reflections when passing from one chip to another and losses caused by this high impedance. SUMMARY

[0004] In this context, an integrated circuit is proposed comprising a first chip and a second chip assembled on top of each other, the first chip being electrically connected to the second chip by a coupling capacitor which is located in a junction zone between chips, between the first chip and the second chip, and which allows a high-frequency electrical connection (frequency greater than 10, or even greater than 100 or 300 GHz) between these two chips.

[0005] Such a capacitor, of capacitance C, has an impedance which varies as 1( / jC2ji / ), and which therefore decreases when the frequency f increases, becoming very low at high frequency. It is therefore well suited to making a connection for the purpose of transmitting a high-frequency electrical signal from one to the other. In an integrated circuit, however, space requirements are generally critical, and one might therefore, at first sight, be dissuaded from using such a capacitor, which is by nature quite bulky, to make this connection. But precisely, for very high frequencies, for example of the order of a hundred gigahertz or more, even a capacitor of low electrical capacitance (for example of the order of fifty femtofarads), which is not very bulky, makes it possible to obtain a low connection impedance, for example less than ten Ohms.In other words, in this frequency range, this type of coupling capacitor connection becomes interesting in terms of size and integration.

[0006] Arranging this capacitor in the junction zone between chips also makes it possible to advantageously exploit the space available in this interstitial zone, to carry out a more elaborate function than a DC connection or a mechanical link between chips.

[0007] The coupling capacitor in question may comprise: • a first conductive armature, in electrical contact with the first chip, and • a second conductive armature in electrical contact with the second chip, • at least part of the first armature being located opposite the second armature, the first and second armatures being electrically insulated from each other, • at least part of the first armature being formed by one or more electrically conductive microposts, each of which extends from the first chip, towards the second chip.

[0008] By "micropost" is meant an element, for example of cylindrical shape, projecting relative to the chip in question, extending towards the other chip, but not completely to the other chip. The dimensions (diameter, height) of such a micropost are typically greater than 1 micron, and less than 100 microns, for example between 10 and 50 microns.

[0009] By "micropillar", or, equivalently, by "complete micropillar" is meant an element which extends from one of the two chips to the other chip, by directly connecting these two chips together. Such a micropillar is for example formed of two microposts, one produced on the first chip, and the other on the second chip, connected to each other by a solder microball.

[0010] The microposts and micropillars in question are electrically conductive. They are typically formed from one or more metallic materials. Each micropost may be a single piece, formed from the same metallic material (for example copper or a copper-based alloy), or comprise several portions (several layers) formed from different metallic materials.

[0011] Furthermore, by "armature" is meant an electrically conductive structure, typically metal-based, the shape of which may be simple (for example a plate shape) or more complex. The different elements of the armature are in electrical contact with each other. In other words, by "armature" is meant one of the two electrodes of the coupling capacitor.

[0012] Producing one of the capacitor armatures from one or more microposts is particularly interesting. Indeed, the production of such microposts (which serve as a basis for the micropillars mentioned in the section relating to the technological background) is well mastered technologically, in particular in such a junction zone between chips. This also makes it possible to bring certain portions of the first armature closer to the second armature, to obtain a high capacitance per unit area despite the distance which separates the two chips in the junction zone between chips. Indeed, this distance is typically greater than 5 microns, for an assembly between chips by micropillars (due to the dimensions of the microposts themselves, and the solder microball which ensures the junction between them).It should also be noted that, in general, in the integrated circuit in question, DC connections between the two chips (classic connection, by electrical conduction) are made in addition to the high-frequency capacitive connection mentioned above, these DC connections being made by means of one or more complete micropillars. The gap between chips is then quite large (several microns), and it is therefore particularly interesting to bring the two armatures closer to each other, at least in places, to increase the capacitance of the capacitor (which is cleverly obtained by the use of one or more microposts, electrically connected to the first chip, but isolated from the second armature of the capacitor).

[0013] In the present application, the term “chip” is understood to mean a generally planar structure (whose overall shape is that of a small plate), based on one or more semiconductor materials (as well as other materials, in particular metallic materials and / or electrically insulating oxides), and capable of integrating different components, active or passive (transistor, diode, resistor, radiating or guiding structure). The chip in question may be formed by a complete (and functionalized) wafer, or by only a portion of such a wafer (i.e. by a Die).

[0014] The first chip and the second chip are assembled on top of each other in the sense that they are bonded (mechanically bonded) to each other, with the second chip located just above the first chip, parallel to it, almost against the first chip. In other words, the first chip has a first surface (which delimits the first chip), the second chip has a second surface (which delimits the first chip), and the two chips are assembled in such a way that the first surface extends opposite the second surface, parallel and at a reduced distance from it (for example with a gap of less than 30 microns). The two chips are thus assembled to each other at these first and second surfaces.

[0015] The junction area mentioned above, which is an assembly area between chips and which constitutes an interstitial zone between chips, is delimited by the first and second surfaces in question.

[0016] In practice, the mechanical bond between chips is obtained by adhering certain elements of the first chip, which extend into the assembly area in question (for example microposts), with elements of the second chip (also microposts, for example). An optional filling material, for example a polymer (or an oxide, typically a silicon oxide), can fill the unoccupied part of the assembly area, to obtain a more mechanically robust assembly, by forming a bonding layer between chips.

[0017] The assembly technology used here is typically a micropillar type technology, sometimes called “Copper Pillar bonding” or “Copper Pillar Bump” in English.

[0018] In addition to the characteristics presented above, the device presented above may have one or more of the following optional characteristics, considered individually or in all technically conceivable combinations: • each micropost extends perpendicular to the first chip, from the first chip to an end face of the micropost; • the second reinforcement comprises, for each micro-post, a face or a portion of a flat face located opposite and at a reduced distance from the end face of this micro-post; • at least part of the second armature is formed by one or more additional electrically conductive microposts, each of which extends in the direction of the first chip, from the second chip to an end face of the additional micropost; • each micro-post, as well as each additional micro-post, is delimited laterally by a lateral surface, and at least some of the additional micro-posts are offset laterally relative to said micro-posts, their respective lateral surfaces each being located opposite the lateral surface of one of said micro-posts; this arrangement contribute to increasing the capacitance of the capacitor; it also allows for fairly large tolerances in terms of lateral alignment between chips; at least some of said additional microposts are interposed between microposts of the first frame; This makes it possible to increase the surface density of microposts, and the capacitance of the capacitor; at least some of the additional microposts each extend opposite one of said microposts, the end face of the additional micropost in question being located opposite and at a reduced distance from the end face of the corresponding micropost, being electrically insulated from the end face of this micropost; the second frame comprises a flat plate which extends opposite said micro-post(s); the second frame is without micro-post; this arrangement facilitates manufacturing; said micro-posts are arranged periodically to form a regular network; at least part of the first reinforcement is separated from the second reinforcement by a distance of less than 2 microns, or even less than 0.5 microns; the coupling capacitor has an average electrical capacitance per unit area greater than or equal to 5 picofarads per square millimeter; the coupling capacitor has an electrical capacity greater than or equal to 50 femtofarads; the first chip is formed at least in part, or even mainly, from a first type of semiconductor material while the second chip is formed at least in part, or even mainly from a second type of semiconductor material different from the first type of semiconductor material; the first type of material is for example silicon; the second type of material is for example a III-V type semiconductor; in the field of microelectronics, the type of semiconductor material and the manufacturing technologies used can be quite different depending on the type of function to be achieved; thus assembling two chips made from different types of semiconductor materials therefore makes it possible to integrate quite different functions into this same circuit; the first armature of the coupling capacitor is electrically connected, for example by an electrical conductor, to a first electronic component of the transistor, diode, amplifier, antenna, waveguide or filter type, while its second armature is electrically connected, for example by an electrical conductor, to a second electronic component such as a transistor, diode, amplifier, antenna, waveguide or filter; • the first electronic component is configured to generate, emit, transmit or filter an electrical signal with a frequency greater than or equal to 10 GHz, or even greater than 100 or even 300 GHz, or even more (the spectrum of the signal in question may, for example, extend up to 325 GHz); • the first electronic component and / or the second electronic component is an active component (electrically powered).

[0019] The present technology and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0020] The figures are presented for information purposes only and are not limiting.

[0021] [Fig.l] [Fig.l] schematically represents a prior art stacked chip integrated circuit.

[0022] [Fig.2] [Fig.2] schematically represents an integrated circuit according to a first embodiment, comprising two chips assembled one on top of the other and electrically connected to each other by a coupling capacitor.

[0023] [Fig.3] [Fig.3] schematically represents the integrated circuit of [Fig.2], seen from the side.

[0024] [Fig.4] [Fig.4] schematically represents a set of microposts of the coupling capacitor in question, seen from above.

[0025] [Fig.5] [Fig.5] schematically represents the coupling capacitor, in perspective.

[0026] [Fig.6] [Fig.6] represents the integrated circuit of figures 2 and 3, in the form of an equivalent electrical diagram.

[0027] [Fig.7] [Fig.7] represents, in the form of an equivalent electrical diagram, an integrated circuit according to a second embodiment, also comprising two chips assembled one on top of the other and connected by a coupling capacitor.

[0028] [Fig.8] [Fig.8] schematically represents an integrated circuit according to a third embodiment, also comprising two chips assembled one on top of the other and connected by a micro-post coupling capacitor.

[0029] [Fig.9] [Fig.9] schematically represents an integrated circuit according to a fourth embodiment, also comprising two chips assembled one on top of the other and connected by a micro-post coupling capacitor. DETAILED DESCRIPTION

[0030] An example of an integrated circuit 1 with stacked chips, connected by the particular type of capacitive connection presented above, is shown schematically in [Fig.2]. In this example, the circuit is intended to emit a very high frequency signal, in this case at a frequency f greater than 100 GHz, and even greater than 300 GHz.

[0031] It comprises a first chip 10, here based on silicon, and a second chip 20, here based on Gallium Arsenide GaAs (more generally, based on a III-V type semiconductor, i.e. comprising an element from column V of the periodic table of elements, for example nitrogen N or phosphorus P, associated with one or more elements from column III of the periodic table of elements, for example gallium Ga, aluminum Al and / or indium In). The first chip 10, based on silicon, constitutes a support well suited to producing one or more components allowing a frequency increase of the signals, and making it possible to generate a very high frequency signal.Here, for example, the first chip 10 comprises a preamplifier 11 (“pre-power amplifier PPA”, in English), which delivers a signal (for example in the form of an electrical voltage) at the frequency f mentioned above.

[0032] As for the second chip 20, it constitutes a support well adapted to produce one or more components allowing power amplification at these very high frequencies, before emitting the signal thus amplified, by means of a radiating antenna 40. Here, the second chip 20 integrates a power amplifier 21 (“power amplifier PA”) adapted to these frequencies, produced for example in the form of a transistor (see [Fig.6]).

[0033] The first chip 10 and the second chip 20 are assembled one on top of the other, parallel to each other, to form a three-dimensional stack. The first chip 10 has a first surface 11 (upper surface of the first chip, here), and the second chip 20 has a second surface 21 (lower surface of the second chip, here), which faces the first surface 11. The two chips are thus assembled to each other with their surfaces 11 and 21 facing each other.

[0034] The first surface 11 corresponds more precisely to the free surface of the first chip 10 before assembly, microposts and assembly structure not included. It is a flat surface (in this case, it is the average plane of the free surface presented by the chip 10 before assembly). Similarly, the second surface 21 is the free surface of the second chip 20 before assembly, microposts and assembly structure not included.

[0035] A junction zone between chips, 30, extends from the first surface 11 to the second surface 21. This junction zone, which is an assembly zone between chips, comprises connecting elements between chips allowing them to be secured to each other. These connecting elements comprise complete micropillars, 32, which extend from the first chip 10 to the second chip 20 (and which are each formed by two microposts, or “posts” connected for example by a solder microball). A filling material 31 (generally called “undefill” in this technical field), optional, for example based on polymers, can fill the unoccupied part of the assembly zone 30 to obtain a more mechanically robust assembly.

[0036] The complete micropillars 32 also make it possible to electrically connect the first chip 10 to the second chip 20 to transmit from one chip to the other voltages or currents for supplying electronic components (see figures 6 and 7), or continuous signals (DC connections) or low-frequency signals (of a frequency well below 100, or even 10 or even 1 GHz). Indeed, here, each of the micropillars 32 is conductive, and thus allows electrical conduction from one chip to the other.

[0037] The first chip 10 is also connected to the second chip 20 by a coupling capacitor, C, located in the junction zone 30. This capacitor here connects the preamplifier 11 of the first chip to the power amplifier 21 of the second chip 20, in order to transfer the very high frequency signal mentioned above, from one chip to the other.

[0038] For this capacitive connection, we want to obtain a small impedance Z compared to the characteristic impedance of the transmission lines, which is here 50 Ohms. This in fact makes it possible to limit the return losses RL (losses due to reflection on the capacitive connection). Table 1 below brings together some values ​​of the impedance Z associated with such a capacitive connection, at a frequency of 300 GHz, for different values ​​of the capacitance of the coupling capacitor C. In this table, the return losses are expressed in decibels, i.e. RL(dB) = 20 log [((50+Z)-50) / (50+Z+50)], Z being expressed in Ohms.

[0039] [Tables 1] Table 1 C (fF) Z @ 300 GHz (Ohms) Rl (dB) 50 10.6 -20 100 5.3 -26 200 2.6 -32 500 1 -40

[0040] As illustrated by these values, if return losses of less than 20 decibels are desired (Z less than approximately 10 Ohms), it is desirable for the capacitance of the coupling capacitor C to be greater than 50 fF. Furthermore, in terms of size, an occupied surface area of ​​less than 100x100qm2 is generally desirable for such a component. The desired capacitance per unit area is therefore typically greater than or equal to 5 pF / mm2.

[0041] As we will see below, such values ​​can indeed be obtained by producing this coupling capacitor from armatures provided with microposts, for realistic dimensional parameters for this type of technology. The coupling capacitor C used in this example is now described in more detail, with reference to figures 3 to 5.

[0042] This capacitor includes: • a first conductive armature, 100, in electrical contact with the first chip 10 (more precisely, here, in electrical contact with an output terminal 12 of the preamplifier 11), and • a second conductive armature 200, in electrical contact with the second chip 20 (more precisely, here, in electrical contact with an input terminal 22, for example a grid, of the power amplifier 21).

[0043] The first and second armatures are electrically insulated from each other, i.e. they are separated from each other by an insulator (whether air or a solid insulating material such as the polymer-based filling material 31 mentioned above).

[0044] The first armature 100 comprises a first conductive plate 101, for example made of metal (sometimes called a “pad” in this technical field), which extends parallel to the first surface 11, against the first chip 10, for example against the first surface 11, or possibly slightly set back from it. The first armature 100 also comprises conductive microposts, 110, which extend from the first plate 101, towards the second chip 20 (see Figures 3 and 5).

[0045] Similarly, the second armature 200 comprises a second conductive plate 201, or “pad”, which extends parallel to the second surface 21, against the second chip 20, for example against the second surface 21 (or possibly slightly set back from it). The first armature 200 also comprises conductive microposts, 210, which extend from the second plate 201, towards the first chip 10.

[0046] In this first embodiment, the microposts 210 of the second armature are laterally offset relative to the microposts 110 of the first armature and extend almost to the first plate 101, while the microposts 110 of the first armature extend almost to the second plate 201. The microposts 110 and 210 are thus intercalated with each other, with their respective lateral surfaces located opposite each other. This arrangement makes it possible to increase the surface area over which the two armatures are in electrical influence with each other, by also exploiting the lateral surfaces 112, 212 of the microposts 110, 210. In other words, this makes it possible to increase the effective surface area of ​​the capacitor C, and therefore its electrical capacity.

[0047] As can be seen in [Fig. 3], each micropost 110 extends from the first plate 101, towards the second chip, to an end face 111. The axis of the micropost is perpendicular to the first chip while its end face 111 is parallel to the first chip. The end face 111 of the micropost is located at a reduced distance from the second plate 201 (in this case, at a small distance compared to the thickness of the junction zone 30). This distance, denoted ez, is for example less than 2 or even 0.5 microns. It can for example be between 0.1 and 0.5 microns. For each micropost 110, the end face 111 of the micropost thus extends opposite and at a reduced distance from a flat portion 202 of the second frame, more precisely opposite a small portion of the second plate 201 of this frame.

[0048] In the same way, each micropost 210 extends from the second plate 201, in the direction of the first chip 10, to an end face 211 of the micropost. The axis of the micropost is perpendicular to the second chip while its end face 211 is parallel to the second chip. The end face 211 of the micropost is located at a reduced distance from the first plate 101. This distance is for example less than 2 or even 0.5 microns (it can for example be between 0.1 and 0.5 microns). It can be equal to the distance ez mentioned above. For each micropost 210, the end face 211 of the micropost thus extends opposite and at a reduced distance from a flat portion 102 of the first frame, more precisely opposite a small portion of the first plate 101 of this frame.

[0049] As indicated above, for each micropost 110, a portion of the lateral surface 112 of the micropost 110 is located opposite the lateral surface 212 of one of the microposts 210, the microposts 110 and 210 being interposed with each other.

[0050] Here, the microposts 110 of the first reinforcement are distributed periodically on the first plate 101, forming a regular two-dimensional network. In this case, this network has a staggered pattern (a pattern that is repeated periodically), that is to say a square pattern with a micropost 110 at each vertex of the square and an additional micropost 110 in the center of the square (Figures 4 and 5).

[0051] The microposts 210 of the second reinforcement are also distributed periodically, on the second plate 201, forming a regular two-dimensional network, in this case a network identical to that of the first reinforcement. These two networks are offset laterally with respect to each other so as to fit together. The assembly comprising the microposts 110 and 210 then forms a square network, of pitch p, with an alternation between microposts 110 and microposts 210. In other words, on each row, and on each column of this matrix of microposts, there is a micropost 110, then a micropost 210, then a micropost 110, and so on. Each micro-post 210, except those located at the corners of the network, is thus interposed between several micro-posts 110.

[0052] The microposts 110 and 210 are here cylindrical, with a diameter d. From a lateral point of view, they are therefore separated two by two by a distance eL equal to pd.

[0053] A numerical simulation was carried out to determine the capacitance of the capacitor C for this geometry of the armatures, in a case where ([Fig.5]): • the diameter d of the microposts is 10 microns while their height is 15 microns, • the pitch p is 20 microns, • the gap ez is 1 micron, and where • each frame forms a square with sides measuring 80 microns (with eight microposts per frame, and sixteen microposts in total).

[0054] When the armatures are separated by air (relative permittivity er=1), the capacitance of the capacitor is then estimated at 23 femtofarad (fF), or 3.6 picoFarad per mm2 (3.6 pF / mm2). And when the space between armatures is filled with a filling polymer such as polyimide (for which the relative permittivity er is approximately 3.5 at the frequencies considered), the capacitance of the capacitor is then estimated at 80 femtofarad (fF), or 12.5 pF per mm2.

[0055] The examples of values ​​given above for the dimensions of the microposts and their spacing are typical of this type of assembly technology (these dimensions can also be slightly smaller). It can therefore be seen from this example that this type of capacitor structure actually makes it possible to obtain a capacitance per unit area adapted to the intended application, typically greater than 5, and even 10 pF / mm2, for realistic dimensions in terms of manufacturing.

[0056] In terms of dimensions, the micropillars used to make this capacitive connection can have a diameter d of between 10 and 50 microns, and a height also of between 10 and 50 microns. The lateral spacing eL between micropillars can be between d and twice d. The micropillars can be distributed with a surface density of, for example, between 5% and 25%. This surface density is equal to the section of a micropillar, multiplied by the number N of micropillars considered and divided by the total surface area over which these N micropillars are distributed (surface area occupied by these N micropillars). For example, for a square network, with a pitch p=2.d (i.e. eL=d, which corresponds to a type of structure whose manufacture is well controlled in practice), this surface density is 20%.

[0057] It may be noted, in terms of manufacturing, that this type of structure allows for fairly large tolerances in terms of alignment of the two chips with each other. Indeed, if the two chips are laterally offset with respect to each other, compared to the configuration presented above (i.e.: if each micropost 210 is not not positioned exactly in the middle, between two microposts 110), the capacitance value obtained will nevertheless remain close to that corresponding to a perfect alignment (in other words, the value of this capacitance is relatively insensitive to lateral alignment errors between chips). Indeed, in the event of an alignment error, each micropost 210 would be a little closer to one of the microposts 110 (which would tend to increase the value of the capacitance), but, in return, it would also be a little further from the other micropost 110 which frames it (which would tend on the contrary to reduce the capacitance in question, at least partially compensating for the increase in question, and limiting the variation in capacitance due to this misalignment).

[0058] Different variants can be made to the capacitor C of this first embodiment, for example by using another type of two-dimensional network, based on another pattern (for example a triangular pattern), or by using another arrangement of the microposts, for example a globally concentric or spiral arrangement. Furthermore, as mentioned above, smaller dimensions than those of the numerical example described above are conceivable, in particular for the spacing ez (which would lead to larger capacitance values ​​than in the numerical example in question).

[0059] [Fig.6] schematically represents the integrated circuit 1 of [Fig.2], in the form of an equivalent electrical diagram.

[0060] As can be seen in this figure, an electrical supply voltage Vs is applied to a supply terminal 13 of the preamplifier 11 of the first chip while the electrical ground M of the circuit is connected to a ground terminal 14 of the preamplifier. The output terminal 12 of the preamplifier 11 is connected to the first armature 100 of the coupling capacitor C, via a line or track having for example a line impedance of 50 Ohms.

[0061] On the other side of the junction zone 30, the second armature 200 of the coupling capacitor C is connected to the input terminal 22 of the power amplifier 21 (via a line having an impedance of 50 Ohms). This input terminal actually corresponds to the gate of the transistor which forms this amplifier, here. The source 24 of this transistor is connected to the ground M, in this case by being connected to the ground of the first chip via a complete micropillar 32 (DC micropillar) crossing the junction zone 30. The drain 23 of the transistor 21 is connected to a radiating antenna 40, to emit the very high frequency signal thus amplified.

[0062] The transistor is biased using the supply voltage Vs. More precisely, the voltage Vs is applied to the drain 23, while a voltage, reduced by an adjustment resistor Rbias, is applied to the gate 22. For this, the drain 23 and the gate 22 are each connected to a supply voltage source, located on the first chip (and which delivers the voltage Vs), via complete micropillars 32 (DC micropillars) passing through the junction zone 30. To prevent the very high frequency signals produced by the preamplifier 11, and by the power amplifier 21, from going up the DC power supply lines, a quarter-wave line 15, 16 is connected between the micropillar 32 considered and the supply voltage source in question, for each of these two micropillars 32. Each quarter-wave line 15, 16 is a portion of transmission line having a length equal to X / 4, where X is the wavelength of the signal in question.

[0063] [Fig. 7] represents, in the form of an equivalent electrical circuit, an integrated circuit 1' according to a second embodiment. The integrated circuit 1' is identical to the integrated circuit 1 of the first embodiment (shown in Figures 2 to 6), except that the amplified signal produced by the power amplifier passes back through the first chip 10 before being transmitted to the radiating antenna 40. For this, an additional coupling capacitor, C', is connected to the drain 23 of the transistor of the power amplifier. This coupling capacitor C' is identical, or at least similar to the coupling capacitor C shown above. The drain 23 is thus connected to a second armature of this capacitor (by a 50 Ohm line) while the first armature of this capacitor is connected to the radiating antenna 40 via an impedance Z, produced on the first chip 10, and allowing impedance matching with the antenna.The elements of circuit 1' which are identical, or at least corresponding to those of circuit 1, bear the same references as for circuit 1 of the first embodiment.

[0064] Other ways of producing an inter-chip coupling capacitor from one or more microposts, different from that of the first embodiment, can be envisaged, as can be seen in Figures 8 and 9.

[0065] [Fig.8] thus represents an integrated circuit 1” according to a third embodiment, similar to circuit 1 of the first embodiment, but in which the microposts 210” of the second frame 200” extend in line with the microposts 110'' of the first frame 100”, instead of being offset laterally relative to them.

[0066] For the rest, the integrated circuit 1” is identical, or at least essentially identical to the integrated circuit 1 of the first embodiment. The identical elements of these two embodiments are also identified by the same reference numbers.

[0067] The coupling capacitor C” of the integrated circuit 1” comprises, as previously, a first armature 100” in electrical contact with the first chip 10, and a second armature 200” in electrical contact with the second chip 20. The first armature and the second armature respectively comprise a first plate 101 and a second plate 201, as presented above. Furthermore, they each comprise one or more, here several microposts 110”, 210”.

[0068] As indicated above, the microposts 210” extend in line with the microposts 110”, that is to say by being aligned with the microposts 110” in a direction perpendicular to the chips. The microposts 210” as well as the microposts 110” each have a height close to half the thickness of the junction zone 30, and slightly less than this half-thickness (whereas in the first embodiment, the microposts 110 and 210 each had a height close to the thickness of the junction zone). Each pair of microposts, grouping together one of the microposts 110” and the micropost 210” located opposite, thus forms a sort of complete micropillar, but without solder microballs between the two microposts 110” and 210”.

[0069] Each micropost 110'' extends from the first plate 101, in the direction of the second chip 20, to an end face 111 parallel to the first chip. Similarly, each micropost 210” extends from the second wafer 201, in the direction of the first chip 10, to an end face 211 parallel to the second chip. For each pair of microposts 110” and 210” located opposite each other, the respective end faces 111 and 211 of the two microposts are located opposite and at a reduced distance from each other. They are parallel to each other. And here, they are entirely superimposed on each other. The gap ez which separates them is here less than 2, or even 0.5 microns. It can for example be between 0.1 and 0.5 microns.

[0070] For microposts of 10 microns in diameter and a spacing ez of 1 micron, we obtain, for each pair of 110”, 210” microposts, an elementary electrical capacitance of approximately 2.4 fF (with, for example, polyimide as filler material). Twenty or more microposts are then required on each armature (to obtain twenty 110'7210” pairs or more) to obtain a total electrical capacitance greater than or equal to 50 fF, for the coupling capacitor C”. Assuming that the microposts are arranged in a square network, with a pitch of 20 microns, we then obtain a capacitance per unit area of ​​approximately 6 pF / mm2, which is in the desired range.We can therefore also see that this type of capacitor structure makes it possible to obtain a capacitance per unit of surface adapted to the intended application (typically greater than 5 pF / mm2) for realistic dimensions in terms of manufacturing, especially since the ez gap could have a value of less than 1 micron, in practice.

[0071] [Fig.9] represents an integrated circuit 1”' according to a fourth embodiment. This integrated circuit 1”' is similar to circuit 1 of the first embodiment, but it comprises a coupling capacitor C”' whose second armature is devoid of micropost. For the rest, the integrated circuit 1”' is identical, or at least essentially identical to the integrated circuit 1 of the first embodiment. The identical elements of these two embodiments are identified by the same reference numbers.

[0072] The coupling capacitor C”' of the integrated circuit 1”' comprises, as previously, a first armature 100”' in electrical contact with the first chip 10, and a second armature 200'” in electrical contact with the second chip 20. The first armature and the second armature respectively comprise a first plate 101 and a second plate 201 as presented above. Furthermore, the first armature 100'” comprises at least one, here several microposts 110. On the other hand, the second armature 200'” is devoid of microposts.

[0073] The microposts 110 of the first armature extend in the direction of the second chip 20, from the first plate 101 to an end face 111 parallel to the first chip, and parallel to the second plate 200'”. For each micropost 110, the end face 111 of the micropost thus extends opposite and at a reduced distance from a flat portion 202 of the second armature 200”, more precisely opposite a small portion of the second plate 201. This distance is again noted ez. It is for example less than 2 microns, or even less than 0.5 microns (it can for example be between 0.1 and 0.5 microns).

[0074] The distribution of the microposts 110 on the first plate 101 may be different from the distribution of the microposts 110 presented above for the first embodiment. In particular, the surface density of microposts 110 may be greater than in the first embodiment (since there are no microposts belonging to the second electrode to be interposed between the microposts 110 of the first electrode).

[0075] Different variants can be made to the integrated circuits which have just been presented, in addition to those already mentioned.

[0076] Thus, the two chips could be made from the same type of semiconductor material (for example, silicon) instead of being made from two different types of materials. In addition, the integrated circuit could include one or more other chips, assembled with the two chips mentioned above to form a more complete three-dimensional stack (these other chips could also be connected to the rest of the circuit via one or more coupling capacitors, made in an assembly zone between chips).

[0077] Furthermore, the coupling capacitor mentioned above could be used to connect together other components than those mentioned above, and other types of functions than the amplification functions presented above could be implemented in such an integrated circuit.

Claims

Claims

1. Integrated circuit (1; 1'; 1”; 1'”) comprising a first chip (10) and a second chip (20) assembled on top of each other, the first chip being electrically connected to the second chip by a coupling capacitor (C; C'; C”; C”') which is located in a junction area (30) between chips, between the first chip (10) and the second chip (20), the coupling capacitor comprising: - a first conductive armature (100; 100”; 100'”), in electrical contact with the first chip (10), and - a second conductive armature (200; 200”; 200'”) in electrical contact with the second chip (20), - at least a portion of the first armature (100; 100”; 100”') being located opposite the second armature (200; 200”; 200”'), the first and second armatures being electrically insulated from each other, - at least a portion of the first armature (100; 100”; 100”') being formed by one or more electrically conductive microposts (110; 110”) which each extend from the first chip (10), in the direction of the second chip (20); integrated circuit in which: - the first armature (100; 100”; 100'”) of the coupling capacitor (C; C'; C”; C”') is electrically connected to a first electronic component (11; 40) of the transistor, diode, amplifier, antenna, waveguide or filter type, configured to generate, emit, transmit or filter an electrical signal of frequency greater than or equal to 10 GHz, or even 300 GHz; - the second armature (200; 200”; 200'”) is electrically connected to a second electronic component (21) of the transistor, diode, amplifier, antenna, waveguide or filter type.

2. Integrated circuit (1; 1'; 1”; 1'”) according to claim 1, wherein: - each micropost (110; 110”) extends perpendicularly to the first chip, from the first chip (10) to an end face (111) of the micropost, - and in which the second frame (200; 200”; 200'”) has, for each micropost (110; 110”), a face (211) or a portion (202) of a flat face located opposite and at a reduced distance (ez) from the end face (111) of this micropost (110; 110”).

3. Integrated circuit (1; 1'; 1”) according to one of claims 1 or 2, wherein at least part of the second armature (200; 200”) is formed by one or more additional electrically conductive microposts (210; 210”), which each extend in the direction of the first chip (10), from the second chip (20) to an end face (211) of the additional micropost (210; 210”).

4. Integrated circuit (1; 1') according to claim 3, wherein each micropost (110), as well as each additional micropost (210), is delimited laterally by a lateral surface (112, 212), and wherein at least some of the additional microposts (210) are laterally offset relative to said microposts (110), their respective lateral surfaces (212) each being located opposite the lateral surface (112) of one of said microposts (110).

5. Integrated circuit (1; 1') according to claim 4, wherein at least some of said additional microposts (210) are interposed between microposts (110) of the first armature (100).

6. Integrated circuit (1”) according to claims 1 and 3, wherein at least some of the additional microposts (210”) each extend opposite one of said microposts (110”), the end face (211) of the additional micropost (210”) in question being located opposite and at a reduced distance (ez) from an end face (111) of the corresponding micropost (110”), while being electrically insulated from the end face (111) of this micropost.

7. Integrated circuit (1”) according to claim 2, wherein the second armature (200”) is devoid of micropost.

8. Integrated circuit (1; 1'; 1”; 1'”) according to one of the preceding claims, wherein said microposts (110; 110”) are arranged periodically forming a regular network.

9. Integrated circuit (1; 1'; 1”; 1'”) according to one of the preceding claims- preceding, in which at least a portion (111) of the first armature (100; 100”; 100”') is separated from the second armature (200; 200”; 200'”) by a distance (ez) less than 2 microns, or even less than 0.5 microns.

10. Integrated circuit (1; 1'; 1”; 1'”) according to one of the preceding claims, in which the coupling capacitor (C; C'; C”; C'”) has an average electrical capacitance per unit area greater than or equal to 5 picofarad per square millimeter.

11. Integrated circuit (1; 1'; 1”; 1'”) according to one of the preceding claims, in which the coupling capacitor (C; C'; C”; C'”) has an electrical capacitance greater than or equal to 50 femtofarads.

12. Integrated circuit (1; 1'; 1”; 1'”) according to one of the preceding claims, wherein the first chip (10) is formed at least in part from a first type of semiconductor material while the second chip (20) is formed at least in part from a second type of semiconductor material different from the first type of semiconductor material.

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