Integrated circuit comprising a high-voltage transistor and corresponding manufacturing process

Abstract

The integrated circuit comprises at least one transistor (200, 400) having a disjoint gate structure (STG) and field plate (FP) arranged on a front face (FA) of a semiconductor substrate (PSUB), and a doped conduction region (D) in the semiconductor substrate located above an edge of the gate structure (RG2brd) and above an edge of the field plate (FPbrd1). Figure for the abbreviation: Fig 2

Description

Title of the invention: Integrated circuit comprising a high voltage transistor and corresponding manufacturing method

[0001] Embodiments and implementations relate to integrated circuits, in particular high voltage transistors.

[0002] Some types of integrated circuits use high voltages, i.e., for example, voltages greater than 12V (volts), for their operation and are at the same time constrained by the size of their components. This is particularly the case for non-volatile memories which use high voltages for write operations. High voltages can also be used for decoding in the memory when the memory cell network is designed according to a dense mesh of high-voltage transistors.

[0003] The evolution of transistor morphology tends towards increasingly narrow transistors (without significant reduction in length due to voltage withstand constraints). The reduction in transistor width results in a decrease in the avalanche voltage between the source-drain conduction regions and the substrate, due to a peak effect in the morphology of the doped regions and an increase in doping concentrations, to satisfy scaling rules following size reductions.

[0004] In this regard, reference is made to [Fig. 1], illustrating an example of a high-voltage transistor 100 comprising two levels of stacked and non-self-aligned gates, typically used in non-volatile memories. The high-voltage transistor 100 comprises a gate structure comprising a first gate G1 located on the surface of a semiconductor substrate PSUB and a second gate G2 covering the first gate, and extending beyond the first gate onto the surface of the substrate PSUB. The high-voltage transistor 100 comprises a conventional drain region D and a lightly doped drain region LDD (usually "Lightly Doped Drain" in English) located under the extending part of the second gate G2.In a conventional manner known to those skilled in the art, the lightly doped drain region LDD is implanted less deeply and with a lower dopant concentration than the conduction region D, and makes it possible to prevent avalanche phenomena at the drain-side end of the conduction channel of the transistor 100.

[0005] That being said, with the continued reductions in lithographic nodes and the width of the high voltage transistors 100, avalanche phenomena at the exterior of the drain D become problematic for high voltages used in the operation of the circuits. Indeed, in an area containing Injunction between the drain D and the PSUB substrate on the outer side of the drain D, i.e. in a BRD zone located along a lateral isolation region STI, the spatial variation of the dopant concentration is greater than between the rest of the volume of the PSUB substrate and the conduction region D. Furthermore, in the area of ​​the BRD junction on the outer side of the drain D, the morphology of the junction has a curvature that is all the greater the smaller the width of the transistor 100. The width of the transistor 100 corresponds to the extent of the channel region and the drain region D in the direction perpendicular to the section plane of [Fig.l]. By an effect comparable to a tip effect, the curvature of the junction in the BRD zone at the end of the transistor 100 contributes to locally increasing the electric field, and consequently to reducing the avalanche voltage. The narrower the transistor, the greater this curvature, and the more the avalanche voltage is locally reduced.However, the evolution of integrated circuits tends towards increasingly narrow transistors (in width).

[0006] Consequently, the PN junction between the drain region D and the PSUB substrate has a BRD locality having a high dopant concentration, and a high curvature morphology, so that the voltage resistance of the junction is locally smaller.

[0007] However, if high voltages cannot be reduced to accompany the reduction in size of transistors, as is the case for the operation of non-volatile memories, then the avalanche voltage becomes a technical blocking point in the reduction of the size of transistors in integrated circuits.

[0008] Thus there is a need to propose a solution making it possible to increase the voltage resistance of high voltage transistors, i.e. to increase the avalanche voltage, while reducing the size of the high voltage transistors.

[0009] According to one aspect, there is provided in this regard an integrated circuit comprising at least one transistor comprising a gate structure and a disjoint field plate, arranged on a front face of a semiconductor substrate, and a doped conduction region in the semiconductor substrate located directly above an edge of the gate structure and directly above an edge of the field plate.

[0010] The field plate makes it possible on the one hand to modulate the electric field present in the semiconductor substrate opposite the field plate, by field effect. On the other hand, the field plate makes it possible to extend a definition of a lightly doped region, typically on the channel side of the conduction region, towards the outer side of the conduction region, free of charge in terms of manufacturing steps. Thus, it is possible to benefit from an improvement in the voltage resistance on the edge of the conduction region, in addition to a typical improvement in the voltage resistance on the channel side of the transistor.

[0011] In this regard, according to one embodiment, said at least one transistor comprises in further a lightly doped conduction region implanted in the semiconductor substrate, extending on either side of the conduction region under the gate structure from said edge of the gate structure and under the field plate from said edge of the field plate.

[0012] This allows the avalanche voltage of the transistor to be increased from 0.5V to IV in a cost-free manner in terms of manufacturing process steps.

[0013] According to one embodiment, the conduction region has a first dopant concentration and extends into the substrate from the front face to a first depth, and the lightly doped conduction region has a second dopant concentration less than the first concentration, and extends into the substrate from the front face to a second depth less than the first depth.

[0014] According to one embodiment, the gate structure comprises a first gate region and a second gate region, the first gate region comprising a first conductive layer arranged on a first dielectric layer and being located on the front face of the substrate, the second gate region comprising a second conductive layer arranged on a second dielectric layer, the second gate region comprising an inner portion on the first gate region and an outer portion extending beyond the first gate region onto the front face of the substrate, the conduction region being located directly above the edge of the outer portion of the second gate region.

[0015] According to one embodiment, the lightly doped conduction region extends under the outer portion of the second gate region.

[0016] According to one embodiment, the field plate comprises a third conductive layer disposed on a third dielectric layer and is located on the front face of the substrate, the third conductive layer having the same composition and the same thickness as the second conductive layer, the third dielectric layer having the same composition and the same thickness as the second dielectric layer of the outer portion of the second gate region.

[0017] In other words, the field plate is produced by the same process steps as the second gate region, making it possible in particular to mask the implantation of the self-aligned conduction region on the material of the second gate region, so as to conceal this implantation under the field plate, and to keep the lightly doped conduction region under the field plate.

[0018] According to one embodiment, the field plate comprises a third conductive layer disposed on a third dielectric layer and is located on the front face of the substrate, the third conductive layer having the same composition and the same thickness as the first conductive layer, the third dielectric layer having the same composition and the same thickness as the first dielectric layer.

[0019] In other words, the field plate is produced by the same process steps as the first gate region, allowing for example to form the lightly doped conduction region under the field plate during the implantation of the conduction region, partially crossing the material of the first gate region.

[0020] According to one embodiment, the field plate is electrically connected to the conduction region.

[0021] This makes it possible to benefit from a field effect in the outer part of the conduction region, adapted to increase the avalanche voltage of the transistor additionally and independently of the presence of the lightly doped conduction region.

[0022] According to one embodiment, the edge of the field plate opposite said edge directly above the conduction region is located above a dielectric volume of a shallow isolation trench.

[0023] This is advantageous in terms of alignment of the field plate formation, and in terms of surface footprint since the field plate partially occupies an inactive surface opposite the shallow isolation trench.

[0024] According to another aspect, there is provided a method of manufacturing an integrated circuit comprising at least one formation of a transistor comprising: a formation of a gate structure and a disjoint field plate, arranged on a front face of a semiconductor substrate; and a formation of a doped conduction region in the semiconductor substrate located directly above an edge of the gate structure and directly above an edge of the field plate.

[0025] According to one embodiment, said at least one formation of the transistor further comprises: a formation of a lightly doped conduction region implanted in the semiconductor substrate, extending on either side of the conduction region under the gate structure from said edge of the gate structure and under the field plate from said edge of the field plate.

[0026] According to one embodiment, the formation of the conduction region comprises an implantation of dopants at a first concentration and with a first energy, and the formation of the lightly doped conduction region comprises an implantation of dopants at a second concentration lower than the first concentration and at a second energy lower than the first energy.

[0027] According to one embodiment, the formation of the gate structure comprises: - a formation of a first dielectric layer on the front face of the substrate, a formation of a first conductive layer on the first dielectric layer and an etching of the first conductive layer delimiting a first gate region, - a formation of a second dielectric layer, a formation of a second conductive layer on the second dielectric layer, and an etching of the second conductive layer delimiting a second gate region, such that the second gate region comprises an inner portion on the first gate region and an outer portion extending beyond the first gate region onto the front face of the substrate, - the formation of the conduction region comprising a self-aligned dopant implantation on the second gate region.

[0028] According to one embodiment, the formation of the lightly doped conduction region comprises a self-aligned implantation of dopants on the first gate region, before the steps of forming the second gate region.

[0029] According to one embodiment, the formation of the field plate comprises a formation of a third dielectric layer on the front face of the substrate, a formation of a third conductive layer on the third dielectric layer and an etching of the third conductive layer delimiting the field plate, simultaneously with the respective formations and etching of the second gate region.

[0030] According to one embodiment, the formation of the field plate comprises a formation of a third dielectric layer on the front face of the substrate, a formation of a third conductive layer on the third dielectric layer and an etching of the third conductive layer delimiting the field plate, simultaneously with the respective formations and etching of the first gate region, the formation of the lightly doped conduction region comprising an implantation of dopants through the field plate during the implantation of the conduction region.

[0031] According to one embodiment, the method further comprises forming an electrical connection between the field plate and the conduction region.

[0032] According to one embodiment, the method comprises forming a dielectric volume of a shallow isolation trench prior to forming the field plate, the forming of the field plate comprising delimiting the field plate such that the edge of the field plate opposite said edge directly above the conduction region is located above the dielectric volume of the shallow isolation trench.

[0033] Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments and implementations, which are in no way limiting, and the appended drawings, in which:

[0034] [Fig. 1] previously described, illustrates a conventional high voltage transistor;

[0035] [Fig.2] ;

[0036] [Fig.3] ;

[0037] [Fig.4] ;

[0038] [Fig.5] ;

[0039] [Fig.6] ;

[0040] [Fig.7] ;

[0041] [Fig.8] illustrate embodiments and implementations of the invention.

[0042] [Fig. 2] illustrates a top view and a sectional view of a first example of a transistor 200 suitable for high voltages, i.e. voltages typically greater than 12V (volts). The transistor 200 is produced in an integrated manner, for example in a non-volatile memory integrated circuit of the “EEPROM” type (for “Electrically Erasable and Programmable Read Only Memory”).

[0043] The transistor 200 comprises a gate structure STG and a disjoint field plate FP, arranged on a front face FA of a semiconductor substrate PSUB. The field plate FP is structurally comparable to a typical simple gate region of a transistor. The field plate FP is adapted to produce a field effect in the underlying semiconductor substrate (like a conventional transistor gate), but is not intended to form a conduction channel between two conduction regions (unlike a conventional transistor gate).

[0044] The front face FA of the semiconductor substrate PSUB, typically made of P-type doped silicon, is conventionally the face of the substrate from which the components of the integrated circuit are made, in a part usually called "FEOL" (for "Front End Of Line" in English, literally "line entry" in French, or "semiconductor part" usually in French). The region of the substrate PSUB on the side of the front face FA, in and on which the components of the integrated circuit are made, typically comprises doped wells of the same P-type as the substrate, and / or doped wells of the opposite N-type. In the following, the wells will not be distinguished with respect to the substrate, and will be referred to by the term "substrate".

[0045] Lateral isolation structures, for example of the shallow isolation trench type STI, make it possible to define an active region ACT in the substrate PSUB, in and opposite which the transistor 200 is produced. The active region ACT extends in length in a first direction, i.e. the horizontal direction in the orientation of the drawings of [Fig. 2], and in width perpendicular to the section plane of the drawing of [Fig. 2] and in the vertical direction of the orientation of the drawing of the top view of [Fig. 2]. Typically, the length of the active region of the transistor 200 is particularly constrained for the reduction in size of the transistors, because this would involve a reduction in the length of the channel of the transistor, which would reduce the source-drain voltage withstand (usually “Vds”). Furthermore, the reduction in the width of the active region ACT conventionally produces a reduction in the avalanche voltage between the drain and the substrate. The transistor 200 is advantageously configured to limit this reduction in the avalanche voltage and to withstand higher voltages than conventional transistors.

[0046] The transistor 200 comprises two conduction regions doped in the semiconductor substrate PSUB on either side of the gate structure STG, i.e. a source region S and a drain region D.

[0047] The gate structure STG is on the one hand advantageously configured to withstand high voltages, that is to say in particular not to generate an avalanche phenomenon in the channel region at voltages of the order of 12V, for example voltages between 12V and 13V. The gate structure STG comprises in this respect a first gate region RG1 and a second gate region RG2 superimposed, making it possible to obtain lightly doped conduction regions LDD, LDDs in the substrate PSUB having a greater extent under the gate structure STG than conventional single gate region transistors. Usually, the lightly doped conduction regions LDD, LDDs, LDD2 are called "lightly doped drain", independently of their positions on the source side S or drain side D.

[0048] The first gate region RG1 comprises a first dielectric layer D1, typically made of silicon oxide, located on the front face of the substrate FA and a first conductive layer PI, typically made of polycrystalline silicon, arranged on the first dielectric layer DL

[0049] The second gate region RG2 comprises a second dielectric layer D2, typically made of silicon oxide and / or nitride, and a second conductive layer P2, typically made of polycrystalline silicon, arranged on the second dielectric layer D2. The second gate region RG2 covers the entire width of the first gate region RG1 in an inner portion RG2int of the second gate region RG2, and extends beyond each side of the first gate region RG1, so as to cover the front face of the substrate FA in an outer portion RG2ext of the second gate region RG2.

[0050] The lightly doped conduction regions LDDs, LDD are located under the outer portions RG2ext of the second gate region RG2, and their ends on the channel side of the transistor are located directly above the respective edges of the first gate region RG1.

[0051] Indeed, as will be seen below in relation to [Fig.8], the first grid region RG1 can act as a self-aligned mask for the implantation of the lightly doped conduction regions LDDs, LDD.

[0052] The drain region D of the transistor 200 is located directly above an edge of the gate structure STG, i.e. directly above the edge RG2brd of the external portion RG2ext of the second grid region RG2, and directly above an edge FPbrdl of the field plate FP.

[0053] Indeed, as will be seen below in relation to [Fig.8], the second grid region RG2 as well as the field plate FP, can act as self-aligned masks for the implantation of the conduction regions S, D.

[0054] Also, the field plate FP comprises a “third” dielectric layer D2 located on the front face of the substrate FA and a “third” conductive layer P2 arranged on the third dielectric layer D2.

[0055] The definition of the field plate FP may extend outside the active region ACT in the first direction (i.e. in the direction of the length of the active region ACT), such that the edge FPbrd2 of the field plate FP opposite said edge FRbrdl directly above the drain D is located above the dielectric volume of the shallow isolation trench STI.

[0056] In this first example of transistor 200, the field plate FP advantageously has the same nature and the same composition as the second gate region RG2. The field plate FP and the second gate region RG2 are in this respect formed during the same manufacturing steps (see [Fig.8]). Thus, the third conductive layer P2 has the same composition (polycrystalline silicon) and the same (measurable) thickness as the second conductive layer P2, and the third dielectric layer D2 of the field plate FP has the same composition (silicon oxide and / or nitride) and the same (measurable) thickness as the second dielectric layer D2 located at the outer part RG2ext of the second gate region RG2.

[0057] In this context, the field plate FP produces precisely the same self-aligned mask effect for the implantation of the conduction regions S, D as the second gate region RG2.

[0058] Thus, the extent of the lightly doped conduction region LDDs, LDD, LDD2 is defined by the overflows RG2ext of the second gate region RG2 with respect to the first gate region RG1 opposite the active region ACT; and by the position of the field plate FP opposite the active region ACT.

[0059] Consequently, on the side of the drain region D, the lightly doped conduction region LDD, LDD2 extends on either side of the conduction region D, in the first direction, under the gate structure STG from said edge of the second gate region RG2brd and under the field plate FP from said edge of the field plate FPbrdl. On the side of the source region S, the lightly doped conduction region LDDs extends under the gate structure STG, in the first direction, from the edge of the second gate region RG2brd defining the implantation of the source S.

[0060] The conduction regions S, D have a first concentration of dopants and extend into the PSUB substrate from the front face FA to a first depth. The lightly doped conduction region LDDs, LDD, LDD2 (as is the case with conventional lightly doped drain regions) has a second dopant concentration lower than the first concentration, and extends into the PSUB substrate from the front face FA to a second depth lower than the first depth.

[0061] Furthermore, the field plate FP is advantageously electrically connected to the drain region D, for example via metal pillars of CNT contacts and a metal track of a metal level M1.

[0062] Indeed, it is typically the drain region D which is subject to avalanche phenomena, given that it is typically on the drain D that the greatest absolute potentials are applied, positively for an N-type transistor and negatively for a P-type transistor, while less great absolute potentials are typically applied on the source.

[0063] Consequently, the field effect at the PN junction between the drain and the substrate, generated by the field plate PL at the drain potential D, makes it possible to reinforce the voltage resistance of the PN junction, i.e. to increase the avalanche voltage of the transistor 200.

[0064] The effect of increasing the avalanche voltage of the transistor 200 by the field plate PL biased to a voltage of the same sign as the voltage of the drain region D is obtained by field effect in the PN junction and is not linked to the presence of the lightly doped conduction region LDD2 under the field plate PL.

[0065] That being said, as mentioned previously and described below in relation to [Fig.8], the presence of the PL field plate generates the presence of the lightly doped conduction region LDD2 under the PL field plate, by the self-aligned implantation steps.

[0066] Furthermore, the presence of the lightly doped conduction region LDD2 under the field plate PL also makes it possible to independently increase the avalanche voltage of the transistor 200.

[0067] In this regard, reference is made to [Fig.3].

[0068] [Fig. 3] represents a part of the cross-sectional view of the transistor 200 of [Fig. 2], in which the dopant concentration in the PSUB substrate is represented, and in particular in the drain region D and the lightly doped conduction region LDD, LDD2 under the gate structure STG and under the field plate FP. The dopant concentration is schematically represented by "isopleth" lines of equal concentrations of N-type dopants (for example, for the case of an N-type transistor), with the smallest concentration at the PSUB substrate and the largest concentration at the drain D.

[0069] The presence of the lightly doped conduction region LDD2, in particular under the field plate FP, results in the variation of the dopant concentration between the drain region D and the substrate PSUB, in particular at the edge of the shallow isolation region STI, being spatially more gradual than in conventional transistors 100 as illustrated in [Fig.l].

[0070] Indeed, the morphology of the dopant concentrations around the drain region D, LDD, LDD2 is substantially the same on the side of the gate structure STG as on the side of the field plate FP. Thus, in the transistor 200, the variation in the concentration of the dopants between the drain region D and the volume of the substrate PSUB is substantially the same in all directions of the volume.

[0071] As a result, the PN junction between the drain region D and the PSUB substrate does not have a high dopant concentration locality, and the PN junction between the drain region D and the PSUB substrate is capable of supporting larger voltages without producing an avalanche phenomenon.

[0072] [Fig.4] illustrates a top view and a sectional view of a second example of transistor 400 suitable for high voltages, typically greater than 12V, as a variant of transistor 200 described previously in relation to [Fig.2].

[0073] The common elements of transistor 400 with transistor 200 described in relation to [Fig.2], bear the same references and will not all be detailed again.

[0074] In particular, the gate structure STG, the source conduction regions S and drain D, and the lightly doped conduction region LDDs, LDD located under the gate structure STG of the transistor 400 are identical to the respective elements of the transistor 200 described in relation to [Fig.2].

[0075] In this variant of transistor 400, the field plate FP has the same nature and the same composition as the first gate region RG1, which are in this respect formed during the same manufacturing steps (see [Fig.8]). Thus, the third conductive layer PI of the field plate FP has the same composition (polycrystalline silicon) and the same (measurable) thickness as the first conductive layer PI of the first gate region RG1; and the third dielectric layer DI of the field plate FP has the same composition (silicon oxide) and the same (measurable) thickness as the first dielectric layer DI of the first gate region RG1. Typically, the thicknesses of the first conductive layer PI and of the first dielectric layer DI are respectively less than the thicknesses of the second conductive layer P2 and of the second dielectric layer D2.

[0076] Here again, the field plate FP can advantageously be electrically connected to the drain region D, in order to reinforce the voltage resistance of the PN junction by field effect, and thus increase the avalanche voltage of the transistor 400.

[0077] In this context, the FP field plate produces the same self-aligned mask effect for the implantation of the lightly doped conduction region LDDs, LDD than the first gate region RG1. In other words, the lightly doped conduction region LDD2 is not implanted under the field plate FP when implanting the lightly doped conduction region LDDs, LDD under the gate structure STG.

[0078] That being said, the implantation of the S, D conduction regions is done with a greater concentration and a greater energy than the implantation of the lightly doped conduction region LDDs, LDD, so that the first conductive layer PI and the first dielectric layer DI are partially permeable to the implantation of the S, D conduction regions.

[0079] Therefore, a second lightly doped conduction region LDD2 is implanted in the PSUB substrate through the field plate FP, when implanting the S, D conduction regions. The second lightly doped conduction region LDD2 has a dopant concentration lower than the concentration of the S, D conduction regions, and extends into the PSUB substrate from the front face FA to a depth less than the depth of the S, D conduction regions.

[0080] Thus, in a similar manner to the example described in relation to [Fig.2], the lightly doped conduction regions LDD, LDD2 extend on either side of the drain region D under the gate structure STG from the edge of the second gate region RG2brd and under the field plate FP from the edge of the field plate FPbrdl, directly above which the drain region D is located.

[0081] Here too, the presence of the second lightly doped conduction region LDD2 under the field plate PL makes it possible to increase the avalanche voltage of the transistor 200.

[0082] In this regard, reference is made to [Fig.5].

[0083] [Fig.5] represents a part of the sectional view of the transistor 400 of [Fig.4], in which the dopant concentration in the substrate PSUB is represented, and in particular in the drain region D and the lightly doped conduction regions LDD, LDD2 under the gate structure STG and under the field plate FP.

[0084] Analogously to the morphology of the dopant concentrations around the drain region D, LDD, LDD2 described in relation to [Fig.3], the presence of the second lightly doped conduction region LDD2 under the field plate FP, means that the PN junction between the drain region D and the substrate PSUB does not have a locality with high dopant concentration. Thus, the PN junction between the drain region D and the substrate PSUB is capable of supporting higher voltages without producing an avalanche phenomenon.

[0085] Furthermore, the embodiments of the transistor 200, 400 described previously in relation to FIGS. 2 to 5 indicate the presence of the field plate FP located on the outer side (in the first direction, i.e. in the length of the active region ACT) of the drain conduction region D. This is justified by the fact that avalanche phenomena typically occur on the drain D side of high-voltage transistors. However, in particular applications, it may be desirable to improve the voltage resistance of the PN junction between the source S and substrate PSUB. In this respect, the field plate FP as well as the lightly doped conduction region LDD2 under the field plate can perfectly be made symmetrically on the side of the source conduction region S, in order to obtain the same effects there.

[0086] [Fig. 6] shows measured results of avalanche voltages BV, between the drain region D and the substrate PSUB of transistor embodiments 200 as described in relation to [Fig. 2], of transistor embodiments 400 as described in relation to [Fig. 4], and of conventional transistor embodiments 100 as described in relation to [Fig. 1].

[0087] The avalanche voltages BV of the conventional transistors 100 are between 12.46V and 12.5V. The avalanche voltages BV of the transistors 200 are between 13.22V and 13.36V. The avalanche voltages BV of the transistors 400 are between 13.05V and 13.18V.

[0088] In other words, the presence of the field plate PL and the lightly doped conduction region LDD2 under the field plate makes it possible to increase the avalanche voltage of the high voltage transistors 200, 400 by substantially IV, compared to a conventional high voltage transistor 100.

[0089] In addition to being an advantage in itself, the gain of substantially IV on the avalanche voltage BV can be particularly beneficial for non-volatile memory technologies of the EEPROM type.

[0090] In this regard, reference is made to [Fig.7].

[0091] [Fig.7] represents a portion of a memory plane PM of an EEPROM type memory, in particular a memory word MWi,j belonging to a row RGj and to a column COLi. The memory word MWi,j, comprises at least one byte OCTOi, for example 4 bytes, of eight memory cells CEL each.

[0092] Each memory cell CEL comprises an access transistor TA and a state transistor TE having a floating gate and a control gate. The access transistor TA and the state transistor TE are coupled in series between a bit line BL0i-BL7i individually coupled to the drain of the access transistor TA, and a source line SLOi coupled to the source of the state transistor TE. The source line SLOi may be common for the memory cells CEL belonging to one or more bytes OCTOi, or even to all the memory cells CEL of the memory plane PM.

[0093] The gates of the access transistors TA of all the memory cells CEL of the same row RGj are coupled to a word line WLj dedicated to each row.

[0094] The control gates of the state transistors TE of the memory cells of the same memory word MWi,j are coupled to a control grid line CGi,j dedicated to a memory word MWi,j of a column COLi and a row RGj.

[0095] Access (decoding) to a control gate line CGi,j in the memory plane PM is done by means of a control gate switch circuit CGSWij located in a region CGSW of the memory plane PM near the respective memory word MWi,j.

[0096] Each control gate switch circuit CGSWij may comprise an inverter circuit comprising a high voltage PMOS transistor and a high voltage NMOS transistor. The high voltage PMOS and NMOS transistors are advantageously embodiments of high voltage transistors 200 described in relation to [Fig.2] or embodiments of high voltage transistors 400 described in relation to [Fig.4].

[0097] The PMOS and NMOS 200 / 400 transistors of the control gate switch circuit CGSWij are controlled by a control signal on their gates, transmitted on a common control line CLj and dedicated to each row RGj.

[0098] The drains of the complementary transistors 200 / 400 of the inverters of the respective switching circuits CGSWij are coupled to common and dedicated bias lines Dpi, Dni for each column COLi. Well bias lines Bn, Bp can be used to bias the complementary wells containing the PMOS and NMOS transistors. The sources of the complementary transistors 200 / 400 of the inverters of the switching circuits CGSWij are coupled to the respective control gate lines CGij.

[0099] Thus, the control line CLj of the row RGj and the polarization lines Dpi, Dni of the column COLi make it possible to transmit a polarization selectively on the control grid line CGij of the memory word MWij belonging to the column COLi and to the row RGj.

[0100] In writing operations of the memory cells CEL, the write voltages transmitted on the control gate line CGij are adapted to produce an injection of charges into the floating gate of the state transistor TE, by Fowler-Nordheim effect through a thickness of tunnel oxide.

[0101] The write voltages transmitted on the polarization lines Dpi, Dni are typically 15V, with a polarization of the Bn wells at 3V and of the Bp wells at 15V, so as not to exceed the avalanche voltage of the 200 / 400 transistors, which is typically close to 12V.

[0102] However, the gain of substantially IV on the avalanche voltages BV of the transistors 200 / 400 of the control gate switch circuit CGSWij can allow, for a given current budget, the use of higher write voltages in the memory. This would make it possible to increase the thickness of the tunnel oxide for better data retention, or to reduce the cycle time of writing.

[0103] Indeed, an increase of 500mV in the write voltage can allow an increase of 0.3 to 0.4 nm (nanometers) in the thickness of the tunnel oxide, providing an improvement of a factor of 10 in data retention; or allow a division by 2 of the duration of the write cycles.

[0104] Alternatively, the gain of substantially IV of the avalanche voltage can make it possible to reduce the consumption budget of the high voltage circuit, comprising numerous narrow transistors in the decoders and the control gate switch circuits CGSWi,j of the memory plane PM.

[0105] Another advantage of the transistors 200, 400 described in relation to figures 2 and 4 is to have, on the same transistor 200 / 400, both the benefit of the low current in the blocked state (usually "loff") of the conventionally narrow channel transistors (i.e. in the width of the active region ACT), and the benefit of the high avalanche voltage of the conventionally wide channel transistors (i.e. in the width of the active region ACT).

[0106] [Fig.8] illustrates an example of a manufacturing method 800 of the transistors 200, 400 described in relation to FIGS. 2 and 4.

[0107] The method 800 comprises a formation of at least one transistor comprising in particular: a formation 802-804, 806-808 of a gate structure STG and a field plate FP disjoint, arranged on a front face of a semiconductor substrate; and a formation 809 of an S / D doped conduction region in the semiconductor substrate located directly above an edge of the gate structure RG2brd and directly above an edge of the field plate FPbrd.

[0108] The method 800 comprises a formation 801 of a dielectric volume of a shallow isolation trench STI, making it possible in particular to define the active region ACT of the transistor 200 / 400.

[0109] The method 800 then comprises a formation 802 of a first dielectric layer DI on the front face of the substrate, then a formation 803 of a first conductive layer PI on the first dielectric layer DI and then an etching 804 of the first conductive layer PI delimiting the first gate region RG1.

[0110] In the context of the example transistor 400 described in relation to [Fig. 4], the etching 804 of the first conductive layer PI is configured to also delimit the field plate FP. Thus, the formation of the field plate FP is implemented simultaneously with the formation steps 802, 803 and with the etching step 804 of the first gate region RG1.

[0111] The etching 804 is configured to selectively etch the polycrystalline silicon more quickly than the silicon oxide of the first dielectric layer DI. That being said, the etching 804 is typically calibrated to “over-etch” the first conductive layer PI, i.e. remove a thickness greater than the actual thickness of the first conductive layer PI, in order to avoid any polycrystalline silicon residue. This over-etching removes a portion of the first dielectric layer DI not located under the gate, and a residual thickness of the first dielectric layer Dl remains.

[0112] The method 800 then comprises a formation 805 of a lightly doped conduction region LDDs, LDD, LDD2 implanted in the semiconductor substrate, in a self-aligned manner on the first gate region RG1, and possibly on the field plate formed during steps 802, 803 and 804.

[0113] Implantation 805 is implemented with a second concentration lower than the first concentration of step 809 and with a second energy lower than the first energy of step 809.

[0114] The method 800 then comprises a formation 806 of a second dielectric layer D2, on the structure obtained, then a formation 807 of a second conductive layer P2 on the second dielectric layer D2.

[0115] The method 800 then comprises an etching 808 of the second conductive layer P2 delimiting a second gate region RG2. The etching 808 is configured so that the second gate region RG2 comprises an inner portion RG2int on the first gate region and an outer portion RG2ext projecting outside the first gate region on the front face of the substrate.

[0116] In the context of the example of transistor 200 described in relation to [Fig.2], the etching 808 of the second conductive layer P2 is configured to also delimit the field plate FP. Thus, the formation of the field plate FP is implemented simultaneously with the formation steps 806, 807 and with the etching step 808 of the second gate region RG2. During steps 806, 807 and 808, the active region covered by the (future) field plate FP comprises the lightly doped conduction region LDD2 formed during the implantation step 805.

[0117] The formation 806 of the second dielectric layer D2 stacks on the residual thickness of the first dielectric layer D1, at the locations where the residual thickness of D1 is present. Thus, in absolute terms, under the outer portion RG2ext of the second gate region RG2 and under the field plate FP in the example transistor 200 described in relation to [Fig. 2], the second dielectric layer D2 comprises a stack of the residue of the partially etched first dielectric layer D1 (for example going from 22nm to 16nm thick after etching 804), and of the second dielectric layer added in step 806 (for example about 16nm thick, for a total of about 32nm thick). This stack ensures the gate-source and gate-drain voltage resistance of the second dielectric layer D2 at high voltages of the order of 12V to 13V.

[0118] The method 800 then comprises a formation 809 of the S / D conduction regions, comprising a self-aligned dopant implantation on the second gate region RG2, at a first concentration greater than the second concentration of step 805 and with a first energy greater than the second energy of step 805.

[0119] Simultaneously, in the context of the example transistor 400 described in relation to [Fig.4], a formation 809 of the lightly doped conduction region LDD2 under the field plate FP is implemented through the field plate FP during the implantation 809 of the conduction regions S / D.

[0120] Thus, at this step of the method 800, in the context of the two examples of transistors 200, 400 described in relation to FIGS. 2 and 4, the lightly doped conduction region LDDs, LDD, LDD2 extends on either side of the conduction region D under the gate structure STG from the edge of the gate structure and under the field plate FP from the edge of the field plate.

[0121] The method 800 then comprises a formation 810 of an electrical connection, typically by means of a CNT contact metal pillar and a metal track M1, connecting the field plate and the conduction region.

Claims

Claims

1. Integrated circuit comprising at least one transistor (200, 400) comprising a gate structure (STG) and a field plate (FP) which are disjoint, arranged on a front face (FA) of a semiconductor substrate (PSUB), and a doped conduction region (D) in the semiconductor substrate located directly above an edge of the gate structure (RG2brd) and directly above an edge of the field plate (FPbrdl).

2. An integrated circuit according to claim 1, wherein said at least one transistor (200, 400) further comprises a lightly doped conduction region (LDD, LDD2) implanted in the semiconductor substrate, extending on either side of the conduction region (D) under the gate structure (STG) from said edge of the gate structure (RG2brd) and under the field plate (FP) from said edge of the field plate (FPbrdl).

3. An integrated circuit according to claim 2, wherein the conduction region (D) has a first dopant concentration and extends into the substrate (PSUB) from the front face (FA) at a first depth, and the lightly doped conduction region (LDD, LDD2) has a second dopant concentration lower than the first concentration, and extends into the substrate (PSUB) from the front face (FA) at a second depth lower than the first depth.

4. Integrated circuit according to one of the preceding claims, wherein the gate structure (STG) comprises a first gate region (RG1) and a second gate region (RG2), the first gate region (RG1) comprising a first conductive layer (PI) arranged on a first dielectric layer (D1) and being located on the front face of the substrate (FA), the second gate region (RG2) comprising a second conductive layer (P2) arranged on a second dielectric layer (D2), the second gate region (RG2) comprising an inner portion (RG2int) on the first gate region (RG1) and an outer portion (RG2ext) projecting from the first gate region (RG1) onto the front face of the substrate (FA), the conduction region (D) being located directly above an edge (RG2brd) of the outer portion of the second gate region (RG2ext).

5. An integrated circuit according to claim 4 taken in combination with one of claims 2 or 3, wherein the lightly doped conduction region (LDD) extends under the outer portion of the second grid region (RG2ext).

6. Integrated circuit according to one of claims 4 or 5, wherein the field plate (FP) comprises a third conductive layer (P2) arranged on a third dielectric layer (D2) and is located on the front face of the substrate (FA), the third conductive layer (P2) having the same composition and the same thickness as the second conductive layer (P2), the third dielectric layer (D2) having the same composition and the same thickness as the second dielectric layer (D2) of the outer portion (RG2ext) of the second gate region (RG2).

7. Integrated circuit according to one of claims 4 or 5, wherein the field plate (FP) comprises a third conductive layer (PI) arranged on a third dielectric layer (Dl) and is located on the front face of the substrate (Fl), the third conductive layer (PI) having the same composition and the same thickness as the first conductive layer (PI), the third dielectric layer (Dl) having the same composition and the same thickness as the first dielectric layer (Dl).

8. Integrated circuit according to one of the preceding claims, in which the field plate (FP) is electrically connected (CNT, Ml) to the conduction region (D).

9. Integrated circuit according to one of the preceding claims, in which the edge of the field plate (FPbrd2) opposite said edge (FRbrdl) directly above the conduction region (D) is located above a dielectric volume of a shallow isolation trench (STI).

10. A method of manufacturing an integrated circuit comprising at least one formation (800) of a transistor comprising: a formation (802-804, 806-808) of a gate structure (STG) and a field plate (FP) which are disjoint, arranged on a front face of a semiconductor substrate; and a formation (809) of a doped conduction region (S / D) in the semiconductor substrate located directly above an edge of the gate structure (RG2brd) and directly above an edge of the field plate (FPbrd).

11. The method of claim 10, wherein said at least one formation (800) of the transistor further comprises: a formation (805) of a lightly doped conduction region (LDD) implanted in the semiconductor substrate, extending on either side of the conduction region (D) under the gate structure (STG) from said edge of the gate structure and under the field plate (FP) from said edge of the field plate.

12. The method of claim 11, wherein forming (809) the conduction region (S / D) comprises implanting dopants at a first concentration and with a first energy, and forming (805) the lightly doped conduction region (LDD) comprises implanting dopants at a second concentration lower than the first concentration and at a second energy lower than the first energy.

13. Method according to one of claims 10 to 12, wherein the formation of the gate structure comprises: - a formation (802) of a first dielectric layer (D1) on the front face of the substrate, a formation (803) of a first conductive layer (PI) on the first dielectric layer (D1) and an etching (804) of the first conductive layer (PI) delimiting a first gate region, - a formation (806) of a second dielectric layer (D2), a formation (807) of a second conductive layer (P2) on the second dielectric layer (D2), and an etching (808) of the second conductive layer (P2) delimiting a second gate region, such that the second gate region comprises an inner portion (RG2int) on the first gate region and an outer portion (RG2ext) projecting from the first gate region onto the front face of the substrate,- the formation (809) of the conduction region (S / D) comprising a self-aligned dopant implantation on the second gate region (D2, P2).,

14. A method according to claim 13 taken in combination with one of claims 11 or 12, wherein the formation (805) of the lightly doped conduction region (LDD) comprises a self-aligned dopant implantation on the first gate region (Dl, PI), before the steps of forming the second gate region.

15. A method according to one of claims 13 or 14, wherein the formation of the field plate (806-808) comprises a formation (806) of a third dielectric layer (D2) on the front face of the substrate, a formation (807) of a third conductive layer (P2) on the third dielectric layer and an etching (808) of the third conductive layer (P2) delimiting the field plate, simultaneously with the respective formations (806, 807) and etching (808) of the second grid region (D2, P2).

16. Method according to one of claims 13 or 14, wherein the formation of the field plate (802-804) comprises a formation (802) of a third dielectric layer (Dl) on the front face of the substrate, a formation (803) of a third conductive layer (PI) on the third dielectric layer and an etching (804) of the third conductive layer (PI) delimiting the field plate, simultaneously with the respective formations (802, 803) and etching (804) of the first gate region (Dl, PI), the formation (809) of the lightly doped conduction region (LDD2) comprising an implantation of dopants through the field plate during the implantation (809) of the conduction region (S / D).

17. The method of one of claims 10 to 16, further comprising forming (810) an electrical connection (CNT - Ml) between the field plate and the conduction region.

18. Method according to one of claims 10 to 17, comprising a formation (801) of a dielectric volume of a shallow isolation trench (STI) prior to the formation of the field plate, the formation of the field plate comprising a delimitation of the field plate (GRV1, GRV2) so that the edge of the field plate opposite said edge directly above the conduction region is located above the dielectric volume of the shallow isolation trench (STI).

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