Electronic device

Abstract

Electronic device Electronic device (100, 200) comprising: a first electronic chip (110) and a second electronic chip (130); and an interconnection circuit (150) comprising a first flat surface (151); a first region (115) of a first surface (116) of the first electronic chip (110) being assembled by hybrid bonding to a first region (157) of the first surface of the interconnection circuit (150), a first region (134) of a first surface (133) of the second electronic chip (130) being assembled by hybrid bonding to a second region (154) of the first surface of the interconnection circuit (150) so that the first electronic chip (110) is electrically connected to the second electronic chip (130) through the interconnection circuit (150);the first surface of the first electronic chip (110) comprising a second region (114) which is not in contact with the interconnect circuit (150) and comprising at least one connection pad (111). Figure for the abbreviation: Fig. 1;

Description

Title of the invention: Electronic device Technical field

[0001] The present description relates generally to electronic devices and associated manufacturing methods. Prior art

[0002] In order to follow Moore's law concerning the juxtaposition or stacking of the number of heterogeneous electronic chips per unit area, one solution implemented is, for example, the use of an interconnection substrate on which the chips are mounted, the substrate being provided with through-silicon vias (TSV). However, the use of these through-silicon vias is problematic because it causes limitations in radio frequency in particular and their implementation is expensive. Other limitations of through-silicon vias are linked to the loss of usable surface area due to the footprint of the through-silicon vias and also the need to adapt the connection pitches to the size of the through-silicon vias. Summary of the invention

[0003] There is a need to integrate several chips having, for example, heterogeneous functions, without using through vias and while limiting manufacturing costs.

[0004] One embodiment overcomes all or part of the drawbacks of known electronic devices.

[0005] One embodiment provides an electronic device comprising: - a first electronic chip and a second electronic chip; and - an interconnection circuit comprising a first planar surface; a first region of a first surface of the first electronic chip being assembled by hybrid bonding to a first region of the first surface of the interconnection circuit, a first region of a first surface of the second electronic chip being assembled by hybrid bonding to a second region of the first surface of the interconnection circuit so that the first electronic chip is electrically connected to the second electronic chip through the interconnection circuit; the first surface of the first electronic chip further comprising a second region which is not in contact with the interconnection circuit and comprising at least one connection pad.

[0006] One embodiment provides a method of manufacturing an electronic device comprising: - providing a first electronic chip, a second electronic chip and a connection circuit comprising a first planar surface; - assembling, by hybrid bonding, a first region of a first surface of the first electronic chip to a first region of the first surface of the interconnection circuit and assembling, by hybrid bonding, a first region of a first surface of the second electronic chip to a second region of the first surface of the interconnection circuit so that the first electronic chip is electrically connected to the second electronic chip through the interconnection circuit; the first surface of the first electronic chip further comprising a second region which is not in contact with the interconnection circuit and comprising at least one connection pad.

[0007] According to one embodiment, the first and second electronic chips as well as the connection circuit comprise a substrate and conductive tracks, the conductive tracks of the first electronic chip being arranged on a plurality of levels and comprising at least one connection element arranged on the first surface of the first region of the first electronic chip, the conductive tracks of the second electronic chip being arranged on a plurality of levels and comprising at least one connection element arranged on the first region of the first surface of the second electronic chip, and the conductive tracks of the interconnection circuit comprising at least one connection element arranged on the first and second regions of the first surface of the interconnection circuit;the connection element of at least one of the conductive tracks of the first region of the first electronic chip being in contact with the connection element of at least one of the conductive tracks of the first region of the interconnection circuit, the connection element of at least one of the conductive tracks of the first region of the second electronic chip being in contact with the connection element of at least one of the conductive tracks of the second region of the interconnection circuit.;

[0008] According to one embodiment, the first electronic chip comprises one or more active or passive components connected to the conductive tracks of the first electronic chip, the connection element of the conductive tracks of the first electronic chip is surrounded at least in part by an insulator, the second electronic chip comprises one or more active or passive components connected to the conductive tracks of the second electronic chip, the connection element of the conductive tracks of the second electronic chip is surrounded at least in part by an insulator, the interconnection circuit comprises one or more active or passive components connected to the conductive tracks of the interconnection circuit, and the connection element of the conductive tracks of the interconnection circuit is surrounded at least in part by an insulator.

[0009] According to one embodiment, the assembly by hybrid bonding of the first region of the first surface of the first electronic chip to the first region of the first surface of the interconnection circuit is carried out: between the connection element of at least one of the conductive tracks of the first region of the first surface of the first electronic chip and the connection element of at least one of the conductive tracks of the first region of the first surface of the interconnection circuit, and / or between the insulator surrounding the connection element of said at least one of the conductive tracks of the first region of the first surface of the first electronic chip and the insulator surrounding the connection element of said at least one of the conductive tracks of the first region of the first surface of the interconnection circuit; and the hybrid bonding assembly of the first region of the second electronic chip to the second region of the interconnection circuit is carried out: between the connection element of at least one of the conductive tracks of the first region of the first surface of the second electronic chip and the connection element of at least one of the conductive tracks of the second region of the first surface of the interconnection circuit; and / or between the insulator surrounding the connection element of said at least one of the conductive tracks of the first region of the first surface of the second electronic chip and the insulator surrounding the connection element of said at least one of the conductive tracks of the second region of the first surface of the interconnection circuit.

[0010] According to one embodiment, the interconnection circuit has a thickness less than or equal to 100 micrometers.

[0011] According to one embodiment, the first electronic chip and the second electronic chip are reverse chips.

[0012] According to one embodiment, the electronic device comprises a connection substrate comprising one or more connection pads arranged at a contact surface of the connection substrate, one or more electrical connection elements connecting the one or more connection pads of the second region of the first electronic chip to the connection pads of the connection substrate.

[0013] According to one embodiment, the first surface of the second electronic chip further comprises a second region which is not in contact with the interconnection circuit and which comprises at least one connection pad arranged at the first surface of the second electronic chip.

[0014] According to one embodiment, the substrate of the interconnection circuit is in contact with the contact surface of the connection substrate.

[0015] According to one embodiment, prior to the hybrid bonding assembly step, the first and second electronic chips are held fixed on a transfer substrate and, after the hybrid bonding assembly step, the first and second electronic chips are separated from said transfer substrate.

[0016] According to one embodiment, in a connection step, said at least one of the connection pads of the second region of the first surface of the first electronic chip is brought into contact, by a thermal and / or mechanical treatment, with one end of one of the electrical connection elements, and said electrical connection element is brought into contact, with said treatment, with one of the connection pads of the connection substrate.

[0017] According to one embodiment, in the connection step, said at least one of the connection pads of the second region of the first surface of the second electronic chip is brought into contact, by a thermal and / or mechanical treatment, with one end of one of the electrical connection elements, and another end of said electrical connection element is brought into contact, with said treatment, with another of the connection pads of the connection substrate.

[0018] According to one embodiment, prior to the connection step, the assembly formed by the first electronic chip, the second electronic chip and the interconnection circuit is turned over so that the interconnection circuit is on the side of the connection substrate and so that the connection pads of the first and second electronic chips are oriented towards the connection substrate.

[0019] According to one embodiment, the device comprising another interconnection circuit comprising a first planar surface and a third electronic chip; a first region of the third electronic chip being assembled by hybrid bonding to a first region of the first surface of the other interconnection circuit; the second region of the first electronic chip being hybrid bonded to a second region of the first surface of the other interconnection circuit so that the first electronic chip is electrically connected to the third electronic chip through the other interconnection circuit. Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0021] [Fig.l] represents an electronic device according to an embodiment of the present description;

[0022] [Fig.2] represents an electronic device according to another embodiment of the present description;

[0023] [Fig. 3] represents a method of manufacturing the electronic devices of Figures 1 and 2; and

[0024] [Fig.4] is an enlarged schematic sectional view of a device according to another embodiment of the present description. Description of the embodiments

[0025] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0026] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. For example, molecular or hybrid or direct bonding methods between integrated circuits are known to those skilled in the art and will not be described in detail here.

[0027] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0028] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0029] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0030] [Fig. 1] shows an electronic device 100 according to an embodiment of the present description. The electronic device 100 comprises a first electronic chip 110 and a second electronic chip 130. The first and second chips 110, 130 each comprise, for example, a substrate 112, 132, electronic tracks 117, 137 and active or passive components 118, 138. The substrates 112, 132 are, for example, made of a semiconductor material such as silicon. The electronic tracks 117, 137 are, for example, stacked on several interconnection levels and they are connected to the components 118, 138. In one example, the first and second chips 110, 130 are flip-type chips (FLIP CHIP in English).

[0031] The electronic device 100 further comprises, for example, an interconnection circuit 150 comprising, for example, a first planar surface 151. The interconnection circuit 150 comprises, for example, a substrate 152 which is, for example, semiconductor, electronic tracks 156 and optionally active or passive components 158. The electronic tracks 156 are, for example, stacked on several interconnection levels and, for example, connected to the components 158. The electronic tracks 156 of the interconnection circuit 150 comprise, for example, at least one connection element 153 arranged on the first surface 151 of the interconnection circuit 150. The connection elements 153 are, for example, flush and with a planar surface, and are compatible with hybrid bonding or direct contact with one of the connection elements 113.

[0032] The first electronic chip 110 comprises, for example, a first region 115 of a first surface 116, the first region 115 being in contact with a first region 157 of the surface 151 of the interconnection circuit 150. For example, the first region 115 of the first electronic chip 110 is assembled by hybrid bonding to the first region 157 of the interconnection circuit 150. A hybrid bonding between two surfaces corresponds to a bonding both between portions of metal of each surface, such as connection elements, and between portions of insulation surrounding the portions of metal.

[0033] The first surface 116 of the first electronic chip 110 comprises, for example, a second region 114 which is not in contact with the interconnection circuit 150 and at the level of which are arranged, for example, connection pads 111 connected to the tracks 117. The connection pads 111 comprise, for example, one or more barrier layers such as for example titanium and / or tantalum nitrides.

[0034] The second electronic chip 130 comprises, for example, a first region 134 of a first surface 133, the first region 134 being, for example, assembled by hybrid bonding to a second region 154 of the first surface 151 of the interconnection circuit 150. In doing so, the first electronic chip 110 is, for example, electrically connected to the second electronic chip 130 via the interconnection circuit 150. In an example not illustrated, this makes it possible to make a direct electrical connection between the interconnection network 117 of the chip 110, to the interconnection network 137 in the chip 130, passing through the conductive tracks 157 of the interconnection circuit 150, without passing through the active / passive devices 158 of the interconnection circuit 150. The first surfaces 116, 133 of the first and second chips 110, 130 are located, for example, on the same horizontal plane. The first and second chips 110, 130 have, for example, the same height, each chip 110, 130 comprising, for example, a second surface opposite their first surface, the second surfaces of the first and second chips 110, 130 also being, for example, on the same horizontal plane. However, it will also be possible for the first and second chips 110, 130 to have different heights relative to each other. The first and second chips 110, 130 are, due to the bonding, integral with the connection circuit 150. This makes it possible to manipulate the assembly resulting from the hybrid bonding.

[0035] The electronic tracks 117 of the first electronic chip 110 comprise, for example, at least one connection element 113 arranged on the first surface 116 of the first region 115 of the first electronic chip 110. The connection element 113 is, for example, flush with the surface and allows contact to be made from the outside of the chip. The electronic tracks 137 of the second electronic chip 130 comprise, for example, at least one connection element 135 arranged on the first surface 133 of the first region 134 of the first electronic chip 130. The electronic tracks 156 of the interconnection circuit 150 comprise, for example, at least one connection element 155 arranged on the first surface 151 of the interconnection circuit 150.The connection elements 155 are, for example, flush and with a flat surface, and are compatible with hybrid bonding or direct contact with one of the connection elements 135 of the second chip 130. The connection elements 113, 135 of the conductive tracks of the first and second electronic chips 110, 130 as well as those 153, 155 of the interconnection circuit 150 are, for example, surrounded at least in part by an insulator. In one example, this insulator is the same for the first and second chips 110, 130 as well as for the interconnection circuit 150. This allows optimal hybrid bonding. The insulator is, for example, silicon oxide or a low-k insulator.

[0036] The connection elements 113, 135, 153 and 155 are, for example, connection pads and / or flat conductive surfaces and / or surfaces having undergone surface preparation to make them suitable for hybrid bonding. This surface preparation step consists, for example, of chemical-mechanical polishing and / or cleaning, and / or chemical activation on the surface to improve adhesion.

[0037] According to one example, the assembly by hybrid bonding of the first region 115 of the first surface 116 of the first electronic chip 110 to the first region 157 of the first surface 151 of the interconnection circuit 150 is carried out between the connection element 113 of at least one of the conductive tracks of the first region 115 of the first surface 116 of the first electronic chip 110 and the connection element 153 of at least one of the conductive tracks of the first region 157 of the first surface of the interconnection circuit 150. The hybrid bonding is, for example, carried out between the insulator surrounding the connection element 113 of at least one of the conductive tracks 117 of the first region 115 of the first surface 116 of the first electronic chip 110 and the insulator surrounding the connection element 153 of at least one of the conductive tracks of the first region 157 of the first surface 151 of the interconnection circuit 150. The insulator undergoes, for example, a preparation prior to the hybrid bonding. This preparation may consist of chemical-mechanical polishing and / or cleaning, and / or chemical activation on the surface to improve adhesion

[0038] According to an example, the assembly by hybrid bonding of the first region 134 of the second electronic chip 130 to the second region 154 of the interconnection circuit 150 is produced between the connection element 135 of at least one of the conductive tracks of the first region 134 of the first surface 133 of the second electronic chip 130 and the connection element 155 of at least one of the conductive tracks of the second region 154 of the first surface of the interconnection circuit 150. The hybrid bonding is, for example, produced between the insulator surrounding the connection element 135 and the insulator surrounding the connection element 155 of at least one of the conductive tracks of the second region 154 of the first surface 151 of the interconnection circuit 150.

[0039] The use of hybrid bonding makes it possible to create reliable and high-quality contacts.

[0040] Such an electronic device 100 makes it possible to connect two chips having, for example, heterogeneous functions without using through vias. The interconnection circuit 150 of [Fig.l] does not need to be larger than the two chips 110, 130, and this makes it possible to limit manufacturing costs.

[0041] The first surface 133 of the second electronic chip 130 comprises, for example, a second region 136 which is not in contact with the interconnection circuit 150 and which comprises, for example, several connection pads 131. In one example, a single connection pad 131 can be envisaged. The connection pad(s) 131 are, for example, connected to the tracks 137. The connection pads 131 comprise, for example, one or more barrier layers such as for example titanium and / or tantalum nitrides. In one example, the connection pads 131 are similar to the connection pads 111.

[0042] According to the example of [Fig.l], the electronic device 100 optionally comprises a connection substrate 180 which comprises, on a contact surface 181, for example, connection pads (not shown), for example, similar to the connection pads 111, 131 of the first or second electronic chip 110, 130. The connection pads of the substrate 180 are connected, for example, to electrical tracks (not shown) arranged, for example, in a routing substrate 182 of the connection substrate 180. Electrical connection elements 119 connect, for example, the connection pads 111, 131 of the first and / or second electronic chip 110, 130 with the connection pads of the connection substrate 180. The electrical connection elements 119 consist, for example, of one or more conductive balls. In another example, the electrical connection elements 119 comprise copper pillars or microbeads positioned on a connection pad (Under Bump Metallurgy, UBM, in English) on the surface of the chip, forming a solder pad, which can be soldered to the connection pads provided on the surface of the substrate 180. In one example, the connection elements 119 are formed by soldering between one or more conductive balls and a copper pillar, for example, by thermocompression or by heat treatment.

[0043] In an example not illustrated, a protective material (Underfill in English) is implemented between the first chip 110 and the connection substrate 180. The protective material is, for example, present in spaces 160 between the electrical connection elements 119 and / or in spaces 162 between the surfaces 116 and 181. The proportion of the protective material used depends on the application and may be evaluated by the person skilled in the art in a search for a compromise between mechanical robustness and thermal performance, for example. The protective material is, for example, hardened, after application by liquid means, by an ultraviolet and / or thermal treatment.

[0044] In the example of [Fig.l], the substrate 152 of the interconnection circuit 150 is in contact with the contact surface 181 of the connection substrate 180. This ensures the stability of the device 100.

[0045] [Fig.2] represents an electronic device 200 according to another embodiment of the present description.

[0046] The electronic device 200 is similar to the device 100, except that the second chip 130 does not exceed the width of the interconnection circuit 150. In the example of [Fig. 2], the second electronic chip 130 does not have a second region 136 and also no connection pads 131. The second electronic chip 130 is therefore not soldered or connected to a connection substrate 180.

[0047] The connection substrate 180 is not illustrated in [Fig. 2], but could be present, and connected to the first chip 110 as in the device 100 of [Fig. 1]. It would also be possible that the devices 100, 200 of FIGS. 1 and 2 do not include a substrate 180, and that the connection pads 111, 131 are connected to other circuits for example by connection wires.

[0048] [Fig. 3] represents a method of manufacturing the electronic devices of Figures 1 and 2.

[0049] In a step 302 (PROVIDING INTERCONNECTION CIRCUIT), the connection circuit 150 is provided.

[0050] In a step 304 (PROVIDING FIRST AND SECOND CHIPS ON A TRANSFER SUBSTRATE), the first electronic chip 110 and the second electronic chip 130 are provided.

[0051] In a step 306 (FIX FIRST AND SECOND CHIPS ON THE TRANSFER SUBSTRATE BY MOLDING), which is optional, the first electronic chip 110 and the second electronic chip 130 are held fixed, for example side by side on a transfer substrate (not shown). This step can be carried out, for example, by depositing the first and second chips 110, 130 on the transfer substrate, then depositing a molding material in order to hold, after curing, the two chips in place.

[0052] In a step 308 (MOLECULAR BONDING OF FIRST CHIP AND SECOND CHIP ON THE INTERCONNECTION CIRCUIT), the first and second chips 110, 130 are assembled by hybrid bonding to the interconnection circuit 150.

[0053] In a step 310 (REMOVE TRANSFER SUBSTRATE), which is optional, the transfer substrate is detached from the first and second electronic chips 110, 130, for example by a laser or thermal or mechanical detachment treatment, depending on the temporary bonding material considered.

[0054] In a step 312 (FLIP ASSEMBLY OF FIRST CHIP, SECOND CHIP AND INTERCONNECTION CIRCUIT), which is optional, the assembly formed by the first and second electronic chips 110, 130, which are molecularly bonded to the interconnection circuit 150, is flipped.

[0055] In a step 314 (CONNECTING CONTACT PADS OF FIRST CHIP WITH CONTACT ELEMENTS OF CONNECTION SUBSTRATE), which is optional, the connection pads 111, 131 respectively of the first and second electronic chip 110, 130 are brought into contact, for example by welding or thermocompression or heat treatment, with the connecting elements 119, which are themselves brought into contact with the respective connection pads of the connection substrate 180.

[0056] Such a method makes it possible to limit manufacturing costs with parallel processing of the assembly, and it also makes it possible to improve assembly precision.

[0057] [Fig.4] represents an enlarged schematic sectional view of the device 100 according to another embodiment of the present description. In the example of [Fig. 4], the first and second electronic chips 110, 130 as well as the interconnection circuit 150 are, for example, similar to those of figures 1 or 2. The view of [Fig. 4] focuses on the interface between the first chip 110 and the interconnection circuit 150.

[0058] In the example of [Fig.4], the tracks 117 of the first chip 110 are connected or linked, for example, to the connection pads 111 of the region 114 of the first surface 116, and to the connection elements 113 of the region 115 of the first surface 116.

[0059] The connection pads 111 comprise, for example, one or more barrier layers (not shown) such as, for example, titanium and / or tantalum nitrides. An insulating layer 402 covers, for example, in part one face of the connection pads 111 arranged towards the electrical connection element 119, while leaving an opening on which is arranged, for example, the connection element 119.

[0060] At the level of the first region 115 of the first chip 110, at least one connection element 113 is, for example, flush with the surface and is capable of being in contact with the corresponding connection element 153 of the interconnection circuit 150, which is arranged opposite.

[0061] Thus, the surface 116 of the chip 110 comprises both connection pads 111 capable of being connected to connecting elements, for example balls or pillars, and connection elements 113 capable of being placed in direct contact, by hybrid bonding, with corresponding connection elements 153 of the interconnection circuit 150.

[0062] A similar arrangement is, for example, implemented between the second chip 130 and the interconnection circuit 150.

[0063] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art. In particular, those skilled in the art will be able to implement a number greater than 2 electronic chips so that they are assembled with hybrid bonding to the same interconnection circuit while being electrically connected to each other. In another case, the number of electronic chips is greater than 2 and they are assembled in a chain two by two with a separate interconnection circuit between each pair of assembled chips.

[0064] In one example, the device comprises, for example, another interconnection circuit comprising a first planar surface and a third electronic chip. In this example, a first region of the third electronic chip is assembled by hybrid bonding to a first region of the first surface of the other interconnection circuit. In this example, the second region 114 of the first electronic chip is assembled by hybrid bonding to a second region of the first surface of the other interconnection circuit so that the first electronic chip is electrically connected to the third electronic chip through the other interconnection circuit. Such an example makes it possible to easily interconnect several chips having several functions without having to use through vias.

[0065] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. An electronic device (100, 200) comprising: - a first electronic chip (110) and a second electronic chip (130); and - an interconnection circuit (150) comprising a first planar surface (151); a first region (115) of a first surface (116) of the first electronic chip (110) being assembled by hybrid bonding to a first region (157) of the first surface of the interconnection circuit (150), a first region (134) of a first surface (133) of the second electronic chip (130) being assembled by hybrid bonding to a second region (154) of the first surface of the interconnection circuit (150) so that the first electronic chip (110) is electrically connected to the second electronic chip (130) through the interconnection circuit (150);the first surface of the first electronic chip (110) further comprising a second region (114) which is not in contact with the interconnection circuit (150) and comprising at least one connection pad (111); the electronic device comprising a connection substrate (180) comprising one or more connection pads arranged at a contact surface (181) of the connection substrate (180), one or more electrical connection elements (119) connecting the one or more connection pads (111) of the second region (114) of the first electronic chip (110) to the connection pads of the connection substrate (180); and a substrate (152) of the interconnection circuit (150) being semiconducting and in contact with the contact surface (181) of the connection substrate (180).;

2. A method of manufacturing an electronic device comprising: - providing a first electronic chip (110), a second electronic chip (130) and a connection circuit comprising a first planar surface; - assembling, by hybrid bonding, a first region of a first surface of the first electronic chip (110) to a first region of the first surface of the interconnection circuit (150)

3. and assembling, by hybrid bonding, a first region of a first surface of the second electronic chip (130) to a second region of the first surface of the interconnection circuit (150) so that the first electronic chip (110) is electrically connected to the second electronic chip (130) through the interconnection circuit (150); the first surface of the first electronic chip (110) further comprising a second region which is not in contact with the interconnection circuit (150) and comprising at least one connection pad (111); the electronic device comprising a connection substrate (180) comprising one or more connection pads arranged at a contact surface (181) of the connection substrate (180), one or more electrical connection elements (119) connecting the one or more connection pads (111) of the second region (114) of the first electronic chip (110) to the connection pads of the connection substrate (180); and a substrate (152) of the interconnection circuit (150) being semiconductive and in contact with the contact surface (181) of the connection substrate (180). Device according to claim 1, wherein the first and second electronic chips (110, 130) as well as the connection circuit (150) comprise a substrate (112, 132) and conductive tracks (117, 137), wherein the conductive tracks (117) of the first electronic chip (110) are arranged on a plurality of levels and comprise at least one connection element (113) arranged on the first surface of the first region (115) of the first electronic chip (110), wherein the conductive tracks (137) of the second electronic chip (130) are arranged on a plurality of levels and comprise at least one connection element (135) arranged on the first region (134) of the first surface of the second electronic chip (130), and wherein the conductive tracks of the interconnection circuit (150) comprise at least one connection element (153, 155) arranged on the first and second regions (157,154) of the first surface of the interconnection circuit (150);, the connection element (113) of at least one of the conductive tracks of the first region (115) of the first electronic chip (110) being in contact with the connection element (153) of at least one of the conductive tracks of the first region (157) of the interconnection circuit (150), the connection element (155) of at least one of the conductive tracks of the first region (134) of the second electronic chip (130) being in contact with the connection element (155) of at least one of the conductive tracks of the second region of the interconnection circuit (150).

4. Device according to claim 3, wherein: the first electronic chip (110) comprises one or more active or passive components (118) connected to the conductive tracks of the first electronic chip (110), the connection element of the conductive tracks of the first electronic chip (110) is surrounded at least in part by an insulator, the second electronic chip (130) comprises one or more active or passive components (138) connected to the conductive tracks of the second electronic chip (130), the connection element of the conductive tracks of the second electronic chip (130) is surrounded at least in part by an insulator, the interconnection circuit (150) comprises one or more active or passive components (158) connected to the conductive tracks of the interconnection circuit (150), and the connection element of the conductive tracks of the interconnection circuit (150) is surrounded at least in part by an insulator.

5. Device according to claim 4, in which the assembly by hybrid bonding of the first region (115) of the first surface of the first electronic chip (110) to the first region (157) of the first surface of the interconnection circuit (150) is carried out: between the connection element of at least one of the conductive tracks of the first region (113) of the first surface of the first electronic chip (110) and the connection element (153) of at least one of the conductive tracks of the first region of the first surface of the interconnection circuit (150), and / or between the insulator surrounding the connection element (113) of said at least one of the conductive tracks of the first region of the first surface of the first electronic chip (110) and the insulator surrounding the connection element (153) of said at least one of the conductive tracks of the first region of the first surface of the interconnection circuit (150); and wherein the hybrid bonding assembly of the first region of the second electronic chip (130) to the second region of the interconnection circuit (150) is carried out between the connection element (135) of at least one of the conductive tracks of the first region of the first surface of the second electronic chip (130) and the connection element (155) of at least one of the conductive tracks of the second region of the first surface of the interconnection circuit (150);and / or between the insulator surrounding the connection element (135) of said at least one of the conductive tracks of the first region of the first surface of the second electronic chip (130) and the insulator surrounding the connection element (155) of said at least one of the conductive tracks of the second region of the first surface of the interconnection circuit (150).;

6. A device according to any one of claims 1 or 3 to 5, wherein the interconnection circuit (150) has a thickness less than or equal to 100 micrometers.

7. A device according to any one of claims 1 or 3 to 6, wherein the first electronic chip (110) and the second electronic chip (130) are reverse chips.

8. Device according to claim 7, wherein the first surface (133) of the second electronic chip (130) further comprises a second region (136) which is not in contact with the interconnection circuit (150) and which comprises at least one connection pad (131) arranged at the first surface (133) of the second electronic chip (130).

9. Method according to claim 2 in which, prior to the hybrid bonding assembly step, the first and second electronic chips (130) are held fixed on a transfer substrate and, after the hybrid bonding assembly step, the first and second electronic chips (110, 130) are detached from said transfer substrate.

10. The method of claim 2 or 9, wherein the electronic device comprises a connection substrate (180) comprising one or more connection pads arranged at a surface contact (181) of the connection substrate (180), one or more electrical connection elements (119) connecting the connection pads (111) of the second region (114) of the first electronic chip (110) to the connection pads of the connection substrate (180) and in which, in a connection step, said at least one of the connection pads (111) of the second region of the first surface (116) of the first electronic chip (110) is brought into contact, by a thermal and / or mechanical treatment, with one end of one of the electrical connection elements (119), and said electrical connection element (119) is brought into contact, with said treatment with one of the connection pads of the connection substrate (180).

11. Method according to claim 10, wherein, in the connecting step, said at least one of the connection pads (111) of the second region (136) of the first surface (133) of the second electronic chip (130) is brought into contact, by a thermal and / or mechanical treatment, with one end of one of the electrical connection elements (119), and another end of said electrical connection element (119) is brought into contact, with said treatment, with another of the connection pads of the connection substrate (180).

12. Method according to claim 10 or 11, in which, prior to the connection step, the assembly formed by the first electronic chip (110), the second electronic chip (130) and the interconnection circuit (150) is returned so that the interconnection circuit (150) is on the side of the connection substrate (180) and so that the connection pads (111, 131) of the first and second electronic chips are oriented towards the connection substrate (180).

13. A device according to any one of claims 1 or 3 to 8, the device comprising a further interconnection circuit comprising a first planar surface and a third electronic chip; a first region of the third electronic chip being assembled by hybrid bonding to a first region of the first surface of the further interconnection circuit; the second region (114) of the first electronic chip being assembled by hybrid bonding to a second region of the first surface of the further interconnection circuit so that the first electronic chip (110) is electrically connected to the third electronic chip (130) through the other interconnection circuit.

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