Silicon-on-insulator type semiconductor device and corresponding manufacturing method

Abstract

The silicon-on-insulator semiconductor device comprises at least one NMOS transistor (TNM) in a P-type well (PW) of the carrier substrate (PSUB), at least one PMOS transistor (TPM) in an N-type well (NW) of the carrier substrate (PSUB, and a power supply circuit (ALM) configured to generate voltages (+V0, -V0) in the P-type and N-type wells, so as to selectively provide neutral back bias (NBB), forward bias (FBB) and reverse bias (RBB) conditions to the NMOS transistor and the PMOS transistor. The neutral back bias condition (NBB) comprises a first non-zero negative voltage (-V0) in the P-type well (PW) and a first non-zero positive voltage (+V0) in the N-type well (NW), the NMOS and PMOS transistors being configured to have nominal threshold voltages in the neutral back bias condition (NBB). Figure for abstract: Fig 1

Description

Title of the invention: Silicon-on-insulator type semiconductor device and corresponding manufacturing method

[0001] Embodiments and implementations relate to semiconductor devices of the silicon-on-insulator type, usually designated by the acronym "SOI" from the English terms "Silicon On Insulator", that is to say semiconductor devices made from a substrate of the SOI type comprising a carrier substrate, a buried dielectric layer, and a semiconductor film typically made of silicon which can be in a state completely depleted of minority carriers ("FDSOI" for "Fully Depleted SOI" in English).

[0002] SOI substrates allow in particular to benefit from a "back bias", that is to say a field effect in the semiconductor film through the buried dielectric layer, caused by a polarization of the carrier substrate. In practice, it is a doped well located in the carrier substrate which is locally polarized. The channel regions of MOS transistors (acronym for "Metal Oxide Semiconductor") produced in SOI technology are located in the semiconductor film, so that the back bias makes it possible to modify the behavior of the MOS transistors.

[0003] Typically, a negative sign back bias for a PMOS transistor and a positive sign back bias for an NMOS transistor, called forward back bias, makes it possible to lower the threshold voltage of the transistors and thus improve their performance, but increases current leakage; while a positive sign back bias for a PMOS transistor and a negative sign back bias for an NMOS transistor, called reverse back bias, makes it possible to increase the threshold voltage of the transistors and thus reduce current leakage, but deteriorates their performance.

[0004] On the other hand, the PMOS and NMOS transistors are typically produced in wells of the carrier substrate having a respective doping type, either in a “regular well” configuration in which the PMOS transistors are produced in an N-type well and the NMOS transistors in a P-type well (i.e. in the manner of MOS transistor production in a monolithic substrate, “bulk” in English); or in a “flip well” configuration in which the PMOS transistors are produced in a P-type well and the NMOS transistors in an N-type well (which is possible due to the buried dielectric layer of the SOI substrates).

[0005] Consequently, in the case of back bias, the potential difference between the The voltage of P-type and N-type wells is limited by the threshold voltage of the PN junction formed between the wells, so that the normal well configuration does not allow (or too little to be exploitable) forward reverse bias, and the inverted well configuration does not allow (or too little to be exploitable) reverse reverse bias.

[0006] The cointegration of normal wells with inverted wells is not advantageous, in particular in terms of surface occupation, because in this case, transistors of the same type (NMOS or PMOS) must be produced in separate and electrically isolated wells.

[0007] Techniques for electrically isolating N-type and P-type boxes using additional and deeper lateral isolation trenches than typical lateral isolation trenches allow for both forward and reverse back biasing but require additional manufacturing steps that are expensive and complex in the fabrication of the semiconductor device, and also require additional complexity in the circuit design.

[0008] Embodiments and implementations allow direct and reverse back biases to be used at values higher than the threshold voltage of the PN junction between the wells, both for NMOS transistors and PMOS transistors, the transistors of the same type (NMOS or PMOS) all being able to be cointegrated in the same well of the carrier substrate, and without generating complexities in the manufacturing and design of the circuit.

[0009] According to one aspect, there is provided in this regard a silicon-on-insulator type semiconductor device comprising at least one NMOS transistor in and on a semiconductor film separated from a P-type doped well arranged in a carrier substrate by a buried dielectric layer, at least one PMOS transistor in and on a semiconductor film separated from an N-type doped well arranged in the carrier substrate by the buried dielectric layer, and a power supply circuit configured to generate voltages in the P-type and N-type wells, so as to selectively provide neutral, forward and reverse back bias conditions to the NMOS transistor and the PMOS transistor, wherein the power supply circuit is configured to generate, under the neutral back bias condition, a first non-zero negative voltage in the P-type well and a first non-zero positive voltage in the N-type well,the NMOS and PMOS transistors being respectively configured to have nominal threshold voltages in the neutral back bias condition.,

[0010] In other words, it is proposed to produce the NMOS and PMOS transistors specifically configured to have nominal threshold voltages, i.e. the threshold voltages provided for normal operation of the circuit, in the condition particular neutral back bias where the transistor boxes are respectively negatively and positively biased.

[0011] Consequently, from the neutral back bias condition comprising a negative bias of the P-type well and a positive bias of the N-type well, it is possible to increase the voltage biasing the P-type well and simultaneously decrease the voltage biasing the N-type well, so as to produce an exploitable forward back bias, both for the NMOS and PMOS transistors, without exceeding the threshold voltage of the PN junction between the two wells.

[0012] According to one embodiment, the power supply circuit is in this regard configured to generate, in the forward reverse bias condition, a voltage greater than said first non-zero negative voltage in the P-type box and a voltage lower than said first non-zero positive voltage in the N-type box.

[0013] According to one embodiment, the power supply circuit is configured to generate, in the reverse back bias condition, a voltage lower than said first non-zero negative voltage in the P-type well and a voltage higher than said first non-zero positive voltage in the N-type well.

[0014] Indeed, from the same condition of neutral back bias comprising a negative bias of the P-type well and a positive bias of the N-type well, it is also possible to decrease the voltage biasing the P-type well and simultaneously increase the voltage biasing the N-type well, so as to produce an exploitable reverse back bias, both for the NMOS and PMOS transistors, without exceeding the threshold voltage of the PN junction between the two wells.

[0015] According to one embodiment, said at least one NMOS transistor comprises a tensionally stressed channel region, in the respective semiconductor film, and said at least one PMOS transistor comprises a compressionally stressed channel region, in the respective semiconductor film.

[0016] A tensile mechanical stress in one direction of a silicon crystal typically generates a compressive stress in a perpendicular direction of the material, and vice versa. By "a tensile / compressively stressed channel region" is meant that the given stress (tension or compression) is considered in the direction of the channel region, i.e. in the direction between the source and the drain of the transistor.

[0017] The tension constraints in the channel of an NMOS transistor and in compression in the channel of a PMOS transistor make it possible to improve the performance of the transistors, in particular in terms of carrier mobility. That being said, conventionally the use of mechanical constraints in the channels of the transistors presents difficulties insofar as they cause a reduction in the threshold voltage of the transistor and thus an increase in current leakage. However, the negative bias of the P-type well and the positive bias of the N-type well cause an increase in the threshold voltages of the respective transistors, thus making it possible to benefit from the advantages of mechanical constraints in the transistor channels without suffering the disadvantages.

[0018] According to one embodiment, said at least one PMOS transistor comprises a silicon-germanium alloy channel region, in the respective semiconductor film, with a germanium concentration greater than 25% in atomic percentage.

[0019] Similarly, the use of a channel region made of a silicon-germanium compound with a high dose of germanium makes it possible to improve the performance of PMOS transistors, but in return causes a reduction in the threshold voltage of the transistor. Here again, the positive bias of the N-type well causes an increase in the threshold voltage of the PMOS transistors, thus making it possible to benefit from the advantages of the silicon-germanium composition in the channels without suffering from its disadvantages.

[0020] According to one embodiment, the NMOS and PMOS transistors comprise a gate dielectric layer located between a gate conductive region and the respective semiconductor film, the gate dielectric layer comprising nitrogen so as to form a silicon oxynitride “SiON” layer.

[0021] The presence of nitrogen in silicon oxide makes it possible to increase the capacitance of the gate dielectric layer without reducing the physical thickness of the gate dielectric layer, which is advantageous in terms of performance, while maintaining constant tunnel leakage through the gate dielectric layer. However, the presence of nitrogen in the gate dielectric layer causes, in return, a reduction in the threshold voltage of the NMOS transistors and an increase in the threshold voltage of the PMOS transistors. However, given the particular configuration of the NMOS and PMOS transistors to have nominal threshold voltages in the particular condition of neutral back bias where the wells of the transistors are respectively negatively and positively biased, it is again possible to benefit from the advantages of silicon oxynitride in the gate dielectric layer without suffering from the disadvantages.

[0022] According to one embodiment, said NMOS and PMOS transistors comprise a conductive gate region comprising titanium nitride and a titanium nitride additive chosen from lanthanum and aluminum, so as to modulate the output work of the gate to obtain said nominal threshold voltages in the neutral back bias condition.

[0023] Lantana and aluminum allow to increase or decrease the threshold voltage PMOS and NMOS transistors, and thus advantageously allows said threshold voltages to be set to a nominal value suitable for normal use of the circuit in the aforementioned neutral back bias condition.

[0024] According to one embodiment, said NMOS and PMOS transistors comprise a respective channel region comprising a concentration of doping species adapted to modulate the output work of the channel region so as to obtain said nominal threshold voltages in the neutral back bias condition.

[0025] The dopings of the channel region, which can nevertheless remain intrinsic, i.e. have a zero concentration of doping species, again make it possible to adjust the threshold voltage of the PMOS and NMOS transistors to a nominal value adapted to the normal use of the circuit in the aforementioned neutral back bias condition.

[0026] According to one embodiment, the device comprises at least one CMOS circuit provided with the NMOS transistors and the PMOS transistor, the NMOS and PMOS transistors being configured to have nominal threshold voltages in the neutral back bias condition, in at least one of the following intervals: - an interval of so-called super low threshold voltages between 0.15 V and 0.25 V, in absolute values; - an interval of so-called low threshold voltages between 0.2 V and 0.3 V, in absolute values; - an interval of so-called lower median threshold voltages between 0.25 V and 0.35 V, in absolute values; - an interval of so-called upper median threshold voltages between 0.3 V and 0.4 V, in absolute values; - an interval of so-called high threshold voltages between 0.35 V and 0.45 V, in absolute values.

[0027] In particular, the device may comprise at least one CMOS circuit in two of the intervals of the above list, or at least one CMOS circuit in three of the intervals of the above list, or at least one CMOS circuit in four of the intervals of the above list, or at least one CMOS circuit in each interval of the above list.

[0028] According to another aspect, there is provided a method of manufacturing a silicon-on-insulator type semiconductor device comprising: - a formation of at least one NMOS transistor in and on a semiconductor film separated from a P-type doped well arranged in a carrier substrate by a buried dielectric layer, - a formation of at least one PMOS transistor in and on a semiconductor film separated from an N-type doped well arranged in the carrier substrate by the di- layer buried electrical, and - a formation of a power supply circuit capable of generating voltages in the P-type and N-type wells, so as to selectively provide neutral, forward and reverse back bias conditions to the NMOS transistor and the PMOS transistor, the neutral back bias condition comprising a first non-zero negative voltage applied in the P-type well and a first non-zero positive voltage applied in the N-type well, said formations of the NMOS and PMOS transistors being configured to provide the NMOS and PMOS transistors with respective nominal threshold voltages in the neutral back bias condition.

[0029] According to one embodiment, the forward reverse bias condition comprises a voltage greater than said first non-zero negative voltage applied in the P-type well and a voltage lower than said first non-zero positive voltage applied in the N-type well.

[0030] According to one embodiment, the reverse back bias condition comprises a voltage lower than said first non-zero negative voltage applied in the P-type well and a voltage higher than said first non-zero positive voltage applied in the N-type well.

[0031] According to one embodiment, the formation of said at least one NMOS transistor comprises a formation of a tensionally strained channel region in the respective semiconductor film, and the formation of said at least one PMOS transistor comprises a formation of a compressionally strained channel region in the respective semiconductor film.

[0032] According to one embodiment, the formation of said at least one PMOS transistor comprises the formation of a silicon-germanium alloy channel region in the respective semiconductor film, with a germanium concentration greater than 25% in atomic percentage.

[0033] According to one embodiment, the formations of said NMOS and PMOS transistors comprise a formation of a gate dielectric layer located between a gate conductive region and the respective semiconductor film, the gate dielectric layer comprising nitrogen so as to form a silicon oxynitride layer.

[0034] According to one embodiment, the formations of said NMOS and PMOS transistors comprise a formation of a conductive gate region comprising titanium nitride and a titanium nitride additive chosen from lanthanum and aluminum, so as to modulate the output work of the gate to obtain said nominal threshold voltages in the neutral back bias condition.

[0035] According to one embodiment, the formations of said NMOS and PMOS transistors comprise a formation of a respective channel region comprising a concentration of doping species modulating the work function of the channel region in a suitable manner to obtain said nominal threshold voltages in the neutral back bias condition.

[0036] According to one embodiment, the method comprises forming at least one CMOS circuit provided with the NMOS transistors and the PMOS transistor, configured to provide the NMOS and PMOS transistors with nominal threshold voltages in the neutral back bias condition, in at least one of the following intervals: - an interval of so-called super low threshold voltages between 0.15 V and 0.25 V, in absolute values; - an interval of so-called low threshold voltages between 0.2 V and 0.3 V, in absolute values; - an interval of so-called lower median threshold voltages between 0.25 V and 0.35 V, in absolute values; - an interval of so-called upper median threshold voltages between 0.3 V and 0.4 V, in absolute values; - an interval of so-called high threshold voltages between 0.35 V and 0.45 V, in absolute values.

[0037] Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments and implementations, which are in no way limiting, and the appended drawings, in which:

[0038] [Fig.l] ;

[0039] [Fig.2] ;

[0040] [Fig.3] ;

[0041] [Fig.4] ;

[0042] [Fig.5] ;

[0043] [Fig.6] ;

[0044] [Fig.7] illustrate embodiments and implementations of the invention.

[0045] [Fig. 1] illustrates an exemplary embodiment of a DSOI semiconductor device of the silicon-on-insulator type comprising at least one NMOS transistor (acronym well known to those skilled in the art for the English terms “N-type Metal Oxide Semiconductor”) TNM and at least one PMOS transistor (acronym well known to those skilled in the art for the English terms “P-type Metal Oxide Semiconductor”) TPM.

[0046] In silicon-on-insulator technologies, the active region of the MOS transistors is located in a semiconductor film located on a buried dielectric, insulating the semiconductor film from a carrier substrate. The MOS transistors are thus formed in and on the semiconductor film, that is to say in particular that their conduction regions (the source and the drain) are implanted in the semiconductor film, and that their control regions (the gate) are formed on the open surface, called the face before, of the semiconductor film.

[0047] The NMOS transistor TNM is produced in and on a semiconductor film FLMn separated from a P-type doped PW well by the buried dielectric layer BOX, the PW well being arranged in the carrier substrate PSUB.

[0048] The PMOS transistor TPM is produced in and on a semiconductor film FLMp separated from an N-type doped NW box by the buried dielectric layer BOX, the NW box being arranged in the carrier substrate PSUB.

[0049] Advantageously from the point of view of carrier mobility in the channel regions of the TNM, TPM transistors, the FLMn semiconductor film of the NMOS transistor can be strain-strained in the direction of the channel region of the NMOS transistor.

[0050] The tensile stress can be obtained by means of conventional techniques, for example with a tensile nitride layer encapsulating the gate; or by using a pre-stressed SOI substrate; or by locally introducing a tensile stress in the channel by other techniques, such as “BOX creep” (use of a temperature rise of a sacrificial layer having a thermal expansion coefficient different from that of the channel region), or “STRASS” (acronym for the English terms “Strain by Top Recrystallization of Amorphized SiGe on SOI”, formation of stress by surface recrystallization of an amorphous material).

[0051] The channel region of the NMOS transistor is adapted to be formed in the region of the FLMn semiconductor film between the N+ conduction terminals of the NMOS transistor, under the NG gate region.

[0052] Furthermore, the FLMn semiconductor film can be formed from intrinsic silicon, or from P-type doped silicon with a greater or lesser concentration of doping species.

[0053] Similarly, the FLMp semiconductor film of the PMOS transistor can advantageously be compressed in the direction of the channel region of the PMOS transistor, the channel region of the PMOS transistor being adapted to form in the region of the FLMp semiconductor film between the P+ conduction terminals of the PMOS transistor, under the PG gate region. The FLMp semiconductor film can advantageously be formed from a silicon-germanium composition SiGe30%, with a germanium concentration greater than 25% in atomic percentage, for example 30%, which can also be intrinsic or N-type doped with a greater or lesser concentration of doping species.

[0054] The gate regions NG, PG of the transistors TNM, TPM typically comprise a conductive layer and a gate dielectric layer located between the conductive layer and the respective semiconductor film FLMn, FLMp. Typically, the conductive layer comprises a part made of metal or a metal compound, for example titanium nitride, located on the side of the channel region, for example on the di layer electric grid, and a polycrystalline silicon part used to electrically contact the grid.

[0055] Advantageously, the gate dielectric layer comprises a layer of silicon oxynitride (“SiON”, or SiOxNy, for example Si2O2N with x=1, y=0.5), for example in a two-layer structure comprising a high permittivity (usually “high-k”) dielectric layer, such as hafnium oxide HfO2, and the layer of silicon oxynitride SiON. The presence of the silicon oxynitride makes it possible to increase the capacitance of the gate dielectric region and thus to improve the performance of the transistor, compared to a conventional layer of silicon dioxide. Indeed, a greater capacitance of the gate dielectric causes an increase in the number of carriers in the channel for a given voltage, which allows conduction of a greater quantity of current. The concentration of nitrogen in the silicon oxynitride SiON also makes it possible to modulate the threshold voltage of the NMOS and PMOS transistors.

[0056] The different characteristics of the NMOS and PMOS transistors described above are provided on the one hand in order to configure the NMOS and PMOS transistors to have respective nominal threshold voltages VTnom ([Fig.3]) in the neutral back bias condition NBB ([Fig.2]) described below; and on the other hand simultaneously in order to benefit from the aforementioned techniques for improving the performance of the NMOS and PMOS transistors.

[0057] The DSOI semiconductor device in fact comprises an ALM power supply circuit configured to generate voltages +V0, -Vo in the P-type PW well and the N-type NW well, so as to selectively provide neutral NBB, forward FBB and reverse RBB ([Fig.2]) reverse bias conditions to the NMOS transistor and the PMOS transistor.

[0058] The neutral back bias condition NBB is characterized by a generation of a first non-zero negative voltage -Vo, for example substantially - IV (volt), in the P-type PW well housing the NMOS transistor; as well as a first non-zero positive voltage +V0, for example substantially +1 V, in the N-type NW well housing the PMOS transistor.

[0059] In this regard, the P-type PW well comprises a contact region P+ capable of receiving the first negative voltage -Vo and the N-type NW well comprises a contact region N+ capable of receiving the first positive voltage +V0. The DSOI device may further comprise an N-type NISO isolation well, preventing the polarization of the carrier substrate PSUB at the voltages -Vo or +V0 applied in the PW or NW wells, due to the two opposite PN junctions, JPNiso and JNPiso. Lateral isolation structures STI, for example shallow isolation trenches, are typically provided to provide local electrical isolation between the elements of the PW, NW wells, and in particular to form access to the respective PW, NW boxes via the P+, N+ contact sockets.

[0060] Thus, since the NMOS and PMOS transistors are specifically configured to have a nominal threshold voltage, and therefore a nominal behavior, in the neutral back bias condition "-Vo; +V0" (i.e. the threshold voltages and behavior intended for normal operation of the circuit), it is advantageously possible to produce exploitable forward FBB and reverse RBB back biases, for both the NMOS and PMOS transistors, without exceeding the threshold voltage of the PN junction between the two wells.

[0061] In this regard, reference is made to [Fig.2].

[0062] [Fig.2] illustrates the neutral back bias condition NBB, the forward back bias condition FBB and the reverse back bias condition RBB, in the PW, NW wells of the DSOI semiconductor device described in relation to [Fig.l].

[0063] It is recalled that the ALM power supply circuit is configured to generate a first non-zero negative voltage -Vo, for example substantially - IV or even -1.5 V, in the PW well housing the NMOS transistor, as well as a first non-zero positive voltage +V0, for example substantially +1 V or even +1.5 V, in the NW well housing the PMOS transistor, in the neutral rear bias condition NBB.

[0064] In the NBB neutral back bias condition, the JPN junction (and the JPNiso junction) between the PW and NW wells (respectively NISO) is biased at a forward voltage of -2 V or even -3 V and is therefore blocked. Similarly, the JNPiso junction between the NISO well and the PSUB substrate is biased at a forward voltage of -1 V or even -1.5 V (considering that the potential of the PSUB carrier substrate is at 0 V), and is therefore blocked.

[0065] The ALM power supply circuit is further configured to generate, in the forward reverse bias condition FBB, a voltage -V0+Af greater than the first non-zero negative voltage -Vo in the PW well, for example a voltage of substantially 0 V, i.e. greater "+Af" by substantially +1 V or even +1.5 V; as well as a voltage +V0-Af lower than said first non-zero positive voltage +V0 in the NW well, for example a voltage of substantially 0 V, i.e. lower "-Af" by substantially - IV or even -1.5 V.

[0066] In the forward reverse bias condition FBB, the junctions JPN, JPNiso, JNPiso between the wells PW, NW, NISO, PSUB are biased to forward voltages of 0 V and are therefore blocked.

[0067] The ALM power supply circuit is further configured to generate, in the reverse reverse bias condition RBB, a voltage -V0-Ar lower than said first non-zero negative voltage -Vo in the PW well, for example a voltage of substantially -2 V or even -3 V, i.e. lower than "-Ar" by substantially -1 V or -1.5 V; and a voltage +Vo+Ar greater than said first non-zero positive voltage +V0 in the NW box, for example a voltage of substantially +2 V or even +3 V, i.e. greater than “+Ar” by substantially +1 V or even +1.5 V.

[0068] In the reverse RBB back bias condition, the JPN junction (and the JPNiso junction) between the PW and NW wells (respectively between the PW and NISO wells) is biased at a forward voltage of -4 V or even -6 V and is therefore blocked. Similarly, the JNPiso junction between the NISO well and the PSUB substrate is biased at a forward voltage of -2 V or even -3 V (considering that the potential of the PSUB carrier substrate is at 0 V), and is therefore blocked.

[0069] [Fig.3] illustrates a graph of possible applications for implementing neutral, forward and reverse back bias conditions.

[0070] Indeed, the back bias conditions can advantageously make it possible to compensate for a random drift in the effective threshold voltages of the NMOS and PMOS transistors, typically due to the physical hazards of the manufacturing processes.

[0071] Thus, the horizontal axis of the graph represents the random variations of the characteristics of the NMOS transistors, going from left to right from a “slow” behavior N_SLW, i.e. a larger threshold voltage (in absolute value), towards a “fast” behavior N_FST, i.e. a smaller threshold voltage (in absolute value).

[0072] The vertical axis of the graph represents the random variations of the characteristics of the PMOS transistors, going from bottom to top from a “slow” behavior P_SLW, i.e. a larger threshold voltage (in absolute value), to a “fast” behavior P_FST, i.e. a smaller threshold voltage (in absolute value).

[0073] The coordinates of significant points are represented on the graph, SS, TS, FS, TT, ST, SF, FF, the left letter of the coordinates signifying the behavior of the NMOS transistor, the right letter signifying the behavior of the PMOS transistor, with "S" for "slow" behavior, "T" for "normal" behavior and "F" for "fast" behavior.

[0074] The ellipse VTeff in the diagonal SS, TT, FF represents the dispersion in practice of the threshold voltages of a statistical population of pairs of NMOS and PMOS transistors.

[0075] Thus, in the most common symmetrical case, that is to say when the PMOS and NMOS transistors have a drift in the same direction, substantially along the diagonal SS, TT, FF, a direct back bias FBB or a reverse back bias RBB, will make it possible to bring the effective threshold values back to the nominal value VTnom, towards the point TT.

[0076] In the symmetrical case, the direct FBB or reverse RBB back biases are applied in the two PW, NW boxes as shown in [Fig.2], with va- nations “+ / -Ar”, “+ / -Af” whose amplitude corresponds to the difference between the effective threshold voltage SS, FF and the nominal threshold voltage Vnom, at point TT, for example (Vo+O.5V; Vo-O.5V) and (Vo-O.5V; Vo+O.5V).

[0077] That being said, the DSOI semiconductor device described previously in relation to [Fig.l] also makes it possible to compensate for an asymmetric drift of the NMOS and PMOS transistor characteristics, i.e. when the PMOS and NMOS transistors have different or opposite drifts.

[0078] Indeed, in this respect, it will be possible, for example, to provide a direct rear polarization to one of the two PW, NW boxes and a reverse rear polarization to the other of the two NW, PW boxes.

[0079] For example, it will be possible to provide a direct back bias to the PW box and a reverse back bias to the NW box, "FBB / RBB" in order to compensate for the drift of the SF case, with variations "+Af", "+Ar" of adapted amplitude, for example (Vo +0.5V; V0+0.5V). Conversely, it will be possible to provide a reverse back bias to the PW box and a direct back bias to the NW box, "RBB / FBB" in order to compensate for the drift of the FS case, with variations "-Ar", "-Af" of adapted amplitude, for example (V0-0.5V; V0-0.5V).

[0080] Furthermore, it will also be possible, for example, to provide a direct or reverse rear bias to one of the two PW, NW boxes and the neutral rear bias to the other of the two NW, PW boxes.

[0081] For example, it will be possible to provide a direct rear bias to the PW box and a neutral rear bias to the NW box, "FBB / NBB" in order to compensate for the drift of the ST case, with a variation "+Af" of adapted amplitude, for example (V0+0.5V; Vo ). Conversely, it will be possible to provide a reverse rear bias to the PW box and a neutral rear bias to the NW box, "NBB / FBB" in order to compensate for the drift of the TS case, with a variation "-Af" of adapted amplitude (for example Vo; Vo -0.5V).

[0082] In fact, all cases of drift can be compensated with suitable amplitude variations. That being said, in particular the direct back bias FBB is limited to substantially (0V, 0V) because of the PN junction threshold between the PW, NW wells. On the other hand and in particular, the reverse back bias RBB in the two PW, NW wells and the asymmetric back biases FBB / RBB and RBB / FBB are not limited in amplitude nlmtd (to an extent lower than the reverse breakdown voltage of the PN junctions).

[0083] [Fig. 4] illustrates examples of advantageous embodiments of the DSOI semiconductor device, comprising CMOS circuits (acronym well known to those skilled in the art for the English terms “Complementary Metal Oxide Semiconductor”) each provided with at least one NMOS transistor TNM and at least one PMOS transistor TPM as previously described in connection with Figures 1 to 3.

[0084] In these examples, the NMOS transistors and the PMOS transistors may advantageously be configured to have respective nominal threshold voltages at different values in the NBB neutral back bias condition, for each respective CMOS circuit SLVT, LVT, iRVT, R VT, HVT.

[0085] [Fig.5] illustrates a graph of the threshold voltage pairs for the respective CMOS circuits SLVT, LVT, iRVT, RVT, HVT.

[0086] The NMOS and PMOS transistors can be configured to have threshold voltages in a range of so-called super low threshold voltages SLVT, between 0.15 V and 0.25 V, in absolute values, for example 0.24 V for the NMOS transistor and 0.17 V for the PMOS transistor.

[0087] The NMOS and PMOS transistors can be configured to have threshold voltages in a range of so-called low threshold voltages LVT, between 0.2 V and 0.3 V, in absolute values, for example 0.28 V for the NMOS transistor and 0.22 V for the PMOS transistor.

[0088] The NMOS and PMOS transistors may be configured to have threshold voltages in a range of so-called lower median threshold voltages iRVT, between 0.25 V and 0.35 V, in absolute values, for example 0.34 V for the NMOS transistor and 0.27 V for the PMOS transistor.

[0089] The NMOS and PMOS transistors can be configured to have threshold voltages in a range of so-called upper median threshold voltages RVT, between 0.3 V and 0.4 V, in absolute values, for example 0.39 V for the NMOS transistor and 0.32 V for the PMOS transistor.

[0090] The NMOS and PMOS transistors can be configured to have threshold voltages in a range of so-called high threshold voltages HVT, between 0.35 V and 0.45 V, in absolute values, for example 0.43 V for the NMOS transistor and 0.37 V for the PMOS transistor.

[0091] All threshold voltage values presented above in relation to [Fig.5] are given as examples and can be considered to within 10%.

[0092] We refer again to [Fig.4].

[0093] On the one hand, the different threshold voltages SLVT, LVT, iRVT, RVT, HVT of the transistors of the CMOS circuits can be parameterized by modulating the output work of the gate regions NG, PG, in particular by introducing an additive into the metallic part, made of titanium nitride, of the gate. For example, lanthanum is an additive making it possible to lower the output work of the gate NG, in this case called “N-type output work” without designating a type of doping. For example, aluminum is an additive making it possible to increase the output work of the gate PG, in this case called “P-type output work” without designating a type of doping.

[0094] On the other hand, the different threshold voltages SLVT, LVT, iRVT, RVT, HVT of the transistors of the CMOS circuits can be parameterized by modulating the output work of the channel regions, in particular by doping the respective semiconductor films FLMn, FLMp, at a concentration of doping species which can be zero iSi, iSiGe (intrinsic semiconductor material) or at different concentrations ChlI, ChII2 (for example two levels of dopant concentrations).

[0095] Furthermore, all the NMOS transistors of the CMOS circuits of the DSOI semiconductor device can be made in the same P-type PW well, and biased according to the same neutral (-1V) or forward or reverse back bias condition. Similarly, all the PMOS transistors of the CMOS circuits of the DSOI semiconductor device can be made in the same N-type NW well, and biased according to the same neutral (+1V) or forward or reverse back bias condition.

[0096] Furthermore, the DSOI semiconductor device may advantageously comprise an ultra-low leakage uHVT CMOS circuit (also called “ultra-high threshold voltage”), and a CMOS circuit of static random access memory cells “SRAM” (acronym well known to those skilled in the art for the English terms “Static Random Access Memory”), according to the same manufacturing process steps as the other CMOS circuits (in this regard, reference will be made to FIGS. 6 and 7 described below). The two NMOS and PMOS types of uHVT and SRAM transistors are located in a P-type doped PW semiconductor well, arranged in the carrier substrate PSUB. Consequently, the uHVT and SRAM transistors, in particular the PMOS transistors, are not suitable for being produced in the same PW, NW well as the transistors of the same type of the CMOS circuits.

[0097] [Fig. 6] illustrates steps of a manufacturing method 600 of the NMOS transistors described previously in relation to FIGS. 4 and 5. More particularly, steps 610, 620, 631, 632, 641, 642 of [Fig. 6] represent the modifications made to a manufacturing of a conventional NMOS transistor NMOS_lgcy to obtain the TNM transistors described previously in relation to FIGS. 4 and 5, i.e. the NMOS transistors configured to have the different nominal threshold voltages SLVT, LVT, iRVT, RVT, HVT in the neutral back bias condition NB B.

[0098] The conventional NMOS_lgcy transistor, considered as the starting point in step 601, is produced in an N-type well arranged in the carrier substrate, comprises an intrinsic silicon channel region, and has for example a threshold voltage of substantially 0.34V. All the structural characteristics of the conventional NMOS_lgcy transistor which are not modified in the method 600, such as in particular the channel length, the implantations of the N+ conduction regions, and others, are identical in the obtained NMOS transistors.

[0099] Step 610 comprises a replacement of the well arranged in the carrier substrate, conventionally doped with N type, by a PW well doped with P type, and a neutral back bias at the non-zero negative voltage -Vo. Step 610 has the effect of increasing the threshold voltage of the NMOS transistor by substantially +0.1 V.

[0100] Step 620 comprises forming the gate dielectric layer comprising a silicon oxynitride region Ndose, and forming a voltage-strained channel region STRN in the semiconductor film FLMn of the NMOS transistor. Step 620 has the effect of decreasing the threshold voltage of the NMOS transistor by substantially -0.1 V.

[0101] Step 631 comprises forming a gate conductive region NG having an N-type output function, comprising titanium nitride and lantan as an additive to the titanium nitride. Step 631 has the effect of decreasing the threshold voltage of the NMOS transistor by substantially -0.1 V. At the end of step 631, it was possible to obtain the NMOS transistor having the “super low” threshold voltage SLVT.

[0102] Step 632 comprises forming a gate conductive region PG having a P-type output function, comprising titanium nitride and aluminum as an additive to the titanium nitride. Step 632 has the effect of increasing the threshold voltage of the NMOS transistor by substantially +0.05 V. At the end of step 632, it was possible to obtain the NMOS transistor having the “upper median” threshold voltage RVT.

[0103] Step 641 comprises a first implantation of ChlI dopants in the FLMn semiconductor film of the NMOS transistor, so as to form a channel region having a first concentration of ChlI dopant species. Step 641 has the effect of increasing the threshold voltage of the NMOS transistor by substantially +0.05 V. At the end of step 641 combined with step 631, it was possible to obtain the NMOS transistor having the “low” threshold voltage LVT. At the end of step 641 combined with step 632, it was possible to obtain the NMOS transistor having the “high” threshold voltage HVT and / or the NMOS transistor of the SRAM cells.

[0104] Step 642 comprises a second implantation of ChII2 dopants in the FLMn semiconductor film of the NMOS transistor, so as to form a channel region having a second concentration of ChII2 dopant species, higher than the first concentration of ChlI dopant species. Step 642 has the effect of increasing the threshold voltage of the NMOS transistor by substantially +0.1 V. At the end of step 642 combined with step 631, it was possible to obtain the NMOS transistor having the “lower median” threshold voltage iRVT. At the end of step 641 combined with step 632, it was possible to obtain the NMOS transistor having the “ultra high” threshold voltage uHVT and / or the NMOS transistor of the SRAM cells.

[0105] [Fig.7] illustrates steps of a manufacturing method 700 of the PMOS transistors described previously in relation to FIGS. 4 and 5. More particularly, steps 710, 720, 731, 732, 741, 742 of [Fig.7] represent the modifications made to a manufacturing of a conventional PMOS transistor PMOS_lgcy to obtain the TPM transistors described previously in relation to FIGS. 4 and 5, i.e. the PMOS transistors configured to have the different nominal threshold voltages SLVT, LVT, iRVT, RVT, HVT in the neutral back bias condition NBB.

[0106] The conventional PMOS_lgcy transistor, considered as a starting point in step 701, is produced in a P-type well arranged in the carrier substrate, comprises a channel region made of silicon-germanium alloy with a germanium concentration of between 18% and 20%, in atomic percentage, and has for example a threshold voltage of substantially 0.22 V. All the structural characteristics of the conventional PMOS_lgcy transistor which are not modified in the method 700, such as in particular the channel length, the implantations of the P+ conduction regions, and others, are identical in the PMOS transistors obtained.

[0107] Step 710 comprises a replacement of the well arranged in the carrier substrate, conventionally doped P-type, by an NW well doped N-type, and a neutral back bias at the non-zero positive voltage +V0. Step 710 has the effect of increasing the threshold voltage of the PMOS transistor by substantially +0.15 V.

[0108] Step 720 comprises a formation of the gate dielectric layer comprising a silicon oxynitride region Ndose, and a formation of a channel region made of silicon-germanium alloy SiGe30%, with a germanium concentration greater than 25% in atomic percentage, for example 30%, and further a compressive stress CMPR in the semiconductor film FLMp of the PMOS transistor. Step 720 has the effect of decreasing the threshold voltage of the PMOS transistor by substantially -0.15 V.

[0109] Step 731 comprises forming a gate conductive region NG having an N-type output function, comprising titanium nitride and lanthanum as an additive to the titanium nitride. Step 731 has the effect of increasing the threshold voltage of the PMOS transistor by substantially +0.1 V. At the end of step 731, it was possible to obtain the PMOS transistor having the “upper median” threshold voltage RVT.

[0110] Step 732 comprises forming a gate conductive region PG having a P-type output function, comprising titanium nitride and aluminum as an additive to the titanium nitride. Step 732 has the effect of decreasing the threshold voltage of the PMOS transistor by substantially -0.05 V. At the end of step 732, it was possible to obtain the PMOS transistor having the “super low” threshold voltage SLVT.

[0111] Step 741 comprises a first implantation of ChlI dopants in the semi-transparent film. FLMp conductor of the PMOS transistor, so as to form a channel region having a first concentration of ChlI dopant species. Step 741 has the effect of increasing the threshold voltage of the NMOS transistor by substantially +0.05 V. At the end of step 741 combined with step 731, it was possible to obtain the PMOS transistor having the “high” threshold voltage HVT. At the end of step 741 combined with step 732, it was possible to obtain the PMOS transistor having the “low” threshold voltage LVT.

[0112] Step 742 comprises a second implantation of ChII2 dopants in the FLMp semiconductor film of the PMOS transistor, so as to form a channel region having a second concentration of ChII2 dopant species, higher than the first concentration of ChlI dopant species. Step 742 has the effect of increasing the threshold voltage of the PMOS transistor by substantially +0.1 V. At the end of step 742 combined with step 732, it was possible to obtain the PMOS transistor having the “lower median” threshold voltage iRVT.

[0113] At the same time, it will be possible to manufacture PMOS transistors with “ultra high” threshold voltage uHVT, and PMOS transistors for SRAM memory cells, from the classic PMOS_lgcy transistor, considered as the starting point in step 701.

[0114] In step 751, the well arranged in the P-type doped carrier substrate is not replaced, and a neutral back bias is applied to the non-zero negative voltage -Vo. Step 751 has the effect of reducing the threshold voltage of the PMOS transistor by substantially -0.08 V.

[0115] Step 752 includes forming the gate dielectric layer including a silicon oxynitride region Ndose, replacing the channel region (i.e., the FLMp semiconductor film, initially made of silicon-germanium with a germanium concentration of between 18% and 20%, in atomic percentage) with an intrinsic silicon channel region Si, and compressive stress CMPR in the FLMp semiconductor film of the PMOS transistor. Step 720 has the effect of increasing the threshold voltage of the PMOS transistor by substantially +0.25 V.

[0116] Step 732 as described above is carried out at the end of step 752, and makes it possible to obtain the PMOS transistor suitable for SRAM memory cells.

[0117] Step 742 as described above is further performed at the end of step 732 (combined with step 752), and makes it possible to obtain the PMOS transistor with “ultra high” threshold voltage uHVT.

[0118] All the values of increase and decrease of the threshold voltages given above in relation to figures 6 and 7 are arbitrary values nevertheless corresponding to the order of magnitude of the effects actually obtained in practice.

Claims

Claims

1. A silicon-on-insulator type semiconductor device comprising - at least one NMOS transistor (TNM) in and on a semiconductor film (FLMn) separated from a P-type doped well (PW) arranged in a carrier substrate (PSUB) by a buried dielectric layer (BOX), - at least one PMOS transistor (TPM) in and on a semiconductor film (FLMp) separated from an N-type doped well (NW) arranged in the carrier substrate (PSUB) by the buried dielectric layer (BOX), and - a power supply circuit (ALM) configured to generate voltages (+V0, -Vo) in the P-type and N-type wells, so as to selectively provide neutral back bias (NBB), forward bias (FBB) and reverse bias (RBB) conditions to the NMOS transistor and the PMOS transistor, wherein the power supply circuit is configured to generate, in the neutral back bias condition (NBB),a first non-zero negative voltage (-Vo) in the P-type well (PW) and a first non-zero positive voltage (+V0) in the N-type well (NW), the NMOS and PMOS transistors being respectively configured to have nominal threshold voltages in the neutral back bias (NBB) condition.,

2. Device according to claim 1, wherein the power supply circuit (ALM) is configured to generate, in the forward reverse bias condition (FBB), a voltage higher (-V0+Af) than said first non-zero negative voltage (-Vo) in the P-type well (PW) and a voltage lower (+V0-Af) than said first non-zero positive voltage (+V0) in the N-type well (NW).

3. Device according to one of claims 1 or 2, wherein the power supply circuit (ALM) is configured to generate, in the reverse back bias condition (RBB), a lower voltage (-V0-Ar) than said first non-zero negative voltage (-Vo) in the P-type box (PW) and a higher voltage (+V0+Ar) than said first non-zero positive voltage (+V0) in the N-type box (NW).

4. Device according to one of the preceding claims, wherein said at least one NMOS transistor comprises a voltage-stressed channel region (STRN), in the respective semiconductor film (FLMn), and said at least one PMOS transistor comprises a channel region compressive stress (CMPR), in the respective semiconductor film (FLMp).

5. Device according to one of the preceding claims, wherein said at least one PMOS transistor comprises a channel region of silicon-germanium alloy (SiGe30%), in the respective semiconductor film (FLMp), with a germanium concentration greater than 25% in atomic percentage.

6. Device according to one of the preceding claims, in which the NMOS and PMOS transistors comprise a gate dielectric layer located between a gate conductive region (NG, PG) and the respective semiconductor film (FLMn, FLMp), the gate dielectric layer comprising nitrogen so as to form a layer of silicon oxynitride SiON (Ndose).

7. Device according to one of the preceding claims, wherein said NMOS and PMOS transistors comprise a gate conductive region (NG, PG) comprising titanium nitride and a titanium nitride additive chosen from lanthanum and aluminum, so as to modulate the output work of the gate to obtain said nominal threshold voltages in the neutral back bias (NBB) condition.

8. Device according to one of the preceding claims, wherein said NMOS and PMOS transistors (TNM, TPM) comprise a respective channel region comprising a concentration of doping species adapted to modulate the output work of the channel region so as to obtain said nominal threshold voltages in the neutral back bias (NBB) condition.

9. Device according to one of the preceding claims, comprising at least one CMOS circuit provided with the NMOS transistors (TNM) and the PMOS transistor (TPM), configured to have nominal threshold voltages (SLVT, LVT, iRVT, RVT, HVT) in the neutral back bias condition, in at least one of the following ranges: - an interval of so-called super low threshold voltages (SLVT) between 0.15 V and 0.25 V, in absolute values; - an interval of so-called low threshold voltages (LVT) between 0.2 V and 0.3 V, in absolute values; - an interval of so-called lower median threshold voltages (iRVT) between 0.25 V and 0.35 V, in absolute values; - an interval of so-called upper median threshold voltages (RVT) between 0.3 V and 0.4 V, in absolute values; - an interval of so-called high threshold voltages (HVT) between 0.35 V and 0.45 V, in absolute values.

10. A method of manufacturing a silicon-on-insulator type semiconductor device comprising: - a formation (600) of at least one NMOS transistor (TNM) in and on a semiconductor film (FLMn) separated from a P-type doped well (PW) arranged in a carrier substrate (PSUB) by a buried dielectric layer (BOX), - a formation (700) of at least one PMOS transistor (TPM) in and on a semiconductor film (FLMp) separated from an N-type doped well (NW) arranged in the carrier substrate (PSUB) by the buried dielectric layer (BOX), and - a formation of a power supply circuit (ALM) capable of generating voltages (+V0, -Vo) in the P-type and N-type wells, so as to selectively provide neutral (NBB), forward (FBB) and reverse (RBB) back bias conditions to the NMOS transistor and the PMOS transistor,the neutral back bias (NBB) condition comprising a first non-zero negative voltage (-Vo) applied in the P-type well (PW) and a first non-zero positive voltage (+V0) applied in the N-type well (NW), said formations of the NMOS and PMOS transistors (600, 700) being configured to provide the NMOS and PMOS transistors with respective nominal threshold voltages in the neutral back bias (NBB) condition.,

11. The method of claim 10, wherein the forward back bias (FBB) condition comprises a voltage (-V0+Af) higher than said first non-zero negative voltage (-Vo) applied in the P-type well (PW) and a voltage (+V0-Af) lower than said first non-zero positive voltage (+V0) applied in the N-type well (NW).

12. Method according to one of claims 10 or 11, wherein the reverse back bias condition (RBB) comprises a lower voltage (-V0-Ar) than said first non-zero negative voltage (-Vo) applied in the P-type well (PW) and a higher voltage (+V0 +Ar) than said first non-zero positive voltage (+V0) applied in the N-type well (NW).

13. A method according to one of claims 10 to 12, wherein the formation of said at least one NMOS transistor (600) comprises a formation (620) of a tensile strained channel region (STRN) in the respective semiconductor film (FLMn), and forming said at least one PMOS transistor (700) comprises forming a compressive strained channel region (CMPR) (720) in the respective semiconductor film (FLMp).

14. Method according to one of claims 10 to 13, wherein the formation of said at least one PMOS transistor (700) comprises forming a channel region (720) of silicon-germanium alloy (SiGe30%) in the respective semiconductor film (FLMp), with a germanium concentration greater than 25% in atomic percentage.

15. Method according to one of claims 10 to 14, wherein the formations of said NMOS and PMOS transistors (600, 700) comprise a formation of a gate dielectric layer (620, 720) located between a gate conductive region (NG, PG) and the respective semiconductor film (FLMn, FLMp), the gate dielectric layer comprising nitrogen so as to form a silicon oxynitride SiON layer (Ndose).

16. A method according to one of claims 10 to 15, wherein the formations of said NMOS and PMOS transistors (600, 700) comprise a formation of a gate conductive region (NG, PG) comprising titanium nitride and a titanium nitride additive selected from lanthanum (631, 731) and aluminum (632, 732), so as to modulate the gate output work to obtain said nominal threshold voltages in the neutral back bias (NBB) condition.

17. A method according to one of claims 10 to 16, the formations of said NMOS and PMOS transistors (600, 700) comprise a formation of a respective channel region (641, 642, 741, 742) comprising a concentration of dopant species modulating the work function of the channel region in a manner suitable for obtaining said nominal threshold voltages in the neutral back bias (NBB) condition.

18. Method according to one of claims 10 to 17, comprising a formation of at least one CMOS circuit provided with the NMOS transistors (TNM) and the PMOS transistor (TPM), configured to provide the NMOS and PMOS transistors with nominal threshold voltages (SLVT, LVT, iRVT, RVT, HVT) in the neutral back bias condition (NBB), in at least one of the following intervals: - an interval of so-called super low threshold voltages (SLVT) between 0.15 V and 0.25 V, in absolute values; - an interval of so-called low threshold voltages (LVT) between 0.2 V and 0.3 V, in absolute values; - an interval of so-called lower median threshold voltages (iRVT) between 0.25 V and 0.35 V, in absolute values; - an interval of so-called upper median threshold voltages (RVT) between 0.3 V and 0.4 V, in absolute values; - an interval of so-called high threshold voltages (HVT) between 0.35 V and 0.45 V, in absolute values.

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