SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURED BY A SEMICONDUCTOR APPARATUS
By forming interconnect holes with a specific ratio and using an insulating layer with low solder wettability, the semiconductor device prevents solder intrusion, improving manufacturing efficiency and yield.
Patent Information
- Application Number
- FR2023009948
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2022-09-20
- Filing Date
- 2023-09-20
- Publication Date
- 2025-12-26
- Estimated Expiration
- 2043-09-20
AI Technical Summary
The integration of a semiconductor device with a housing substrate can degrade manufacturing yield due to deformation or separation of brazing on the back-side electrode, caused by solder entering the interconnect hole during assembly.
Forming an interconnect hole with a thickness-to-width ratio greater than 1 and using an insulating layer with low solder wettability to prevent solder from entering the hole, creating a void and maintaining electrical connectivity.
Prevents solder intrusion into the interconnect hole, enhancing manufacturing efficiency and yield by maintaining electrode integrity.
Smart Images
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Abstract
Description
Title of the invention: SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURED BY A SEMICONDUCTOR APPARATUS Domain
[0001] The embodiments described herein generally relate to a semiconductor device and a method for manufacturing a semiconductor device. Background
[0002] In a semiconductor device in which a semiconductor device, such as a transistor or other, is formed on a semiconductor substrate, an interconnect hole going from the back surface of the semiconductor substrate to the semiconductor device can be formed so as to electrically connect a back-side electrode formed on the back surface to the semiconductor device.
[0003] When the semiconductor device having the above structure is assembled to a housing substrate by brazing, if the brazing formed on a back-side electrode enters inside an interconnect hole, the manufacturing yield may be degraded due to deformation of the back-side electrode or of an electrode of a semiconductor device, caused by leaching or separation of the brazing on the surface of the semiconductor device. Brief description of the drawings
[0004] Fig. 1 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to one embodiment.
[0005] Figure 2 is a diagram explaining an example of a manufacturing process for a semiconductor device according to a first embodiment.
[0006] Figure 3 is a diagram explaining an example of a manufacturing process for a semiconductor device according to a second embodiment.
[0007] FIG. 4 is a diagram explaining an example of a method for manufacturing a semiconductor device according to a third embodiment. Detailed description
[0008] A method for manufacturing a semiconductor device according to one embodiment comprises forming an electrode on a first principal surface of a semiconductor substrate made of a composite semiconductor; forming, at a location where the electrode is formed, an interconnecting hole that penetrates the first principal surface and a second principal surface of the semiconductor substrate, a ratio of the thickness of the semiconductor substrate to a maximum value of the width of an opening in the second principal surface being greater than 1; the formation of a back-side electrode on a second principal surface of the semiconductor substrate such that the back-side electrode is electrically coupled to the electrode in the interconnect hole; the formation of an insulating layer arranged at least one layer above the opening; and the formation of a solder layer in one layer above the back-side electrode and the insulating layer.
[0009] Below, a semiconductor device and a method for manufacturing a semiconductor device according to several embodiments are described, with reference to the attached drawings.
[0010] Fig. 1 is a schematic cross-sectional view showing an example of the structure of a semiconductor device according to the first embodiment.
[0011] The semiconductor device of the present embodiment comprises a semiconductor device, for example a transistor, and includes a solder layer SD, a backside electrode L2, a semiconductor substrate L1, an insulating layer L3, a first electrode El, a second electrode E2, and a third electrode E3.
[0012] The semiconductor device of the present embodiment is assembled to a PB package substrate by means of the solder layer SD. A plurality of semiconductor devices are, for example, mounted in the PB package substrate. The PB package substrate is a flat plate made of a conductive material, such as copper.
[0013] The first electrode E1, the second electrode E2 and the third electrode E3 are arranged on a front surface (first principal surface) of the semiconductor substrate LL
[0014] The first electrode El, the second electrode E2, and the third electrode E3 are made of gold (Au), for example. In the present embodiment, the first electrode El is, for example, a drain electrode of the transistor, the second electrode E2 is, for example, a gate electrode of the transistor, and the third electrode E3 is a source electrode of the transistor.
[0015] The semiconductor substrate L1 is a substrate made of a composite semiconductor, which is, for example, made of silicon carbonate (SiC), gallium arsenide (GaAs), and n-type gallium nitride (GaN). The semiconductor substrate L1 may comprise several layers made of a composite semiconductor.
[0016] The semiconductor substrate L1 has an interconnect hole VH formed to extend in a direction substantially parallel to the direction of the thickness X of the semiconductor substrate L1. The interconnect hole VH penetrates from the rear surface side to the front surface side of the semiconductor substrate L1, and a portion of the rear face of the third electrode E3 (the surface on the semiconductor substrate side L1) is exposed through the interconnect hole VH. In other words, the third electrode E3 is arranged on the opening of the interconnect hole VH on the front surface side of the semiconductor substrate Ll.
[0017] The back-side electrode L2 is formed between the back surface of the semiconductor substrate L1 (second main surface) and the solder layer SD. The back-side electrode L2 is electrically coupled to the third electrode E3 in the interconnect hole VH of the semiconductor substrate LL. The back-side electrode L2 is made of gold (Au), for example.
[0018] The insulating layer L3 is made of a material with low solder wettability, for example silicon dioxide (SiO2) or silicon nitride (SiN). The insulating layer L3 is arranged in a position between the back-side electrode L2 and the solder layer SD such that the insulating layer L3 covers the back-side electrode L2 at the interconnect hole VH of the semiconductor substrate LL
[0019] It is not necessary for the insulating layer L3 to cover the entire back-side electrode L2; it is sufficient for the insulating layer L3 to be arranged so that it covers at least a portion of the back-side electrode L2 located at the opening of the interconnect hole VH on the back surface side and a top layer close to it. In the example of [Fig. 1], the insulating layer L3 is arranged on the lateral surface of the interconnect hole VH extending in a direction substantially parallel to the direction of the thickness X of the semiconductor substrate L1, such that the insulating layer L3 covers the back-side electrode L2.
[0020] If the semiconductor device has the insulating layer L3 arranged as described above, since it is made of a material with low solder wettability, the solder arranged on the insulating layer L3 is repelled by the insulating layer L3 and does not flow into the interconnect hole VH. Consequently, the solder layer SD does not enter the interconnect hole VH but rather remains near the opening of the interconnect hole VH on the rear surface side.
[0021] In the semiconductor device of the present embodiment, the solder does not flow throughout the entire interior of the interconnect hole VH, but the opening of the interconnect hole VH on the rear surface side is sealed by the solder layer SD, and a void is thus formed inside the interconnect hole VH. This void 10 is a space surrounded at least by the solder layer SD and the insulating layer L3 in the interconnect hole VH, and in the present embodiment, it is a space surrounded by the solder layer SD, the insulating layer L3 and the rear-side electrode L2.
[0022] In the semiconductor device of the present embodiment, the ratio of the thickness H of the semiconductor substrate Ll, to a maximum value of the width W of the interconnect hole opening VH (the length in a direction substantially parallel to the second main surface) (thickness H of the semiconductor substrate Ll / maximum width W of the opening), is greater than 1.
[0023] For example, in the case where the opening of the interconnect hole VH is approximately circular, if the aspect ratio of the cross-section of the interconnect hole VH in a plane approximately parallel to the direction of the thickness X of the semiconductor substrate L1 and passing through the center of the opening of the interconnect hole VH (thickness H of the semiconductor substrate L1 / diameter W of the opening) is equal to or less than 1, in other words, if the thickness H of the semiconductor substrate L1 is equal to or less than the diameter W of the opening, the solder layer SD is likely to enter inside the interconnect hole VH even if the insulating layer L3 has been provided.This is probably due to the fact that if the opening of the interconnect hole VH is large and the thickness H of the semiconductor substrate L1 is small, when the semiconductor substrate is assembled to the housing substrate PB, an amount of solder pressed into the interconnect hole VH increases, and a distance between the back surface and the front surface of the interconnect hole VH is short, and the solder can in turn easily reach the front surface side of the semiconductor substrate L1.
[0024] For this reason, it is desirable that the aspect ratio of the cross-section of the interconnect hole VH (thickness H of the semiconductor substrate Ll / diameter W of the opening) be greater than 1. The opening of the interconnect hole VH is not limited to a circular shape; if the shape of the opening is not a circle, it is desirable that the ratio of the thickness H of the semiconductor substrate Ll to a maximum value of the width W of the opening of the interconnect hole VH (thickness H of the semiconductor substrate Ll / maximum width of the opening) be greater than 1.
[0025] Next, a method for manufacturing the semiconductor device is described with reference to the drawings
[0026] Fig. 2 is an explanatory diagram of an example of a manufacturing process for a semiconductor device according to the first embodiment.
[0027] First, an interconnect hole VH is formed on the rear surface side of the semiconductor substrate LL. For example, an etching mask (not shown) is used, and a predetermined portion of the semiconductor substrate LL is selectively removed, thus forming an interconnect hole VH. The etching mask is, for example, a silicon oxide film.
[0028] The VH interconnect hole is formed, for example, via an inductively coupled plasma dry etching process. If the semiconductor substrate L1 is, for example, a SiC substrate, the VH interconnect hole can be formed by etching a portion The SiC substrate is etched using a fluorine-containing etching gas. The interconnect hole VH is formed at a depth that reaches the third electrode E3, penetrating the semiconductor substrate L1.
[0029] Next, a back-side electrode L2 is formed on the back side of the semiconductor substrate L1 (step SA1). The back-side electrode L2 is formed, for example, by sputtering or metallic coating. The back-side electrode L2 contains gold, for example.
[0030] Then, an insulating film is formed on the back-side electrode L2, for example by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process (step SA2). The insulating film is, for example, made of silicon dioxide (SiO2) or silicon nitride (SiN), and formed so as to cover the back-side electrode L2 in the interconnect hole VH.
[0031] Next, the insulating film is etched in the direction of the thickness X of the semiconductor substrate L1 by dry etching, for example by reactive ion etching (RIE), so as to form an insulating layer L3 (step SA3). In other words, the insulating film (insulating layer L3) is removed, except for the portion formed on the lateral surface of the interconnect hole VH, by performing anisotropic etching in the direction of the thickness X of the semiconductor substrate LL
[0032] Next, solder is applied to the rear side of the semiconductor device (rear-side electrode L2 and insulating layer L3), and a solder layer SD is formed (step SA4). At this point, the solder is repelled by the insulating layer L3, thus preventing it from flowing into the interconnect hole VH. Consequently, a void 10 surrounded by the solder layer SD, the insulating layer L3, and the rear-side electrode L2 is formed in the interconnect hole VH.
[0033] As described above, depending on the semiconductor device and the method of manufacturing the semiconductor device according to the present embodiment, it is possible to prevent the solder layer SD from entering the interconnect hole VH and to improve the efficiency of manufacturing the semiconductor device.
[0034] Next, a semiconductor device and a method for manufacturing a semiconductor device according to the second embodiment are described in detail, with reference to the accompanying drawings. In the following description, the same components as those of the first embodiment described above will be assigned the same reference numbers, and their detailed descriptions will be omitted.
[0035] The semiconductor device of the present embodiment differs from the first embodiment mentioned above in the structure of the insulating layer L3.
[0036] The [Fig.3] is an explanatory diagram of an example of a manufacturing process for a semiconductor device according to a second embodiment.
[0037] First, as in the aforementioned first embodiment, an interconnect hole VH is formed on the rear surface side of the semiconductor substrate L1. Then, a rear-side electrode L2 is formed on the rear side of the semiconductor substrate L1 (step SB1). The rear-side electrode L2 is formed, for example, by sputtering or metallic coating. The rear-side electrode L2 contains gold, for example.
[0038] Next, an insulating film is formed on the back-side electrode L2, for example by a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process (step SB2). The insulating film is, for example, made of silicon dioxide (SiO2) or silicon nitride (SiN), and formed so as to cover the back-side electrode L2 in the interconnect hole VH.
[0039] Next, the insulating film on the back surface of the semiconductor substrate L1 is polished by a chemical and mechanical polishing (CMP) device to form the insulating layer L3 (step SB3). In other words, the insulating film is removed by polishing, except for the portion formed inside the interconnect hole VH.
[0040] Next, solder is applied to the rear side of the semiconductor device (rear electrode L2 and insulating layer L3), and a solder layer SD is formed (step SB4). At this point, the solder is repelled by the insulating layer L3, thus preventing it from flowing into the interconnect hole VH. Consequently, a void 10 surrounded by the solder layer SD and the insulating layer L3 is formed in the interconnect hole VH.
[0041] As described above, depending on the semiconductor device and the method of manufacturing the semiconductor device according to the present embodiment, it is possible to prevent the solder layer SD from entering the interconnect hole VH and to improve the efficiency of manufacturing the semiconductor device.
[0042] Next, a semiconductor device and a method for manufacturing a semiconductor device according to the third embodiment are described in detail, with reference to the accompanying drawings. In the following description, the same components as those of the first embodiment described above will be assigned the same reference numbers, and their detailed descriptions will be omitted.
[0043] The semiconductor device of the present embodiment differs from the first embodiment mentioned above in the structure of the insulating layer L3.
[0044] FIG. 4 is an explanatory diagram of an example of a process for manufacturing a semiconductor device according to the third embodiment.
[0045] First, as in the aforementioned first embodiment, an interconnect hole VH is formed on the rear surface side of the semiconductor substrate LL. Then, a rear-side electrode L2 is formed on the rear side of the semiconductor substrate LL. The rear-side electrode L2 is, for example, formed by sputtering. cathodic or metallic coating. The back-side electrode L2 contains gold, for example.
[0046] Then, an insulating film is formed on the back-side electrode L2, for example by a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process (SCI step). The insulating film is, for example, made of silicon dioxide (SiO2) or silicon nitride (SiN), and formed so as to cover the back-side electrode L2 in the interconnect hole VH.
[0047] Next, a photosensitive resin is formed on the insulating film, and the photosensitive resin is exposed via a photosensitive solder mask and developed, so that a reserve pattern Lr is formed on the insulating film in an interconnect hole VH and its peripheral portion (near the opening) (step SC2).
[0048] Next, the exposed insulating film of the reserve pattern Lr is removed via a dry etching process or a wet etching process, and an insulating layer L3 is formed by removing the reserve pattern Lr (step SC3). In other words, only the insulating film disposed under the reserve pattern Lr (the insulating film formed in the interconnect hole VH and near the opening of the interconnect hole VH) remains, and the other parts of the insulation are removed by shaping.
[0049] Next, solder is applied to the rear side of the semiconductor device (rear electrode L2 and insulating layer L3), and a solder layer SD is formed (step SC4). At this point, the solder is repelled by the insulating layer L3, thus preventing it from flowing into the interconnect hole VH. Consequently, a void 10 surrounded by the solder layer SD and the insulating layer L3 is formed in the interconnect hole VH.
[0050] As described above, depending on the semiconductor device and the method of manufacturing the semiconductor device according to the present embodiment, it is possible to prevent the solder layer SD from entering the interconnect hole VH and to improve the efficiency of manufacturing the semiconductor device.
[0051] Although some embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions.
[0052] Indeed, the new embodiments described in this document can be realized in a variety of other forms; moreover, various omissions, substitutions, and changes to the form of the embodiments described in this document can be made without departing from the spirit of the invention. The attached claims and their equivalents are intended to cover the forms or modifications that fall within the scope and spirit of the inventions.
Claims
Demands
1. Semiconductor apparatus further comprising: a semiconductor substrate (L1) having an interconnect hole (VH) penetrating into a first principal surface and a second principal surface; an electrode (E3) arranged above the interconnect hole (VH) on the first principal surface of the semiconductor substrate (L1); a backside electrode (L2) arranged on the second principal surface of the semiconductor substrate (L1) and electrically coupled to the electrode (E3) in the interconnect hole (VH); and an insulating layer (L3) arranged on the back-side electrode (L2) in at least a portion of the interconnect hole, wherein a ratio of a thickness of the semiconductor substrate (L1) to a maximum value of a width of an interconnect hole opening (VH) is greater than 1 said semiconductor device, further comprising: a solder layer (SD) arranged on the back-side electrode (L2) and the insulating layer (L3);and a void surrounded at least by the solder layer (SD) and the insulating layer (L3) in the interconnect hole (VH).;
2. A method for manufacturing a semiconductor device according to claim 1, comprising: the formation of an electrode (E3) on a first principal surface of a semiconductor substrate (L1) made of a compound semiconductor; the formation, at a location where the electrode (E3) is formed, of an interconnect hole (VH) which penetrates the first principal surface and a second principal surface of the semiconductor substrate (L1), in which a ratio of a thickness of the semiconductor substrate (L1) to a maximum value of a width of an opening in the second principal surface is greater than 1; the formation of a back-side electrode (L2) on a second principal surface of the semiconductor substrate (L1) such that the back-side electrode (L2) is electrically coupled to the electrode (E3) in the interconnect hole (VH); the formation of an insulating layer (L3) arranged at least one layer above the opening; and the formation of a brazing layer (SD) in one layer above the backside electrode (L2) and the insulating layer (L3).
3. Method of manufacturing a semiconductor device according to claim 2, wherein the formation of the insulating layer (L3) comprises: the formation of an insulating film on the back-side electrode (L2) and the performance of an anisotropic etching on the insulating film in a direction of the thickness of the semiconductor substrate (L1).
4. A method of manufacturing a semiconductor device according to claim 2, wherein the formation of the insulating layer (L3) comprises: the formation of an insulating film on the back-side electrode (L2) and the polishing of the insulating film arranged on a layer above the second main surface of the semiconductor substrate (L1).
5. A method of manufacturing a semiconductor device according to claim 2, wherein the formation of the insulating layer (L3) comprises: the formation of an insulating film on the back-side electrode (L2), the formation of a reserve pattern on the insulating film in the interconnect hole (VH) and near the opening, the removal of the exposed insulating film of the reserve pattern by etching, and the removal of the reserve pattern.