Optoelectronic device

Abstract

Optoelectronic Device This description concerns a pixel comprising: - a light-emitting element (32) and a first transistor (36) connected in series between a reference node (40) and a power supply node (52); and a first circuit (106) comprising a first terminal connected to the control terminal of the first transistor (36), a second terminal connected to the reference node (40), the first circuit being configured to generate a control voltage (VGS) on the first terminal, the first circuit (106) comprising a variable voltage divider (108, 110, 112, 120) configured to supply the control voltage (VGS) on the first terminal; and - a first switch (114) connected between the first terminal of the first circuit and a conduction terminal of the first transistor (36). Figure for the abstract: Fig. 3

Description

Title of the invention: Optoelectronic device technical field

[0001] This description relates generally to optoelectronic devices and, more particularly, to devices comprising pixels and their drivers. Prior art

[0002] A pixel of an image corresponds to the unit element of the image displayed by a display screen. For displaying color images, the display screen generally comprises, for the display of each pixel of the image, at least three components, also called display sub-pixels, each of which emits light, called the image pixel color component, essentially in the form of a single color (for example, red, green, and blue). The superposition of the image pixel color components emitted by the three display sub-pixels provides the observer with the sensation of color corresponding to the pixel of the displayed image. In this case, the set of three display sub-pixels used for displaying a pixel of an image is called the display pixel of the display screen. Each display sub-pixel may include a light source, in particular a light-emitting diode.

[0003] Display pixels can be distributed in a matrix, each display pixel being located at the intersection of a row and a column of the matrix. Each display pixel includes, for example, a light-emitting element and associated electronic circuits, such as a driver. Electrodes are provided along the rows and columns to connect each display pixel to control circuits. Generally, each row of display pixels is successively selected by a ROW signal transmitted along the row electrodes, and the display pixels of the selected row are programmed to display the desired image pixels by COL signals transmitted along the column electrodes.

[0004] Each generation of screen includes more display pixels in order to offer a more detailed image. However, the increased number of display pixels and, consequently, the increased number of associated electronic circuits create a significant static current and increased energy consumption. Summary of the invention

[0005] An embodiment overcomes all or part of the drawbacks of known optoelectronic devices.

[0006] There is a need for an optoelectronic device that generates less static current.

[0007] There is a need for a more compact pixel driver.

[0008] There is a need to optimize the control voltage of transistors in pixels.

[0009] One embodiment provides for a pixel comprising:

[0010] a light-emitting element and a first transistor connected in series between a reference node and a power supply node; and

[0011] a first circuit comprising a first terminal connected to the control terminal of the first transistor, a second terminal connected to the reference node, the first circuit being configured to generate a control voltage on the first terminal, the first circuit comprising a variable voltage divider configured to provide the control voltage on the first terminal; and

[0012] a first switch connected between the first terminal of the first circuit and a conduction terminal of the first transistor. Such a structure makes it possible to reduce the static current and the size of the pixels.

[0013] According to one embodiment, the voltage divider includes a first capacitor connected between the first and second terminals of the first circuit.

[0014] According to one embodiment, the first circuit includes a third terminal connected to a node for applying a data signal.

[0015] According to one embodiment, the voltage divider includes a second capacitor connected between the first terminal of the first circuit and the third terminal of the first circuit.

[0016] According to one embodiment, the pixel includes a second switch connected between the second terminal of the first circuit and a third switch connected between the second capacitor and the third terminal of the first circuit.

[0017] According to one embodiment, the voltage divider includes at least one third capacitor, the third capacitor being configured to be connected between the first terminal and either the second or the third terminal, depending on a control voltage.

[0018] According to one embodiment, at least one third capacitor is connected in series to a fourth switch, one terminal of the second capacitor being connected to the first terminal of the first circuit, the second terminal of the second capacitor being connected to a first terminal of the fourth switch, the fourth switch comprising a second terminal connected to the second terminal of the first circuit and the fourth switch comprising a third terminal connected to the third terminal of the first circuit.

[0019] According to one embodiment, the first circuit comprises at least two sets of a second capacitor connected in series to a fourth switch, the fourth switches being controlled by different control voltages.

[0020] According to one embodiment, the first transistor and the element are connected in series to a fifth switch.

[0021] According to one embodiment, the first circuit includes a sixth switch connected in series between the control terminal of the transistor and a node for applying a reset voltage.

[0022] Another embodiment provides for a display screen comprising a plurality of pixels as described above.

[0023] According to one embodiment, the pixels are arranged in a matrix and the third terminal of each first circuit is configured to receive a voltage common to all the pixels of the same row.

[0024] According to one embodiment, the light-emitting elements are connected to a common cathode, the elements of each pixel being connected between the first transistor of said pixel and the reference node.

[0025] Another embodiment provides a method for controlling a pixel as described above, comprising:

[0026] a first phase during which the first switch is closed and the capacitors of the voltage dividers connected between the first and second terminals of the first circuit are charged, and

[0027] a second phase during which the first switch is open.

[0028] According to one embodiment, the process comprises an alternation of the first and second phases. Brief description of the drawings

[0029] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0030] [Fig.1] represents an example of an optoelectronic device;

[0031] [Fig.2] schematically represents an example of a pixel;

[0032] [Fig.3] represents in more detail a part of the pixel of [Fig.2] according to one embodiment;

[0033] [Fig.4] represents in more detail a part of the pixel of [Fig.2] according to the embodiment of [Fig.3];

[0034] [Fig.5] represents an operation of the embodiment of [Fig.3];

[0035] [Fig.6] represents another functioning of the embodiment of [Fig.3];

[0036] [Fig.7] represents another functioning of the embodiment of [Fig.3];

[0037] Figure 8 shows in more detail the different functions of the resuscitation mode lisation of [Fig.3];

[0038] [Fig.9] represents in more detail a part of the device of [Fig.2] according to another embodiment;

[0039] [Fig. 10] represents in more detail a part of the pixel of [Fig.2] according to the embodiment of [Fig.9];

[0040] [Fig.1 1] represents an operation of the embodiment of [Fig.9];

[0041] [Fig. 12] represents another functioning of the embodiment of [Fig. 9];

[0042] [Fig. 13] represents another functioning of the embodiment of [Fig. 9]; And

[0043] [Fig. 14] represents the functions of the embodiment of [Fig. 9]. Description of the implementation methods

[0044] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0045] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0046] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0047] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0048] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0049] Fig. 1 represents an example of an optoelectronic device 10.

[0050] The device 10 includes a screen 12. The screen 12 is configured, for example, to project light, images, or videos. The screen includes a pixel matrix 14. The screen 12 includes, for example, at least one million pixels, at least two million pixels, or at least eight million pixels. The screen includes rows 16 of pixels 14 and columns 18 of pixels 14.

[0051] The device 10 further includes a row control circuit, or driver, 20 and a column control circuit, or driver, 22. The circuit 20 is configured to provide row voltages ROW, in other words, to provide common control voltages to all pixels in the same row. Similarly, the circuit 22 is configured to provide column voltages COL, in other words to provide common control voltages to all pixels in the same column. For example, the ROW voltage corresponds to row selection and the clock signal in lighting mode, such as pulse-width modulation (PWM). For example, the COL voltage corresponds to lighting data, such as video data.

[0052] The device 10 includes, for example, a controller 24 configured to provide circuits 20 and 22 with the data to generate the ROW and COL voltages. The controller 24 can also provide the clock signal to circuits 20 and 22 and optionally to pixels 14. The controller 24 is, for example, a synchronization controller.

[0053] Fig. 2 schematically represents an embodiment of a pixel 14. Pixel 14 comprises a region 26 and a region 30.

[0054] Region 26 includes at least one light-emitting element. For example, the light-emitting element is, in the remainder of the description, a light-emitting diode. However, the light-emitting element may be any type of light-emitting component. Region 26 includes, for example, three light-emitting diodes: one diode configured to provide blue light, one diode configured to provide green light, and one diode configured to provide red light.

[0055] Region 30 is, for example, the pixel driver. Region 30 includes analog and digital circuits. Region 30 includes peripheral circuits. Region 30 includes, for example, a power supply circuit configured to provide the supply voltages for the pixels. Region 30 includes, for example, control logic.

[0056] For example, each pixel comprises only four input pads, not shown. In other words, each pixel receives only four external voltages: a supply voltage, a reference voltage, for example ground GND, a ROW signal transmitted along the row electrodes and a COL signal transmitted along the column electrodes.

[0057] Figure 3 shows in more detail a portion of pixel 14 of Figure 2 according to one embodiment. In the example of Figure 3, the pixel is configured to be connected to other pixels by a common anode.

[0058] Pixel 14 includes a light-emitting diode 32. The diode 32 is connected in series to a transistor 36 and a switch 38 between a node 52 for applying a supply voltage VCC to the pixel and a node 40 for applying a reference voltage, for example, ground GND. The transistor 36 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), for example, a P-channel transistor. The transistor 36 includes a control terminal, for example, a gate, and two conduction terminals, for example, a drain and a source. The switch 38 includes two terminals 48 and 50.

[0059] Diode 32, switch 38 and transistor 36 are connected in series between node 52 and node 40. Diode 32, transistor 36 and switch 38 are connected so that the diodes of different pixels can be connected to a common anode. Diode 32 is connected between node 52 and switch 38. In other words, the anode of diode 32 is connected, preferably connected, to node 52 and the cathode of diode 32 is connected, preferably connected, to terminal 48 of switch 38. Terminal 50 of switch 38 is connected to node 40 via transistor 36. In other words, terminal 50 of switch 38 is connected, preferably connected, to a node 105, node 105 being connected, preferably connected, to one conduction terminal, for example the drain, of transistor 36 and the other conduction terminal, for example the source, of transistor 36 is connected, preferably connected, to node 40.

[0060] The control terminal of transistor 36 is connected, preferably connected, to a circuit 106 configured to generate the voltage VGS.

[0061] Circuit 106 includes a variable voltage divider. In other words, circuit 106 includes a voltage divider in which the ratio between the two capacitive branches is variable.

[0062] The voltage divider, and consequently the circuit 106, includes a capacitor 108. The capacitance of the capacitor 108 is preferably fixed. The capacitor 108 is connected between the control terminal of the transistor 36 and the node 40. A first terminal of the capacitor 108 is connected, preferably connected, to a node 109, the node 109 being connected, preferably connected, to the control terminal of the transistor 36. A second terminal of the capacitor 108 is connected, preferably connected, to the node 40.

[0063] The control terminal of transistor 36 is further connected to a node 118 for applying a voltage ROW1 generated from the voltage ROW. The control terminal of transistor 36 is connected to node 118 via a capacitor 120. The capacitance of capacitor 120 is preferably fixed. More precisely, the control terminal of transistor 36 is connected, preferably connected, to one terminal of capacitor 120. In other words, said terminal of capacitor 120 is connected, preferably connected, to node 109. Another terminal of capacitor 120 is connected, preferably connected, to node 118.

[0064] The voltage divider also includes at least one capacitor 110 connected in parallel either to capacitor 108 or to capacitor 120, depending on a control signal. The capacitances of the capacitors 110 are, for example, fixed. The capacitances of the capacitors 110 are, for example, substantially equal.

[0065] In the example of [Fig.3], the divider comprises three capacitors 110, referenced 110a, 110b and 110c. In general, the number of capacitors 110 depends on the application.

[0066] Each capacitor 110 is connected in series to a switch 112. In other words, capacitor 110a is connected in series to a switch 112a, capacitor 110b is connected in series to a switch 112b and capacitor 110c is connected in series to a switch 112c.

[0067] One terminal of each capacitor 110 is connected, preferably connected, to node 109. Another terminal of each capacitor 110 is connected, preferably connected, to an input terminal of the corresponding switch 112. Each switch 112 has a first output terminal connected, preferably connected, to node 40 and a second output terminal connected, preferably connected, to node 118. Each switch 112 is configured to connect the corresponding capacitor 110 to either node 40 or node 118 depending on a control voltage. Each switch 112 is preferably controlled by its own control voltage, for example, independent of the control voltages of the other switches 112.

[0068] The value of the voltage VGS is therefore determined by the control voltages of the switches 112, which determines the capacitance quotient of the two branches of the voltage divider.

[0069] Circuit 106 further includes a switch 114 connected between node 109 and node 105. Circuit 106 further includes a switch 115 connected between node 109 and a node for applying a reset voltage VRS.

[0070] Switch 115 includes a control terminal, for example connected, preferably connected, to a control voltage application node SW1. Switch 115 is configured to be used to reset the voltage divider. Switch 114 includes a control terminal, for example connected, preferably connected, to a control voltage application node SW2.

[0071] The control terminal of the switch 38 is for example connected, preferably connected, to a node for applying a control voltage SW3.

[0072] The circuit in [Fig. 3] includes, for example, a calibration step, during which known capacitance values ​​are supplied to the branches of the voltage divider. The capacitors connected between nodes 109 and 40 are charged, with a CTL voltage, not shown in [Fig. 3], having the first value. The CTL voltage then takes the second value, and the VGS voltage determined by the capacitive divider is applied to transistor 36. The diode is then illuminated with known data. The brightness of the diode is measured and compared to the desired brightness. The control voltage values ​​of switches 112 are modified according to the difference between the desired brightness and the measured brightness. The brightness of the diode is measured again. The calibration step can, for example, be applied again to further correct the brightness value of the diode.

[0073] Figure 4 shows in more detail an example of the implementation of part of the pixel of [Fig.2] according to the embodiment of [Fig.3]. More precisely, [Fig.4] represents a 200 circuit for generating the control voltages SW1, SW2 and SW3.

[0074] The control voltages SW1, SW2 and SW3 are obtained from the ROW signal, the CTL voltage and a PWM-D voltage.

[0075] The CTL voltage indicates that the driver is in PWM mode. In other words, the CTL voltage is, for example, a binary value and takes one value when the driver is in PWM mode and another value when the driver is in video data write mode. The PWM-D voltage, for example, corresponds to a binary signal. The PWM-D voltage corresponds to the data for PWM mode.

[0076] The circuit 200 includes an input node 202, configured to receive the ROW signal, an input node 204, configured to receive the CTL voltage, and an input node 206, configured to receive the PWM-D signal. The circuit 200 includes an output node 208, to which the SW1 voltage is applied, an output node 210, to which the SW2 voltage is applied, and an output node 212, to which the SW3 voltage is applied.

[0077] The circuit 200 includes a NAND logic gate 214. A first input of the gate 214 is connected, preferably connected, to the node 204. A second input of the gate 214 is connected to the node 202 by an inverter 216. In other words, the input of the inverter 216 is connected, preferably connected, to the node 202 and the output of the inverter 216 is connected, preferably connected, to the second input of the gate 214.

[0078] The circuit 200 includes an AND logic gate 218. An output of gate 218 is connected, preferably connected, to node 212. A first input of gate 218 is connected, preferably connected, to node 206. A second input of gate 218 is connected, preferably connected, to an output of logic gate 214.

[0079] The circuit 200 includes a NOR logic gate 220. One output of gate 220 is connected, preferably connected, to node 210. A first input of gate 220 is connected, preferably connected, to the output of logic gate 214. A second input of gate 220 is connected to a node 222. Node 222 is connected to the output of logic gate 214 by a delay circuit 224. In other words, one terminal of the delay circuit 224 is connected, preferably connected, to the output of gate 214 and the other terminal of the delay circuit 224 is connected, preferably connected, to node 222.

[0080] Circuit 200 includes a NOR logic gate 226. One output of logic gate 226 is connected, preferably connected, to node 208. A first input of gate 226 is connected, preferably connected, to the output of logic gate 214. A second input of gate 226 is connected to node 222 via an inverter 228. In other words, the input of inverter 228 is connected, preferably connected, to node 222 and the output of inverter 228 is connected, preferably connected, to the second input of gate 206.

[0081] Figures 5, 6, and 7 represent successive stages of pixel operation. Figures 5 and 6 depict driver refresh. Figure 7 represents PWM mode. Refresh is preferably applied regularly during the pixel's PWM control, for example, before all data transmission.

[0082] Figure 5 represents an operation of the embodiment of Figure 3. More specifically, Figure 5 represents a reset step.

[0083] During this step, the control voltages SW1, SW2, and SW3 are such that switch 115 is closed, switch 114 is open, and switch 38 is open. The voltage across the gate of transistor 36 is therefore substantially equal to the reset value VRS.

[0084] Figure 6 represents another functioning of the embodiment of Figure 3. Figure 6 represents a programming step.

[0085] During this step, the control voltages SW1, SW2, and SW3 are such that switch 115 is open, switch 114 is closed, and switch 38 is open. The voltage across the gate of transistor 36 is therefore substantially equal to the threshold value Vth of transistor 36.

[0086] Figure 7 represents another operating mode of the embodiment of Figure 3. This operation corresponds to the PWM mode.

[0087] During this step, the control voltages SW1, SW2, and SW3 are such that switch 115 is open and switch 114 is open. Switch 38 is open or closed depending on the PWM data. The voltage across the gate of transistor 36 depends on the signal R0W1.

[0088] Figure 8 shows in more detail the different functions of the embodiment of Figure 3. More specifically, Figure 8 shows the signal R0W1, the voltage CTL, the control voltage SW1, the control voltage SW2 and the control voltage SW3 during PWM mode (A) and during video data writing mode (B).

[0089] During video data writing mode (B), the CTL voltage takes a low value, indicating, in this example, that the pixel is not in PWM mode. Furthermore, the SW1, SW2, and SW3 voltages have a high value, a high value, and a low value, respectively. Switches 115, 114, and 38 are open. The ROW1 signal corresponds to a clock signal for writing data received on the COL signal.

[0090] The PWM mode (A) includes an alternation of periods (C) and (D).

[0091] During each period (D), the light-emitting element 32 is illuminated according to at least one data point, for example, a single data point. Each period (D) corresponds to the step in [Fig. 7]. Therefore, the voltages SW1, SW2 Both have a high value, corresponding to an open state. The SW3 voltage is such that switch 38 is open or closed depending on the programmed pixel illumination. The CTL voltage has a high value, indicating PWM mode. The ROW1 signal has a high value.

[0092] The periods (C) correspond to the driver refresh, in other words, to the successive steps in Figures 5 and 6. During the beginning of period (C), in other words, during step [Fig. 5], the signal R0W1 has a low value, the voltage CTL has a high value, the voltage SW1 has a low value, the voltage SW2 has a high value, and the voltage SW3 has a low value. During the remainder of period (C), in other words, during step [Fig. 6], the signal R0W1 has a low value, the voltage CTL has a high value, the voltage SW1 has a high value, the voltage SW2 has a low value, and the voltage SW3 has a low value.

[0093] Preferably, the periods C have identical durations. The periods D, for example, have identical durations. According to one embodiment, the periods D are periods with binary weights. In other words, certain durations of the periods D are equal to 1 / (2An) times the maximum value of the duration of period D, where n is a positive integer. According to one embodiment, the periods (C) occur, for example, periodically in PWM mode (A).

[0094] Figure 9 represents in more detail a part of the device of Figure 2 according to another embodiment.

[0095] The embodiment of [Fig.9] differs from the embodiment of [Fig.3] in that the embodiment of [Fig.9] includes a switch 230 and a switch 232.

[0096] The switch 230 is connected in series to the capacitor 120 between the node 109 and the node 118. In other words, one terminal of the capacitor 120 is connected, preferably connected, to the node 109 and the other terminal of the capacitor 120 is connected, preferably connected, to a node 234. One terminal of the switch 230 is connected, preferably connected, to the node 234 and the other terminal of the switch 230 is connected, preferably connected, to the node 118.

[0097] Switch 232 is connected between nodes 40 and 234. In other words, one terminal of switch 232 is connected, preferably connected, to node 234 and the other terminal of switch 232 is connected, preferably connected, to node 40.

[0098] Switches 230 and 232 are configured to have opposite states. In other words, when one of switches 230 and 232 is open, the other is closed. Switch 230 includes a control terminal configured to receive a control voltage SW4. Switch 232 includes a control terminal configured to receive a control voltage SW4'. The control voltages SW4 and SW4' are, for example, complementary binary voltages. The voltage SW4, for example, is equal to the CTL voltage.

[0099] Figure 10 shows in more detail a portion of the pixel of Figure 2 according to the embodiment of Figure 9. More specifically, Figure 4 shows a circuit 200 for generating the control voltages SW1, SW2 and SW3.

[0100] The control voltages SW1, SW2 and SW3 are obtained from the ROW signal, a CTL voltage and a PWM-D voltage.

[0101] The circuit 200 includes an input node 202', configured to receive the ROW signal, an input node 204', configured to receive the CTL voltage, and an input node 206', configured to receive the PWM-D signal. The circuit 200 includes an output node 208', to which the SW1 voltage is applied, an output node 210', to which the SW2 voltage is applied, and an output node 212', to which the SW3 voltage is applied.

[0102] The circuit 200 includes a NAND logic gate 214'. A first input of gate 214' is connected, preferably connected, to node 204'. A second input of gate 214' is connected to node 202' via an inverter 216'. In other words, the input of inverter 216' is connected, preferably connected, to node 202' and the output of inverter 216' is connected, preferably connected, to the second input of gate 214'.

[0103] Circuit 200 includes an AND logic gate 218'. An output of gate 218' is connected, preferably connected, to node 212'. A first input of gate 218' is connected, preferably connected, to node 206'. A second input of gate 214' is connected, preferably connected, to an output of logic gate 214'.

[0104] Circuit 200 includes a NOR logic gate 220'. One output of logic gate 220' is connected, preferably connected, to node 210'. A first input of gate 220' is connected, preferably connected, to node 204'. A second input of gate 220' is connected to a node 222'. Node 222' is connected to node 204' by a delay circuit 224'. In other words, one terminal of the delay circuit 224' is connected, preferably connected, to node 204' and the other terminal of the delay circuit 224' is connected, preferably connected, to node 222'.

[0105] Circuit 200 includes a NOR logic gate 226'. One output of logic gate 226' is connected, preferably connected, to node 208'. A first input of gate 226' is connected, preferably connected, to node 204'. A second input of gate 226' is connected to node 222' via an inverter 228'. In other words, the input of inverter 228' is connected, preferably connected, to node 222' and the output of inverter 228' is connected, preferably connected, to the second input of gate 226'.

[0106] Figures 11, 12 and 13 represent successive stages of the operation of the pixel.

[0107] Figure 11 represents an operation of the embodiment of Figure 9. More specifically, Figure 11 represents a reset step.

[0108] During this step, the control voltages SW1, SW2, SW3, and SW4 are such that switches 38, 114, and 230 are open and switches 115 and 232 are closed. The voltage across the gate of transistor 36 is therefore substantially equal to the reset value VRS.

[0109] Figure 12 represents another functioning of the embodiment of Figure 9. Figure 12 represents a programming step.

[0110] During this step, the control voltages SW1, SW2, SW3, and SW4 are such that switches 38, 115, and 230 are open and switches 114 and 232 are closed. The gate voltage of transistor 36 is therefore substantially equal to the Vth value of transistor 36.

[0111] Figure 13 represents another operating mode of the embodiment of Figure 9. This operation corresponds to the PWM mode.

[0112] During this step, the control voltages SW1, SW2, SW3, and SW4 are such that switches 114, 115, and 232 are open and switch 230 is closed. Switch 38 is opened or closed depending on the PWM data. The voltage across the gate of transistor 36 depends on the signal R0W1.

[0113] Figure 14 represents the operation of the embodiment of Figure 9. More specifically, Figure 14 represents the signal R0W1, the voltage CTL, in other words the control voltage SW4, the control voltage SW1, the control voltage SW2 and the control voltage SW3, during PWM mode (A) and during video data writing mode (B).

[0114] During PWM mode, the control voltages SW1 and SW2 are held high. In other words, switches 115 and 114 are both held closed. The CTL voltage, in other words, the SW4 voltage, is held high. Consequently, switches 230 and 232 are held closed and open, respectively, during PWM mode. The ROW signal is held low during periods (C) and high during periods (D). Periods (C) occur, for example, periodically during PWM mode (A). During periods (C), the SW3 voltage is held low, corresponding to an open state for switch 38. During periods (D), the SW3 voltage alternates between high and low values ​​depending on the desired pixel illumination.

[0115] The PWM mode (A) comprises an alternation of periods (C) and (D). The pixel operation comprises an alternation of the PWM mode (A) and the data write mode (B).

[0116] The data writing mode comprises a first period (E) followed by a second period (F). The first period (E) corresponds to the beginning of the data writing mode.

[0117] During the first period (E), the ROW signal, the CTL voltage, and the SW1 and SW3 voltages are held at a low value. The SW2 voltage is held at a high value.

[0118] During the second period (F), the CTL voltage takes a low value, indicating, in this example, that the pixel is not in PWM mode. Furthermore, the SW1, SW2, and SW3 voltages have a high, a high, and a low value, respectively. Switches 115 and 38 are open. Switch 114 is closed. The ROW 1 signal corresponds to a clock signal for writing data, received on the COL signal.

[0119] One advantage of the described embodiments is that the control circuit for transistor 36 is simplified, making it less expensive and smaller. In particular, the analog portion of each pixel is reduced.

[0120] Another advantage of the described embodiments is that the control circuit is a passive device, which reduces the static current.

[0121] Another advantage of the described embodiments is that the VGS voltage is generated on the basis of the ROW and COL voltages.

[0122] Another advantage of the described embodiments is that it is possible to easily optimize the VGS voltage and consequently to calibrate each pixel independently.

[0123] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0124] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Pixel comprising: - a light-emitting element (32) and a first transistor (36) connected in series between a reference node (40) and a power supply node (52); and a first circuit (106) comprising a first terminal connected to the control terminal of the first transistor (36), a second terminal connected to the reference node (40), the first circuit being configured to generate a control voltage (VGS) on the first terminal, the first circuit (106) comprising a variable voltage divider (108, 110, 112, 120) configured to provide the control voltage (VGS) on the first terminal, the voltage divider comprising two capacitive branches, the proportion between the branches being variable; and - a first switch (114) connected between the first terminal of the first circuit and a conduction terminal of the first transistor (36).

2. Pixel according to claim 1, wherein the voltage divider comprises a first capacitor (108) connected between the first and second terminals of the first circuit (106).

3. Pixel according to claim 1 or 2, wherein the first circuit comprises a third terminal (118) connected to a data signal application node (ROW).

4. Pixel according to claim 3, wherein the voltage divider comprises a second capacitor (120) connected between the first terminal of the first circuit (106) and the third terminal (118) of the first circuit.

5. Pixel according to claim 4, comprising a second switch (232) connected between the second terminal of the first circuit and a third switch (230) connected between the second capacitor and the third terminal of the first circuit.

6. Pixel according to any one of claims 3 to 5, wherein the voltage divider comprises at least one third capacitor (110a, 110b, 110c), the third capacitor being configured to be connected between the first terminal and either the second or the third terminal, depending on a control voltage (CTL).

7. Pixel according to claim 6 in its connection to claim 4, wherein each at least one third capacitor is connected in series to a fourth switch (112a, 112b, 112c), one terminal of the second capacitor being connected to the first terminal of the first circuit, the second terminal of the second capacitor being connected to a first terminal of the fourth switch, the fourth switch comprising a second terminal connected to the second terminal of the first circuit and the fourth switch comprising a third terminal connected to the third terminal of the first circuit.

8. Pixel according to claim 7, wherein the first circuit comprises at least two sets of a second capacitor connected in series to a fourth switch, the fourth switches being controlled by different control voltages.

9. Pixel according to any one of claims 1 to 8, wherein the first transistor (36) and the element (32) are connected in series to a fifth switch (38).

10. Pixel according to any one of claims 1 to 9, wherein the first circuit comprises a sixth switch (115) connected between the control terminal of the transistor (36) and a node for applying a reset voltage.

11. Display screen comprising a plurality of pixels according to any one of claims 1 to 10.

12. Display screen according to claim 11 in its connection with claim 3, wherein the pixels are arranged in a matrix and the third terminal (118) of each first circuit is configured to receive a voltage common to all pixels in the same row.

13. Display screen according to claim 11 or 12, wherein the light-emitting elements are connected to a common cathode, the elements (32) of each pixel being connected between the first transistor (36) of said pixel and the reference node (40).

14. A method for controlling a pixel according to any one of claims 1 to 10 in relation to claim 2, comprising: - a first phase during which the first switch (114) is closed and the capacitors of the voltage dividers connected between the first and second terminals of the first circuit are charged, and - a second phase during which the first switch (120) is open.

15. A method according to claim 14, comprising an alternation of the first and second phases.

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