Electronic device

Abstract

Electronic device The present description relates to a device comprising: - a power supply input receiving a supply voltage (VDD); - a switching power supply comprising an output on which a supply voltage (VBUCK, VBUCK1, VBUCK2) is generated; and - a linear voltage regulator (12) supplying a load, the regulator (12) receiving the supply voltages, the regulator (12) comprising two transistors (32, 34, 36) connected between the supply input, respectively the output of the supply, and an output node of the regulator (40), when the current drawn by the load is below a threshold, an output current, supplied to the load is equal to a current (IBUCK, IBUCK1, IBUCK2) flowing through the transistor (32, 34) and that, when said current is above the threshold, the output current is equal to a current (IBAT) flowing through the transistor (36) plus a current (IBUCK, IBUCK1, IBUCK2) flowing through the transistor (32, 34).Figure for abstract: Fig. 2.

Description

Title of the invention: Electronic device Technical field

[0001] The present description relates generally to electronic devices, and more particularly to devices comprising a linear voltage regulator. Prior art

[0002] In electronics, a linear regulator is a voltage regulator based on an active component working in its linear region or on a passive component, such as a Zener diode, working in its reverse region.

[0003] A low dropout voltage regulator (LDO) is a type of linear voltage regulator that can regulate the output voltage even when the supply voltage is very close to the output voltage. Summary of the invention

[0004] One embodiment overcomes all or part of the drawbacks of known electronic devices.

[0005] One embodiment provides an electronic device comprising: a first power input configured to receive a first supply voltage; a first switching power supply comprising a first output, the first switching power supply being configured to generate a second supply voltage on the first output; and a linear voltage regulator configured to supply a load included in the device, the regulator being configured to receive the first and second supply voltages, the regulator comprising: a first transistor connected between the first power supply input and an output node of the regulator; and a second transistor connected between the output of the first switching power supply and the output node of the regulator, the regulator being configured so that, when the current, drawn by the load, is below a threshold, a first output current, supplied to the load by the output node of the regulator, is equal to a third current flowing through the second transistor and that, when said current is above the threshold, the first output current is equal to the sum of a fourth current flowing through the first transistor and the third current flowing through the second transistor, the fourth current being non-zero.

[0006] Another embodiment provides a method of controlling an electronic device comprising: a first power input receiving a first supply voltage; a first switching power supply comprising a first output, the first switching power supply generating a second supply voltage on the first output; and a linear voltage regulator supplying a load included in the device, the regulator receiving the first and second supply voltages, the regulator comprising: a first transistor connected between the first power supply input and an output node of the regulator; and a second transistor connected between the output of the first switching power supply and the output node of the regulator, when the current, drawn by the load, is below a threshold, a first output current, supplied to the load by the output node of the regulator, is equal to a third current flowing through the second transistor and, when said current is above the threshold, the first output current is equal to the sum of a fourth current flowing through the first transistor and the third current flowing through the second transistor, the fourth current being non-zero.

[0007] According to one embodiment, the regulator is configured so that, when the current drawn by the load is above the threshold, the greater the current drawn, the greater the fourth current flowing through the first transistor.

[0008] According to one embodiment, the regulator comprises: an error amplifier configured to receive as input a reference voltage and a voltage representative of the output voltage of the regulator and configured to generate an error voltage; a voltage to current converter, comprising an input configured to receive the error voltage and generating a fifth current on a second output of the converter and a sixth current on a third output of the converter; and a first gate driver circuit driving the first transistor and a second gate driver circuit driving the second transistor, the converter being configured to provide the fifth current to the first driver circuit and the sixth current to the second driver circuit.

[0009] According to one embodiment, the regulator comprises a voltage divider bridge whose input is connected to the output node of the regulator and whose output is connected to an input of the amplifier so as to provide the voltage representative of the output voltage.

[0010] According to one embodiment, the converter comprises a third transistor connected between a first node and a node for applying a reference voltage, the third transistor being configured to be controlled by the error voltage, the converter comprising a fourth transistor connecting the first node to the second output and at least a fifth transistor connecting the first node to the third output.

[0011] According to one embodiment, the first node and the third output are connected by a set of at least two fifth transistors connected in parallel.

[0012] According to one embodiment, the second gate control circuit comprises a sixth transistor connected as a diode between the second output of the converter and the output of the first switching power supply, the control terminal of the sixth transistor being connected to an output of the second control circuit.

[0013] According to one embodiment, the second control circuit comprises: a seventh transistor connected as a diode between an input configured to receive a reference current and the output of the first switching power supply, and an eighth transistor connected between the second output of the converter and the output of the first switching power supply, the control terminal of the eighth transistor being connected to the control terminal of the seventh transistor.

[0014] According to one embodiment, the first gate control circuit comprises a ninth transistor connected as a diode, the ninth transistor and a resistor being connected between the first output of the converter and the first input of the device, the control terminal of the ninth transistor being connected to an output of the first control circuit.

[0015] According to one embodiment, the first control circuit comprises: a tenth transistor connected as a diode between an input configured to receive a reference current and the first input of the device, and an eleventh transistor connected between the first output of the converter and the first input of the device, the control terminal of the tenth transistor being connected to the control terminal of the eleventh transistor.

[0016] According to one embodiment, the first control circuit comprises: a twelfth transistor connected between the first output of the converter and the first input of the device; a first switch connected between the control terminal of the twelfth transistor and the input configured to receive the reference current; and a second switch connected between the control terminal of the twelfth transistor and the first input of the device.

[0017] According to one embodiment, the device comprises at least one second switching power supply, and comprises, for each second switching power supply, a second transistor, connected between the output of the corresponding second switching power supply and the output node, the regulator being configured so that only a current passing through one of the second transistors is non-zero at the same time. Brief description of the drawings

[0018] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0019] [Fig.l] represents an embodiment of an electronic device comprising a linear voltage regulator;

[0020] [Fig.2] represents an embodiment of a linear voltage regulator;

[0021] [Fig.3] shows in more detail a part of the embodiment of [Fig.2];

[0022] [Fig.4] shows in more detail another part of the embodiment of the [Fig.2] ; and

[0023] [Fig.5] shows in more detail another part of the embodiment of the [Fig.2], Description of the embodiments

[0024] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0025] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0026] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0027] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures or to a ... in a normal position of use.

[0028] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0029] [Fig.l] shows an embodiment of an electronic device 10 comprising a linear voltage regulator 12. The voltage regulator 12 is a low dropout voltage regulator or LDO regulator (Low DropOut regulator).

[0030] The regulator 12 is configured to supply a load 14. The load 14 is for example an analog circuit. The load 14 is for example a logic circuit. The load 14 is for example an analog circuit for controlling a switching power supply (SMPS - Switched Mode Power Supply).

[0031] The regulator 12 comprises an output on which an output voltage VOUT is generated. The voltage VOUT is the supply voltage of the circuit 14. Said output is connected, preferably connected, to a supply input of the circuit 14.

[0032] The device 10 may for example operate in a low-power mode. In order to ensure low power consumption, the regulator 12 may be powered by at least two voltage sources, at least one having a value lower than the power supply voltage of the device 10. Said voltage sources providing different power supply voltages. The regulator 12 generates the output voltage VOUT from one of the power supply voltages. The regulator generates a current IOUT on said output.

[0033] In the example of [Fig.l], the regulator 12 is connected to three power sources. The regulator 12 can therefore be powered by one or more of these voltage sources. Depending on the load 14 and depending on the power used by the load 14, the supply voltage of the regulator can come from one of these sources, or from several.

[0034] The regulator 12 is for example powered by a supply voltage VDD of the device 10. The voltage VDD is for example greater than 3 V, for example equal to 5 V. In other words, the regulator 12 comprises a supply input connected, preferably connected, to a node 16 for applying the voltage VDD. The regulator therefore receives on said input a current IB AT.

[0035] The regulator 12 is for example powered by at least one voltage generated by a switching power supply. In the example of [Fig.l], the device comprises two switching power supplies 18 and 20. Each of the power supplies 18 and 20 therefore comprises an output connected, preferably connected, to a power supply input of the regulator 12. For example, the power supplies 18 and 20 are step-down (buck) power supplies.

[0036] The power supply 18 generates a supply voltage VBUCK1 on the output connected, preferably connected, to the regulator 12. The regulator 12 therefore receives the voltage VBUCK1 on a power supply input. Similarly, the power supply 18 generates a current IBUCK1 on said output. The regulator 12 therefore receives the current IBUCK1 on a power supply input. Similarly, the power supply 20 generates a supply voltage VBUCK2 on the output connected, preferably connected, to the regulator 12. The regulator 12 therefore receives the voltage VBUCK2 on a power supply input. Similarly, the power supply 20 generates a current IBUCK2 on said output. The regulator 12 therefore receives the current IBUCK2 on a power supply input. The voltages VBUCK1 and VBUCK2 are for example lower than the supply voltage VDD, for example lower than 3.3 V.

[0037] The power supplies 18 and 20 are preferably different. The power supplies 18 and 20 are for example configured to provide different voltage or current ranges.

[0038] The device 10 is preferably configured so that only one of the power supplies 18 and 20 can be active at any one time. In other words, if the regulator 12 is powered by the power supply 18, the regulator is not powered by the power supply 20. Similarly, if the regulator 12 is powered by the power supply 20, the regulator is not powered by the power supply 18. The device 10 is thus configured in such a way that the regulator 12 does not receive unaffected currents IBUCK1 and IBUCK2 at the same time.

[0039] The device 10 is configured in such a way that the current IOUT is equal to the sum of the current IB AT and the current IBUCK, the current IBUCK corresponding to the current IBUCK1 or to the current IBUCK2, depending on the power supply 18 or 20 supplying the regulator.

[0040] The current IB AT is configured to be determined by the following equation: IB AT = [3 * IBUCK - IOS, IOS being a constant value, and [3 is for example a variable, depending for example on the current used by the load. Preferably, the greater the current required by the load, the higher the value [3.

[0041] During operation of the regulator, for example in low consumption mode, when the value [3 is such that the value of the term [3 * IBUCK is less than the value of the constant IOS, the value of the current IBAT is zero, the value of the current IB AT cannot be negative. The current IOUT is therefore equal to the current IBUCK.

[0042] During operation of the regulator, for example in low-power operating mode, when the value [3 is such that the value of the term [3 * IBUCK is greater than the value of the constant IOS, the value of the current IBAT is not zero. Thus, the current IOUT is dependent on the value of the current IBAT and the current IBUCK. The value VOUT is dependent on the value of the voltage VDD and the voltage VBUCK. The regulator is therefore powered by the supply voltage VDD and by the power supply 18 or 20 providing the voltage VBUCK.

[0043] Thus, when the current used by the load is less than a threshold, the regulator is powered by a switching power supply, and when the current used by the load is greater than the threshold, the regulator is powered by the switching power supply and the source of the supply voltage VDD. Preferably, the greater the current used by the load, the greater the proportion of the current IOUT formed by the current IBAT.

[0044] [Fig.2] represents an embodiment of the linear voltage regulator 12.

[0045] The regulator 12 comprises an error amplifier 22. The amplifier 22 is for example an operational amplifier. The amplifier 22 comprises a first input, for example a positive (+) input, on which a voltage of VREF setpoint and an IREF current. The first input is thus connected, preferably connected, to a node for applying the VREF voltage. The amplifier 22 comprises a second input, for example a negative input (-), to which a VFB loop voltage is applied. The loop voltage is dependent on the output voltage VOUT, for example is proportional to the output voltage VOUT.

[0046] The regulator 12 comprises a voltage to current converter (V to I converter) 24. The converter 24 comprises an input connected, preferably connected, to an output of the amplifier 22. The converter 24 comprises at least two outputs, each output providing a current representative of the voltage received as input by the converter 24.

[0047] The regulator 12 comprises gate control circuits 26, 28, 30. The regulator 12 comprises as many gate control circuits as there are possible power sources for the regulator 12. In other words, in the example of [Fig.l], the regulator 12 comprises the gate control circuit 30 associated with the source of the voltage VDD and the gate control circuits 26 and 28 respectively associated with the power supplies 18 and 20.

[0048] The control circuits 26, 28 and 30 are each configured to receive a current generated by the converter 24. Thus, each circuit 26, 28, 30 comprises an input connected, preferably connected, to an output of the converter 24.

[0049] Preferably, the converter 24 is configured so that the current supplied to the gate control circuits 26 and 28, i.e. the gate control circuits associated with the switching power supplies 18 and 20, is n times greater than the current supplied to the gate control circuit 30, i.e. the control circuit associated with the supply voltage source VDD. The value n is preferably an integer value, for example positive, for example greater than two.

[0050] Each gate control circuit is configured to receive the supply voltage with which it is associated. Thus, circuits 26 and 28 respectively receive voltage VBUSK1 and VBUCK2 and circuit 30 receives voltage VDD. In other words, circuit 26 comprises a supply input connected, preferably connected, to a node for applying voltage VBUCK1, for example the output of power supply 18. Circuit 28 comprises a supply input connected, preferably connected, to a node for applying voltage VBUCK2, for example the output of power supply 20. Circuit 30 comprises a supply input connected, preferably connected, to a node for applying voltage VDD.

[0051] Each gate drive circuit 26, 28, 30 generates a gate drive voltage of a transistor. Circuit 26 generates the gate drive voltage VGBUCK1 of a transistor 32. Circuit 28 generates the gate drive voltage VGBUCK2 of a transistor 34. Circuit 30 generates the gate drive voltage VGBAT of a transistor 36.

[0052] Transistor 32 is connected in series with a transistor 38 between a node for applying voltage VBUCK1 and an output node 40, on which the output voltage VOUT of regulator 12 is generated. Transistor 34 is connected in series with a transistor 42 between a node for applying voltage VBUCK2 and output node 40. Transistor 36 is connected between a node for applying voltage VDD and node 40.

[0053] The transistors 32, 34, 36, 38, 42 are for example insulated gate field effect transistors (MOSFET). For example the transistors 32, 34, 36, 38, 42 are P-channel transistors.

[0054] A conduction terminal, for example the source, of the transistor 32 is connected, preferably connected, to the node for applying the voltage VBUSK1 and another conduction terminal, for example the drain, of the transistor 32 is connected, preferably connected, to a node 44. A conduction terminal, for example the source, of the transistor 38 is connected, preferably connected, to the node 40 and another conduction terminal, for example the drain, of the transistor 38 is connected, preferably connected, to the node 44. The body of the transistor 32 is for example connected, preferably connected, to the node for applying the voltage VBUCK1. The body of the transistor 38 is for example connected, preferably connected, to the node 40.

[0055] A conduction terminal, for example the source, of the transistor 34 is connected, preferably connected, to the node for applying the voltage VBUSK2 and another conduction terminal, for example the drain, of the transistor 34 is connected, preferably connected, to a node 46. A conduction terminal, for example the source, of the transistor 42 is connected, preferably connected, to the node 40 and another conduction terminal, for example the drain, of the transistor 42 is connected, preferably connected, to the node 44. The body of the transistor 34 is for example connected, preferably connected, to the node for applying the voltage VBUCK2. The body of the transistor 42 is for example connected, preferably connected, to the node 40.

[0056] A conduction terminal, for example the source, of the transistor 36 is connected, preferably connected, to the node of application of the voltage VDD and another conduction terminal, for example the drain, of the transistor 36 is connected, preferably connected, to the node 40.

[0057] The current flowing through transistor 36, i.e. the current arriving at node 40 from the node of application of voltage VDD, is current IB AT. The current flowing through transistor 34 and transistor 42, i.e. the current arriving at node 40 from the node of application of voltage VBUCK2, is current IBUCK2. The current flowing through transistor 32 and transistor 44, i.e. the current arriving at node 40 from the node of application of voltage VBUCK1, is current IBUCK1.

[0058] The output current IOUT, that is to say the current supplied at the output of the regulator 12, corresponds to the sum of the currents IBAT, IBUCK1 and IBUCK2, the currents IBUCK1 and IBUCK2 cannot be non-zero at the same time.

[0059] The regulator 12 comprises a control circuit not shown. Said control circuit is configured to generate the control voltages of the transistors 38 and 42.

[0060] The regulator 12 comprises for example a capacitor 48 connected between the node 40 and a node for applying a reference voltage GND, for example ground. In other words, one terminal of the capacitor 48 is connected, preferably connected, to the node 40 and another terminal of the capacitor 48 is connected, preferably connected, to the node for applying the voltage GND.

[0061] The regulator comprises two resistors 50 and 52. Resistors 50 and 52 form a voltage divider bridge generating the voltage VFB. Resistors 50 and 52 are connected in series between node 40 and the voltage application node GND. One terminal of resistor 50 is connected, preferably connected, to node 40 and another terminal of resistor 50 is connected, preferably connected, to a node 54 on which the voltage VFB is generated. One terminal of resistor 52 is connected, preferably connected, to node 54 and another terminal of resistor 52 is connected, preferably connected, to the voltage application node GND. Node 54 is connected, preferably connected, to the second input of amplifier 22. Node 40 therefore corresponds to the input node of the voltage divider bridge and node 54 corresponds to the output node of the voltage divider bridge.

[0062] [Fig. 3] shows in more detail a portion of the embodiment of [Fig. 2]. More specifically, [Fig. 3] shows an embodiment of the voltage-to-current converter 24 of [Fig. 2].

[0063] The converter 24 comprises an input 56, connected, preferably connected, to the output of the amplifier 22.

[0064] The converter comprises a transistor 58. The transistor 58 is for example a MOSFET transistor, for example an N-channel transistor. The transistor 58 is controlled by the input voltage, i.e. the voltage supplied to the node 56 by the amplifier 22. The control terminal of the transistor 58 is connected, preferably connected, to the node 56.

[0065] The converter comprises a resistor 60. The resistor 60 is connected in series with the transistor 58 between a node 62 and a node for applying the reference voltage GND. In other words, a conduction terminal of the transistor 58, for example the drain, is connected, preferably connected, to the node 62 and another conduction terminal of the transistor 58, for example the source, is connected, preferably connected, to a node 64. The transistor 58 and the resistor 60 are crossed by a current IG.

[0066] The node 62 is connected to an output node 66 of the converter 24. The converter 24 provides, via the output 66, a current IMBAT. The current IMBAT is the current supplied to the control circuit 30 of [Fig.2].

[0067] The converter 24 comprises a transistor 68 and a transistor 70. The transistors 68 and 70 are preferably MOSFET transistors, for example N-channel transistors. The transistors 68 and 70 are connected in series between the node 62 and the output 66. In other words, a conduction terminal, for example the drain, of the transistor 68 is connected, preferably connected, to the output 66 and another conduction terminal, for example the source, of the transistor 68 is connected, preferably connected, to a node 72. A conduction terminal, for example the drain, of the transistor 70 is connected, preferably connected, to the node 72 and another conduction terminal, for example the source, of the transistor 70 is connected, preferably connected, to the node 62.

[0068] The node 62 is connected to an output node 74 of the converter 24. The converter 24 provides, via the output 74, a current IMBUCK1. The current IMBUCK1 is the current supplied to the control circuit 26 of [Fig.2].

[0069] The converter 24 comprises a transistor 76 and a set of transistors 78. The transistor 76 and the transistors of the set 78 are for example MOSFET transistors, for example N-channel transistors. The set of transistors 78 comprises n transistors, connected in parallel. In other words, the drains of the transistors of the set 78 are connected, preferably connected, to each other and the sources of the transistors of the set 78 are connected, preferably connected, to each other. In addition, the control terminals of the transistors of the set 78 are connected, preferably connected, to each other.

[0070] The transistor 76 and the assembly 78 are connected in series between the node 62 and the output 74. In other words, a conduction terminal, for example the drain, of the transistor 76 is connected, preferably connected, to the output 74 and another conduction terminal, for example the source, of the transistor 76 is connected, preferably connected, to a node 80. A conduction terminal, for example the drain, of the assembly 78, that is to say the drains of the transistors of the assembly 78, is connected, preferably connected, to the node 80 and another conduction terminal, for example the source, of the assembly 78 is connected, preferably connected, to the node 62.

[0071] The node 62 is connected to an output node 82 of the converter 24. The converter 24 provides, via the output 82, a current IMBUCK2. The current IMBUCK2 is the current supplied to the control circuit 28 of [Fig.2].

[0072] The converter 24 comprises a transistor 84 and a set of transistors 86. The transistor 84 and the transistors of the set 86 are for example MOSFET transistors, for example N-channel transistors. The set of transistors 86 comprises several transistors, preferably as many transistors as the set 78, preferably n transistors, connected in parallel. In other words, the drains of the transistors of the set 86 are connected, preferably connected, to each other and the sources of the transistors of the set 86 are connected, preferably connected, to each other. In addition, the control terminals of the transistors of the set 86 are connected, preferably connected, to each other.

[0073] The transistor 84 and the assembly 86 are connected in series between the node 62 and the output 82. In other words, a conduction terminal, for example the source, of the transistor 84 is connected, preferably connected, to the output 82 and another conduction terminal, for example the drain, of the transistor 84 is connected, preferably connected, to a node 88. A conduction terminal, for example the source, of the assembly 86, i.e. the sources of the transistors of the assembly 86, is connected, preferably connected, to the node 88 and another conduction terminal, for example the drain, of the assembly 86, i.e. the drains of the transistors of the assembly 86, is connected, preferably connected, to the node 62.

[0074] The control terminals of transistors 68, 76 and 84 are connected, preferably connected, to each other. Transistors 68, 76 and 84 are controlled by a VCAS voltage. The VCAS voltage is a cascode voltage, configured such that the source voltages of transistors 68, 76 and 84 are identical.

[0075] The transistor 70 and the assemblies 78 and 86 are controlled by voltages generated by the control circuit (not shown) of the regulator 12. During operation of the converter 24, the control voltage of the transistor 70 is such that the transistor 70 is on, for example is equal to the voltage VDD. During operation of the converter 24, the control voltage of the assembly 78 or 86 corresponding to the switching power supply supplying the regulator 12 is such that said assembly is on, for example is equal to the voltage VDD. The control voltage of the other assembly is such that said assembly is off, for example substantially equal to 0 V.

[0076] Preferably, the transistors of set 78 are identical to each other. Preferably, the transistors of set 86 are identical to each other. Preferably, the transistors of set 78 are identical to the transistors of set 86. Preferably, transistor 70 is identical to the transistors of sets 78 and 86.

[0077] The currents IMBUCK1 and IMBUCK2 are thus n times greater than the current IB AT. The control voltages of the assemblies 78 and 86 are such that the currents IMBUCK1 and IMBUCK2 cannot be unaffected during the same operating periods.

[0078] The current IG is equal, during operation of the device 10, to the sum of the current IMBAT and the currents IMBUCK1 and IMBUCK2, one of the currents IMBUCK1 and IMBUCK2 being zero. Thus, the non-zero current among the currents IMBUCK1 and IMBUCK2 is equal to ~[IG and the current IMBAT is equal to _^IG-

[0079] [Fig.4] shows in more detail another part of the embodiment of [Fig.2]. More precisely, [Fig.4] illustrates an embodiment of a circuit 89. The circuit 89 corresponds to the circuits 26 and 28, that is to say the gate control circuits of the transistors 32 and 34, in other words the gate control circuit associated with the supply voltages VBUCK1 and VBUCK2. The regulator 12 thus comprises two circuits 89. More generally, the regulator 12 comprises for example as many circuits 89 as there are potential supply voltages coming from a switching power supply.

[0080] The circuit 89 comprises an input 90 to which the supply voltage VBUCK is applied, corresponding to the voltage VBUCK1 or VBUCK2 depending on whether the circuit 89 corresponds to the circuit 26 or 28. The circuit 89 comprises an input 92 to which the current IMBUCK is supplied, corresponding to the current IMBUCK1 or to the current IMBUCK2. In other words, the input 92 is connected, preferably connected, to the output of the circuit 24 associated with the supply voltage VBUCK. The circuit 89 comprises an input 94 to which the reference current IREF is supplied. The current IREF is for example generated by the control circuit (not shown) described in relation to [Fig.2]. The current IREF is for example substantially constant during operation of the circuit 89. The circuit 89 comprises an output 96 to which a voltage VGBUCK is generated, corresponding to the voltage VGBUCK1 or the voltage VGBUCK2.

[0081] The circuit 89 comprises a transistor 98. The transistor 98 is for example a MOSFET transistor, for example a P-channel transistor. The transistor 98 is connected between the input 90 and the input 94. In other words, a conduction terminal of the transistor 98, for example the drain, is connected, preferably connected, to the input 94 and another conduction terminal of the transistor 98, for example the source, is connected, preferably connected, to the input 90. The control terminal of the transistor 98 is connected, preferably connected, to a node 100. The transistor 98 is for example connected as a diode. The node 100 is for example connected, preferably connected, to the input 94.

[0082] The circuit 89 comprises a transistor 102. The transistor 102 is for example a MOSFET transistor, for example a P-channel transistor. The transistor 102 is connected between the input 90 and the input 92. In other words, a conduction terminal of the transistor 102, for example the drain, is connected, preferably connected, to the input 92 and another conduction terminal of the transistor 102, for example the source, is connected, preferably connected, to the input 90. The control terminal of the transistor 102 is connected, preferably connected, to the node 100.

[0083] Circuit 89 comprises a transistor 104. Transistor 104 is for example a MOSFET transistor, for example a P-channel transistor. Transistor 104 is connected between input 90 and input 92. Transistor 104 is connected in parallel with transistor 102. In other words, one conduction terminal of transistor 104, for example the drain, is connected, preferably connected, to input 92 and another conduction terminal of transistor 104, for example the source, is connected, preferably connected, to input 90. The control terminal of transistor 104 is connected, preferably connected, to output 96.

[0084] Preferably, the surface area of the transistor 32 or 34 to which the circuit 89 corresponds is equal to m times the surface area of the transistor 104, m being a constant value, preferably a positive integer value.

[0085] The current IBUCK is equal to a times a current IC flowing through the transistor 104. The value a is equal to m when the transistor 32 or 34 is in saturation.

[0086] Preferably, transistors 98 and 102 are identical. The IMBUCK current is therefore equal to the sum of the IC current and the IREF current.

[0087] [Fig. 5] shows in more detail another part of the embodiment of [Fig. 2]. More specifically, [Fig. 5] illustrates an embodiment of a circuit 30, i.e. the gate control circuit of the transistor 36, in other words the gate control circuit associated with the supply voltage VDD.

[0088] The circuit 30 comprises an input 106 to which the supply voltage VDD is applied. The circuit 30 comprises an input 108 to which the current IMBAT is supplied. In other words, the input 108 is connected, preferably connected, to the output of the circuit 24 associated with the supply voltage VDD. The circuit 30 comprises an input 110 to which the reference current IREF is supplied. The current IREF is for example generated by the control circuit (not shown) described in relation to [Fig.2]. The current IREF is for example substantially constant during operation of the circuit 30. The circuit 30 comprises an output 112 to which the voltage VGBAT is generated.

[0089] The circuit 30 comprises a transistor 114. The transistor 114 is for example a MOSFET transistor, for example a P-channel transistor. The transistor 114 is connected between the input 106 and the input 110. In other words, a conduction terminal of the transistor 114, for example the drain, is connected, preferably connected, to the input 110 and another conduction terminal of the transistor 114, for example the source, is connected, preferably connected, to the input 106. The control terminal of the transistor 114 is connected, preferably connected, to a node 116. The transistor 114 is for example connected as a diode. The node 116 is for example connected, preferably connected, to the input 110.

[0090] The circuit 30 comprises a transistor 118. The transistor 118 is for example a MOSFET transistor, for example a P-channel transistor. The transistor 118 is connected between the input 106 and the input 110. In other words, a conduction terminal of the transistor 118, for example the drain, is connected, preferably connected, to the input 108 and another conduction terminal of the transistor 118, for example the source, is connected, preferably connected, to the input 106. The control terminal of the transistor 118 is connected, preferably connected, to the node 116.

[0091] The circuit 30 comprises a transistor 120. The transistor 120 is for example a MOSFET transistor, for example a P-channel transistor. The transistor 120 is connected between the input 106 and the input 110. The transistor 120 is connected in parallel with the transistor 118. In other words, a conduction terminal of the transistor 120, for example the drain, is connected, preferably connected, to the input 108 and another conduction terminal of the transistor 120, for example the source, is connected, preferably connected, to the input 106. The control terminal of the transistor 120 is connected to the input 110 by a switch 122. Furthermore, the control terminal of the transistor 120 is connected to the input 106 by a switch 124. In other words, a terminal of the switch 122 is connected, preferably connected, to the control terminal of the transistor 120. 120 and the other terminal of switch 122 is connected, preferably connected, to node 116.Similarly, one terminal of the switch 124 is connected, preferably connected, to the control terminal of the transistor 120 and the other terminal of the switch 124 is connected, preferably connected, to the input 106. The switches 122 and 124 are for example controlled by the control circuit not shown described in relation to [Fig.2].

[0092] The circuit 30 comprises for example a transistor 126 and a resistor 128 connected in series between the input 106 and the input 108. The transistor 126 is for example a MOSFET transistor, for example a P-channel transistor. One terminal of the resistor 128 is for example connected, preferably connected, to the input 106 and the other terminal of the resistor 106 is connected, preferably connected, to a node 130. A conduction terminal of the transistor 126, for example the source, is connected, preferably connected, to the node 130 and another conduction terminal of the transistor 126, for example the drain, is connected, preferably connected, to the input 108. The control terminal of the transistor 126 is connected, preferably connected, to the output 112 to which the voltage VGBAT is applied. The output 112 is further connected, preferably connected, to the input 108, so as to connect the transistor 126 as a diode.

[0093] Preferably, the surface area of transistor 36 is equal to m times the surface area of transistor 126. Transistor 36 is always in saturation. The current IBAT is thus equal to m times the value of the current ICB, the current ICB being the current flowing through transistor 126. In addition, the current IMBAT is equal to the sum of p times the current IREF and the current ICB, p being a constant value defined by circuit 24.

[0094] Thus, the IBAT current is configured to be determined by the following equation: IBAT = [3 * IBUCK - IOS, [3 being equal to ~~ and IOS being equal to *IREF-

[0095] When the current used by the load is low, the current IOUT is equal to the current IBUCK, the part IB AT of the current IOUT being zero.

[0096] When the voltage drop is high, that is to say when the voltage difference between VBUCK and the regulated voltage is high, the value a becomes equal to the value m, and the current IOUT is equal to the sum of the current IB AT and the current IBUCK, the current IB AT being non-zero and the current IBUCK being equal to n times the current IB AT. The current IOUT is therefore mainly supplied by the switching power supply generating IBUCK.

[0097] When the voltage drop decreases, transistor 32 or 34, corresponding to the switching power supply generating a non-zero current, enters the triode region. The value a then becomes lower than the value m. The current IBUCK then becomes lower than n times the current IB AT.

[0098] The more the voltage drop decreases, the more the transistor enters the triode region, and the value a becomes increasingly lower than the value m. Thus, the quotient of the value of the current IBUCK on the value of the current IB AT decreases until it becomes less than 1. The current IBUCK becomes less than the current IB AT. The greater part of the current IOUT is therefore provided by the current IB AT.

[0099] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, although the described embodiments include two switching power supplies, it is understood that the device may include a single switching power supply, or a larger number of switching power supplies.

[0100] Furthermore, although the described embodiments comprise a transistor 70 and assemblies 78 and 86, the transistor 70 may be replaced by a set of transistors, preferably identical, connected in parallel such as the assemblies 78 and 6. The assemblies 78 and 86 then comprise n times more transistors than the assembly 70.

[0101] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

1. Claims Electronic device (10) comprising: - a first power supply input (16) configured to receive a first supply voltage (VDD); - a first switching power supply (18, 20) comprising a first output, the first switching power supply (18, 20) being configured to generate a second supply voltage (VBUCK, VBUCK1, VBUCK2) on the first output; and - a linear voltage regulator (12) configured to supply a load (14) included in the device, the regulator (12) being configured to receive the first (VDD) and second (VBUCK, VBUCK1, VBUCK2) supply voltages, the regulator (12) comprising: • a first transistor (36) connected between the first power supply input (16) and an output node of the regulator (40); - a second transistor (32, 34) connected between the output of the first switching power supply (18, 20), and the output node of the regulator (40); - an error amplifier (22) configured to receive as input a setpoint voltage (VREF) and a voltage (VFB) representative of the output voltage (VOUT) of the regulator and configured to generate an error voltage; - a voltage to current converter (24), comprising an input configured to receive the error voltage and generating a fifth current (IMBUCK, IMBUCK1, IMBUCK2) on a second output (66) of the converter (24) and a sixth current (IMBAT) on a third output (74, 82) of the converter (24); and - a first gate control circuit (30) controlling the first transistor (36) and a second gate control circuit (26, 28) controlling the second transistor (32, 34), the converter being configured to supply the fifth current (IMBUCK, IMBUCK1, IMBUCK2) to the first control circuit (30) and the sixth current (IMBAT) to the second control circuit (26, 28), the regulator (12) being configured so that, when the current drawn by the load is below a threshold, a first output current (IOUT), supplied to the load (14) by the output node of the regulator (12), is equal to a third current (IBUCK, IBUCK1, IBUCK2) flowing through the second transistor (32, 34) and that, when said current is above the threshold, the first output current (IOUT) is equal to the sum of a fourth current (IBAT) flowing through the first transistor (36) and the third current (IBUCK, IBUCK1, IBUCK2) flowing through the second transistor (32, 34), the fourth current (IBAT) being non-zero, wherein the second gate control circuit (26, 28, 89) comprises a sixth transistor (104) connected as a diode between the second output of the converter (92) and the output of the first switching power supply (90), the control terminal of the sixth transistor (104) being connected to an output (96) of the second control circuit (26, 28, 89).

2. A device according to claim 1, wherein the regulator (12) is configured so that when the current drawn by the load is above the threshold, the greater the current drawn, the greater the fourth current (IBAT) flowing through the first transistor (36).

3. Device according to claim 1 or 2, in which the regulator (12) comprises a voltage divider bridge (50, 52) whose input is connected to the output node (40) of the regulator (12) and whose output is connected to an input (54) of the amplifier (22) so as to provide the voltage representative of the output voltage (VFB).

4. Device according to any one of claims 1 to 3, in which the converter (24) comprises a third transistor (58) connected between a first node (62) and a node for applying a reference voltage (GND), the third transistor (58) being configured to be controlled by the error voltage, the converter (24) comprising a fourth transistor (70) connecting the first node (62) to the second output (66) and at least a fifth (78, 86) transistor connecting the first node (62) to the third output (74, 82).

5. Device according to claim 4, in which the first node (62) and the third output (74, 82) are connected by a set of at least two fifth transistors (78, 86) connected in parallel.

6. Device according to any one of claims 1 to 5, in which the second control circuit (26, 28, 89) comprises: - a seventh transistor (98) connected as a diode between an input (94) configured to receive a setpoint current (IREF) and the output of the first switching power supply (90), and - an eighth transistor (102) connected between the second output of the converter (92) and the output of the first switching power supply (90), the control terminal of the eighth transistor (102) being connected to the control terminal of the seventh transistor (98).

7. A device according to any one of claims 1 to 6, wherein the first gate driver circuit (30) comprises a ninth transistor (126) connected as a diode, the ninth transistor (126) and a resistor (128) being connected between the first output of the converter (108) and the first input of the device (16, 106), the control terminal of the ninth transistor (126) being connected to an output (112) of the first control circuit (30).

8. Device according to claim 7, in which the first control circuit (30) comprises: - a tenth transistor (114) connected as a diode between an input (110) configured to receive a reference current (IREF) and the first input of the device (16, 106), and - an eleventh transistor (118) connected between the first output of the converter (108) and the first input (16, 106) of the device, the control terminal of the tenth transistor (114) being connected to the control terminal of the eleventh transistor (118).

9. Device according to claim 8, in which the first control circuit (30) comprises: - a twelfth transistor (120) connected between the first output (108) of the converter and the first input (16, 106) of the device; - a first switch (122) connected between the control terminal of the twelfth transistor (120) and the input (110) configured to receive the reference current (IREF); and - a second switch (124) connected between the control terminal of the twelfth transistor (120) and the input (110) configured to receive the reference current (IREF);

10.

11. control of the twelfth transistor (120) and the first input (16, 106) of the device. Device according to any one of claims 1 to 9, wherein the device comprises at least one second switching power supply (18, 20), and comprises, for each second switching power supply (18, 20), a second transistor (32, 34), connected between the output of the corresponding second switching power supply and the output node (40), the regulator (12) being configured so that only a current (IBUCK1, IBUCK2) passing through one of the second transistors is non-zero at the same time. Method for controlling an electronic device (10) comprising: - a first supply input (16) receiving a first supply voltage (VDD); - a first switching power supply (18, 20) comprising a first output, the first switching power supply (18, 20) generating a second supply voltage (VBUCK, VBUCK1, VBUCK2) on the first output; and - a linear voltage regulator (12) supplying a load (14) included in the device, the regulator (12) receiving the first (VDD) and second (VBUCK, VBUCK1, VBUCK2) supply voltages, the regulator (12) comprising: • a first transistor (36) connected between the first supply input (16) and an output node of the regulator (40); - a second transistor (32, 34) connected between the output of the first switching power supply (18, 20), and the output node of the regulator (40); - - an error amplifier (22) configured to receive in input a reference voltage (VREF) and a voltage (VFB) representative of the output voltage (VOUT) of the regulator and configured to generate an error voltage; - a voltage to current converter (24), comprising an input configured to receive the error voltage and generating a fifth current (IMBUCK, IMBUCK1, IMBUCK2) on a second output (66) of the converter (24) and a sixth current (IMBAT) on a third output (74, 82) of the converter (24); and • a first gate control circuit (30) controlling the first transistor (36) and a second gate control circuit (26, 28) controlling the second transistor (32, 34), the converter being configured to supply the fifth current (IMBUCK, IMBUCK1, IMBUCK2) to the first control circuit (30) and the sixth current (IMBAT) to the second control circuit (26, 28), when the current, drawn by the load, is below a threshold, a first output current (IOUT), supplied to the load (14) by the output node of the regulator (12), is equal to a third current (IBUCK, IBUCK1, IBUCK2) flowing through the second transistor (32, 34) and, when said current is above the threshold, the first output current (IOUT) is equal to the sum of a fourth current (IBAT) flowing through the first transistor (36) and the third current (IBUCK, IBUCK1, IBUCK2) flowing through the second transistor (32, 34), the fourth current (IBAT) being non-zero.

12. Method according to claim 11 applied to a device according to any one of claims 1 to 10.

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