Method for manufacturing an electronic device

Abstract

Method for manufacturing an electronic device. This description relates to a method for manufacturing an electronic device comprising the following successive steps: a) forming a structure comprising a first wafer, an active stack (103) disposed on the first wafer, and a first interconnect stack (105) covering a face of the active stack opposite the first wafer; and b) transferring the structure onto a second wafer (111) by molecular bonding to the side of a face of the first interconnect stack opposite the first wafer, the second wafer having a diameter strictly larger than that of the first wafer. Figure for the abstract: Fig. 1C

Description

Title of the invention: Method for producing an electronic device Technical field

[0001] The present description relates generally to electronic devices. The present description relates more particularly to methods for producing electronic devices, for example optoelectronic devices comprising light-emitting diodes. Prior art

[0002] Methods for producing electronic devices, for example using substrates considered to be unconventional, for example substrates of relatively small dimensions and / or substrates made of sapphire or of an IILV semiconductor material have been proposed. However, these methods suffer from various drawbacks. Summary of the invention

[0003] There is a need to improve known methods of producing electronic devices.

[0004] For this, one embodiment provides a method for producing an electronic device comprising the following successive steps: a) forming a structure comprising a first wafer, an active stack disposed on the first wafer, and a first interconnect stack covering a face of the active stack opposite the first wafer; and b) transferring the structure onto a second wafer by molecular bonding on the side of a face of the first interconnection stack opposite the first wafer, the second wafer having a diameter strictly greater than that of the first wafer.

[0005] According to one embodiment, the method further comprises, after step b), a step c) of cutting the active stack and the first interconnection stack into vignettes.

[0006] According to one embodiment, the method further comprises, between steps b) and c), a step of eliminating the first wafer.

[0007] According to one embodiment, the method further comprises, after the step of removing the first wafer and prior to step c), steps of depositing a dielectric layer coating the first interconnection stack and the active stack and of planarizing said layer.

[0008] According to one embodiment, the method further comprises, after the step of planarizing the dielectric layer and prior to step c), a step of transferring the structure comprising the second wafer, the first interconnection stack, the active stack and the dielectric layer onto a third wafer by molecular bonding on the side of a face of the dielectric layer opposite the second wafer.

[0009] According to one embodiment, the third plate has a diameter strictly greater than that of the first plate.

[0010] According to one embodiment, the method further comprises, after the step of bonding to the third wafer and prior to step c), a step of removing the second wafer.

[0011] According to one embodiment, the method further comprises, after the step of eliminating the second wafer and before step c), a step of forming a second interconnection stack on the side of a face of the first interconnection stack opposite the third wafer.

[0012] According to one embodiment, the method further comprises, after step c), a step of transferring the stickers onto a fourth wafer by molecular bonding on the side of a face of the second interconnection stack opposite the third wafer.

[0013] According to one embodiment, the method further comprises, after step c), a step d) of transferring the vignettes onto a fifth wafer by molecular bonding on the side of a face of the active stack opposite the second wafer.

[0014] According to one embodiment, the method further comprises, after step d), a step of eliminating the second wafer.

[0015] According to one embodiment, the method further comprises, after step d), a step e) of forming a third interconnection stack, covering a face of the first interconnection stack opposite the fifth wafer.

[0016] According to one embodiment, the method further comprises, after step e), a step f) of transferring the structure comprising the fifth wafer, the first interconnection stack, the active stack and the third interconnection stack onto a sixth wafer by molecular bonding on the side of a face of the third interconnection stack opposite the second wafer.

[0017] According to one embodiment, the first plate has a diameter equal to approximately 150 mm.

[0018] According to one embodiment, the second plate has a diameter equal to approximately 200 or 300 mm.

[0019] According to one embodiment, the active stack is an active stack of light-emitting diodes.

[0020] According to one embodiment, the first wafer is made of sapphire or an inorganic semiconductor material other than silicon, preferably a III-V semiconductor material. Brief description of the drawings

[0021] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0022] [Fig.lA], [Fig.lB], [Fig.lC], [Fig.lD], [Fig.lE], [Fig.lF] and [Fig.lG] are sectional views illustrating, schematically and partially, structures obtained at the end of successive steps of an example of a method for producing an optoelectronic device according to an embodiment;

[0023] [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D], [Fig.2E] and [Fig.2F] are sectional views illustrating, schematically and partially, structures obtained at the end of successive steps of an example of a method for producing an optoelectronic device according to another embodiment; and

[0024] [Fig.3A] and [Fig.3B] are sectional views illustrating, schematically and partially, structures obtained at the end of successive steps of a variant of the method for producing an optoelectronic device of FIGS. 2A to 2F. Description of the embodiments

[0025] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0026] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the production of the stacks of light-emitting diodes and their control circuits has not been detailed, the production of such stacks and such circuits being within the scope of the person skilled in the art from the indications of the present description.

[0027] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0028] In the following description, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or orientation qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, reference is made to the orientation of the figures.

[0029] Unless otherwise specified, the expressions “about”, “approximately”, “substantially”, and “of the order of” mean to within 10%, preferably to within 5%.

[0030] [Fig.lA], [Fig.lB], [Fig.lC], [Fig.lD], [Fig.lE], [Fig.lF] and [Fig.lG] are sectional views illustrating, schematically and partially, structures obtained at the end of successive steps of an example of a method for producing an optoelectronic device according to one embodiment.

[0031] [Fig. 1A] illustrates more particularly a structure obtained at the end of a step of forming, on one face of a wafer 101 (the upper face of the wafer 101, in the orientation of [Fig. 1A]), an active stack 103, for example an active diode stack, for example an active light-emitting diode stack and, on the side of a face of the active light-emitting diode stack 103 opposite the wafer 101 (the upper face of the active light-emitting diode stack 103, in the orientation of [Fig. 1A]), an interconnection stack 105.Active stack means a stack of layers comprising at least one semiconductor layer, for example an emissive layer, in the case of a light-emitting diode, or a photoelectric conversion layer, in the case of a photodiode, the active stack being able to further comprise one or more charge injection layers (electrons or holes) and / or one or more charge transport layers. In other electronic devices such as power diodes or transistors, the active stack corresponds for example to the semiconductor layers defining the PN junction of the diode, or to a layer in which a channel region of the transistor is formed.

[0032] In the example shown, the wafer 101 acts as a mechanical support, or handle, and is in particular devoid of electrical functionalities. The wafer 101 is for example a substrate having a general disc shape. In this case, the wafer 101 has for example a diameter less than or equal to approximately 150 mm, for example equal to approximately 150 mm. The wafer 101 is for example made of monocrystalline silicon, sapphire or an inorganic semiconductor material other than silicon, for example an IILV compound comprising at least a first element from group III, a second element from group V and, optionally, a third element, for example a group III element other than the first element. By way of example, the wafer 101 is made of gallium nitride (GaN).

[0033] In the example illustrated in [Fig.lA], the active stack of light-emitting diodes 103 covers the upper face of the wafer 101. Although this has not been detailed in the figures, the active stack of light-emitting diodes 103 comprises, for example, an active layer, or emissive layer. The active layer of the stack of light-emitting diode 103 is for example interposed between, on the one hand, a first stack comprising for example hole injection, hole transport and / or electron blocking layers and, on the other hand, a second stack comprising for example electron injection, electron transport and / or hole blocking layers. By way of example, the active stack of light-emitting diode 103 is formed by epitaxy from the upper face of the wafer 101.

[0034] In the example shown, the interconnection stack 105 covers the face of the active stack of light-emitting diodes 103 opposite the wafer 101. The interconnection stack 105 comprises, for example, alternating dielectric and conductive layers. Inside the conductive layers are, for example, formed electrical connection tracks and / or terminals symbolized, in [Fig. 1A], by disjoint rectangles.

[0035] In the example shown, alignment marks 107 are formed in the interconnect stack 105. The alignment marks 107 extend, for example, through the thickness of the interconnect stack 105 from the upper face of the interconnect stack 105. In [Fig. 1A], the alignment marks 107 have been symbolized by triangles, it being understood that the alignment marks 107 may, in practice, have any shape. For example, the upper face of the stack 105 is prepared by chemical and mechanical polishing (CMP), for example, so that the face has a nanotopography and roughness compatible with direct bonding.

[0036] [Fig.lB] illustrates more particularly a structure obtained at the end of a step of forming, on one face of another wafer 111 (the upper face of the wafer 111, in the orientation of [Fig.lB]), a dielectric layer 113.

[0037] In the example shown, the wafer 111 acts as a mechanical support, or handle, and is in particular devoid of electrical functionalities. According to one embodiment, the wafer 111 differs from the wafer 101 previously described in relation to [Fig. 1 A] in that the wafer 111 has a diameter strictly greater than that of the wafer 101. The wafer 111 has, for example, a diameter equal to approximately 200 or 300 mm. The wafer 111 may furthermore be made of a material different from that of the wafer 101. For example, the wafer 111 is made of monocrystalline silicon.

[0038] In the orientation of [Fig.lB], the dielectric layer 113 covers the upper face of the wafer 111. The dielectric layer 113 is for example made of an oxide, for example silicon dioxide (SiO2). By way of example, the dielectric layer 113 is first deposited on the wafer 111 and then planarized, for example by chemical-mechanical polishing, so that its face opposite the wafer 111 (the upper face of layer 113, in the orientation of [Fig.lB]) has a topography suitable for the subsequent production of molecular bonding.

[0039] In the example shown, alignment marks 114 are formed in the dielectric layer 113. The alignment marks 114 extend, for example, in the thickness of the dielectric layer 113 from the upper face of the layer 113. In [Fig. 1B], the alignment marks 114 have been symbolized by triangles, it being understood that the alignment marks 114 may, in practice, have any shape.

[0040] [Fig.lC] illustrates more particularly a structure obtained at the end of subsequent steps of transferring the structure previously described in relation to [Fig.lA] onto the structure previously described in relation to [Fig.lB], of eliminating the wafer 101, and of depositing a dielectric layer 115.

[0041] By way of example, the structure previously described in relation to [Fig.lA] is turned over with respect to the orientation of [Fig.lA] and then brought into contact, by the face of the interconnection stack 105 opposite the wafer 101 (the lower face of the interconnection stack 105, in the orientation of [Fig.lC]), with the dielectric layer 113. During this step, the structure comprising the wafer 101, the active light-emitting diode stack 103 and the interconnection stack 105 is fixed to the wafer 111. By way of example, the fixing on the wafer 111 is obtained by molecular bonding between the two surfaces brought into contact. During a prior step, the surfaces of the layers 115 and 133 are for example prepared so as to be made compatible with the bonding.

[0042] During bonding, the structure previously described in relation to [Fig. 1A] is for example aligned with respect to the structure previously described in relation to [Fig. 1B] with an alignment precision of the order of 100 μm. More precisely, during this step, the alignment marks 107 are aligned with respect to the alignment marks 114.

[0043] For example, the wafer 101 is removed by grinding, by wet etching or, for example in the case where the wafer 101 is made of sapphire, by a laser lift-off technique (LLO).

[0044] Once the wafer 101 has been removed, the dielectric layer 115 is for example deposited on the structure on the side of the face of the dielectric layer 113 opposite the wafer 111 (the upper face of the dielectric layer 113, in the orientation of [Fig. 1C]). The dielectric layer 115 is for example then planarized, for example by chemical-mechanical polishing, so that its upper face has a topography suitable for the subsequent production of molecular bonding. In the example illustrated, the dielectric layer 115 covers parts of the dielectric layer 113 not coated with the interconnect stack 105, the sides of the interconnect stack 105, and the sides and the upper face of the active light-emitting diode stack 103. For example, the dielectric layer 115 is made of the same material as the dielectric layer 113, for example silicon dioxide.

[0045] [Fig. 1D] illustrates more particularly a structure obtained at the end of a subsequent step of transferring the structure previously described in relation to [Fig. 1C] onto a structure comprising a wafer 131 coated, on one of its faces (the upper face of the wafer 131, in the orientation of [Fig. 1D]), with a dielectric layer 133. The wafer 131 and the dielectric layer 133 are for example identical or analogous, respectively, to the wafer 111 and the dielectric layer 113 previously described in relation to [Fig. 1B].

[0046] By way of example, the structure previously described in relation to [Fig.lC] is turned over with respect to the orientation of [Fig.lC] and then brought into contact, by the face of the dielectric layer 115 opposite the wafer 111 (the lower face of the dielectric layer 115, in the orientation of [Fig.lD]), with the dielectric layer 133. During this step, the structure previously described in relation to [Fig.lC] is fixed to the wafer 131. By way of example, the fixing on the wafer 131 is obtained by molecular bonding between the two surfaces brought into contact.

[0047] During the bonding step, the structure previously described in relation to [Fig. 1C] is for example aligned with respect to the wafer 131 with an alignment precision of between 2 and 50 μm.

[0048] [Fig. 1E] illustrates more particularly a structure obtained at the end of subsequent steps of eliminating the wafer 111 and the dielectric layer 113, and of forming an interconnection stack 135.

[0049] For example, the wafer 111 is removed by grinding, by wet chemical etching or by a laser detachment technique. The dielectric layer 113 is for example first partially removed by grinding, then the remaining part of the dielectric layer 113 is removed by chemical-mechanical polishing so as to avoid any risk of damage to the interconnection stack 105.

[0050] In the example shown, the face of the dielectric layer 115 opposite the wafer 131 (the upper face of the dielectric layer 115, in the orientation of [Fig. 1E]), is flush with the face of the interconnection stack 105 opposite the wafer 131 (the upper face of the interconnection stack 105, in the orientation of [Fig. 1E]).

[0051] In the example illustrated in [Fig.lE], the interconnect stack 135 covers the faces of the interconnect stack 105 and the dielectric layer 115 opposite the wafer 131 (the upper faces of the interconnect stack 105 and the dielectric layer 115 in the orientation of [Fig.lE]). The stack interconnection 135 comprises, for example, dielectric layers, for example made of silicon dioxide, and conductive layers, for example made of copper, alternating inside which are formed electrical connection tracks and / or terminals symbolized, in [Fig.lE], by disjoint rectangles.

[0052] By way of example, the interconnection stack 135 is produced by implementing steps of a “damascene” type method. The interconnection stack 135 is, in the example shown, aligned with respect to the alignment marks 107 previously formed in the interconnection stack 105. This makes it possible in particular to ensure that the electrical connection tracks and / or terminals of the interconnection stack 135 are connected to the connection tracks and / or terminals of the underlying interconnection stack 105.

[0053] In the example shown, alignment marks 137 are formed in the interconnect stack 135. The alignment marks 137 extend, for example, through the thickness of the interconnect stack 135 from a face of the interconnect stack 135 opposite the wafer 131 (the upper face of the stack 135, in the orientation of [Fig. 1E]). In [Fig. 1E], the alignment marks 137 have been symbolized by squares, it being understood that the alignment marks 137 may, in practice, have any shape.

[0054] [Fig. 1F] illustrates more particularly a structure obtained at the end of an optional subsequent step of cutting (“dicing”, in English), over its entire thickness, of the structure previously described in relation to [Fig. 1E] so as to form vignettes 141.

[0055] In the example shown, each vignette 141 comprises a portion of the wafer 131 and a stack comprising, in order, from the wafer 131, a portion of the dielectric layer 133, a portion of the dielectric layer 115, a portion of the active light-emitting diode stack 103, a portion of the interconnection stack 105 and a portion of the interconnection stack 135.

[0056] By way of example, each vignette 141 has, in top view, a periphery of substantially rectangular or square shape, and a surface area of ​​between a few square micrometers and a few square centimeters.

[0057] Although four vignettes 141 have been shown in [Fig. 1F], the cutting step can of course lead to the formation of a number of vignettes 141 other than four, for example several tens or several hundreds of vignettes 141. Each vignette 141 corresponds for example to an elementary light-emitting diode, that is to say a light-emitting diode that can be controlled independently of other light-emitting diodes.

[0058] In the case where the cutting step is implemented, the alignment marks 137 formed in the interconnect stack 135 are more precisely marks alignment marks 137 are more precisely alignment marks called "die to wafer" (DTW). Otherwise, that is to say if the structure previously described in relation to [Fig. 1E] is not cut into vignettes 141, this structure being for example intended to be transferred as is onto another wafer, the alignment marks 137 are more precisely alignment marks called "wafer to wafer" (WTW).

[0059] By way of example, the upper face of the layer 135 is previously prepared so as to be made compatible with hybrid bonding operations.

[0060] [Fig. 1G] illustrates more particularly a structure obtained at the end of a step of transferring the vignettes 141 onto a structure comprising a wafer 151, an active region 153, for example formed in and on the wafer 151, and an interconnection stack 155 covering a face of the active region 153 opposite the wafer 151 (the upper face of the active region 153, in the orientation of [Fig. 1G]).

[0061] The plate 151 is, for example, similar or identical to the plates 111 and 131.

[0062] Although this has not been detailed in [Fig.lG], the active region 153 comprises, for example, transistors for controlling the vignettes 141, for example transistors intended to control the part of the active stack of light-emitting diodes 103 of each vignette 141.

[0063] The interconnection stack 155 comprises, for example, dielectric layers, for example made of silicon dioxide, and conductive layers, for example made of copper, alternating inside which are formed electrical connection tracks and / or terminals symbolized, in [Fig. 1G], by disjoint rectangles. By way of example, the upper face of the interconnection stack 155 is previously prepared so as to have a nanotopography compatible with hybrid molecular bonding, for example using copper / oxide surfaces.

[0064] The wafer 151, the active region 153 and the interconnection stack 155 form, for example, a substrate 157 of the CMOS type (from the English “Complementary Metal-Oxide-Semiconductor”).

[0065] By way of example, the vignettes 141 previously described in relation to [Fig. 1F] are turned over with respect to the orientation of [Fig. 1F] and then brought into contact, by the face of the interconnection stack 135 opposite the wafer 131 (the lower face of the interconnection stack 135, in the orientation of [Fig. 1G]), with the interconnection stack 155. During this step, the vignettes 141 are fixed to the wafer 151. By way of example, the fixing on the wafer 151 is obtained by molecular bonding between the two surfaces brought into contact. The transfer of the vignettes 141 onto the wafer 151 is for example carried out by a “pick and place” method, each vignette being transferred individually, or by a collective transfer method.

[0066] During the bonding step, the stickers 141 are for example aligned with respect to the wafer 151 with an alignment precision of between 500 nm and 1.5 μm, for example equal to approximately 700 nm. For this, alignment marks 159, for example similar or identical to the alignment marks 137, are formed in the interconnection stack 155, on the side of a face of the interconnection stack 155 opposite the wafer 151. In [Fig. 1G], the alignment marks 159 have been symbolized by squares, it being understood that the alignment marks 159 can, in practice, have any shape. During the alignment operation, the alignment marks 137 of the stickers 141 are substantially aligned with respect to the alignment marks 159 of the CMOS substrate 157.This makes it possible in particular to ensure that the electrical connection tracks and / or terminals of the interconnection stack 135, therefore the electrical connection tracks and / or terminals of the interconnection stack 105, are connected to the connection tracks and / or terminals of the underlying interconnection stack 155.

[0067] As a variant, in the case where the cutting step previously described in relation to [Fig. 1F] is omitted, the structure previously described in relation to [Fig. 1E] is for example transferred, by molecular bonding, onto the CMOS substrate 157 in a manner analogous to that set out above for the vignettes 141.

[0068] An advantage of the method previously described in relation to figures 1A to 1G lies in the fact that it allows, in order to produce the interconnection stack 155 of the CMOS substrate 157, the use of very precise lithography techniques making it possible in particular to overcome constraints linked to the precision of alignment of the vignettes 141, or of the structure of [Fig. 1E], with respect to the CMOS substrate 157.

[0069] One could have considered replacing the wafer 101, having lateral dimensions smaller than those of the wafer 111, with a wafer made of a material other than silicon, for example sapphire or an IILV semiconductor material, and having lateral dimensions substantially equal to those of the wafer 111. This would, however, require costly, long and environmentally unfriendly technological developments to enable the formation of the active stack of light-emitting diodes 103 on such a substrate. Furthermore, one could have considered carrying out the transfer of the structure of [Fig. 1A] onto a wafer similar to the wafer 111 but having dimensions substantially equal to those of the wafer 101. However, existing molecular bonding methods require the implementation of preliminary planarization steps which are currently incompatible with wafers having a diameter less than or equal to 150 mm.

[0070] Subsequent steps of the manufacturing method of the optoelectronic device can then be implemented from the structure illustrated in [Fig.lG], the CMOS substrate 157 being for example intended to be kept at the end of these steps.

[0071] [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D], [Fig.2E] and [Fig.2F] are sectional views illustrating, schematically and partially, structures obtained at the end of successive steps of an example of a method for producing an optoelectronic device according to another embodiment.

[0072] [Fig. 2A] illustrates more particularly a structure obtained at the end of steps identical or analogous to the steps previously described in relation to figures 1A to 1C. Although this has not been shown in [Fig. 2A] in order not to overload the drawing, the structure comprises for example the alignment marks 107 and 114 previously described in relation to figures 1A and 1B.

[0073] The structure illustrated in [Fig.2A] differs from the structure illustrated in [Fig.1C] in that the structure illustrated in [Fig.2A] further includes alignment marks 207 formed in the dielectric layer 115.

[0074] In the example shown, the alignment marks 207 are formed on the side of a face of the dielectric layer 115 opposite the wafer 111. The alignment marks 207 are for example placed and aligned according to the position of the electrical connection tracks and / or terminals of the interconnection stack 105. In [Fig.2A], the alignment marks 207 have been symbolized by triangles, it being understood that the alignment marks 207 can, in practice, have any shape.

[0075] [Fig.2B] illustrates more particularly a structure obtained at the end of a subsequent step of cutting, over its entire thickness, the structure previously described in relation to [Fig.2A] so as to form vignettes 211.

[0076] In the example shown, each vignette 211 comprises a portion of the wafer 111 and a stack comprising, in order, from the wafer 111, a portion of the dielectric layer 113, a portion of the interconnection stack 105, a portion of the active light-emitting diode stack 103 and a portion of the dielectric layer 115.

[0077] By way of example, each vignette 211 has, in top view, a circumference of substantially rectangular or square shape, and a surface area between a few square micrometers and a few square millimeters.

[0078] Although four vignettes 211 have been shown in [Fig.2B], the cutting step can of course lead to the formation of a number of vignettes 211 other than four, for example several tens or several hundreds of vignettes 211. Each vignette 211 corresponds for example to an elementary light-emitting diode, that is to say a light-emitting diode that can be controlled independently of other light-emitting diodes.

[0079] [Fig.2C] illustrates more particularly a structure obtained at the end of subsequent steps: - transfer of the vignettes 211 onto a structure comprising a plate 221 coated, on one of its faces (the upper face of the plate 221, in the orientation of [Fig.2C]), with a dielectric layer 223; - elimination of platelet 111; and - depositing another dielectric layer 225.

[0080] The wafer 221 and the dielectric layer 223 are for example analogous, respectively, to the wafer 111 and the dielectric layer 113 previously described in relation to [Fig. 1B]. By way of example, the dielectric layer 223 is made of silicon dioxide.

[0081] By way of example, the vignettes 211 previously described in relation to [Fig.2B] are turned over with respect to the orientation of [Fig.2B] and then brought into contact, by the face of the dielectric layer 115 opposite the wafer 111 (the lower face of the dielectric layer 115, in the orientation of [Fig.2C]), with the dielectric layer 223. During this step, the vignettes 211 are fixed to the wafer 221. By way of example, the fixing on the wafer 221 is obtained by molecular bonding between the two surfaces brought into contact.

[0082] During the bonding step, the vignettes 211 are for example aligned with respect to alignment marks 227 previously formed in the dielectric layer 223 so that the alignment marks 207 of the vignettes 211 are positioned substantially opposite the alignment marks 227. By way of example, the alignment precision of the vignettes 211 with respect to the wafer 221 is between 2 and 50 μm.

[0083] For example, the wafer 111 is removed by grinding, by wet chemical etching or by a laser detachment technique.

[0084] Once the wafer 111 has been removed, the dielectric layer 225 is for example deposited on the structure on the side of the face of the dielectric layer 223 opposite the wafer 221 (the upper face of the dielectric layer 223, in the orientation of [Fig.2C]). The dielectric layer 225 is for example then planarized, for example by chemical-mechanical polishing, so that its upper face has a topography suitable for the subsequent production of molecular bonding. In the example illustrated, the dielectric layer 225 coats parts of the dielectric layer 223 not coated with the vignettes 211, as well as the sides and the upper face of each vignette 211. By way of example, the dielectric layer 225 is made of the same material as the dielectric layer 223, for example silicon dioxide.

[0085] In the example shown, the wafer 221 comprises alignment marks 229. In the orientation of [Fig.2C], the alignment marks 229 extend vertically in the thickness of the wafer 221 from its upper face.

[0086] [Fig.2D] illustrates more particularly a structure obtained at the end of a step subsequent planarization of the structure previously described with [Fig.2C] on the side of a face of the structure opposite the plate 221 (the upper face of the structure, in the orientation of [Fig.2C]).

[0087] For example, the dielectric layers 225 and 113 are planarized first by grinding, then by chemical-mechanical polishing. At the end of these operations, the face of the dielectric layer 225 opposite the wafer 211 (the upper face of the layer 225, in the orientation of [Fig. 2D]) is flush with the face of the interconnection stack 105 opposite the wafer 211 (the upper face of the interconnection stack 105, in the orientation of [Fig. 2D]).

[0088] [Fig.2E] illustrates more particularly a structure obtained at the end of a subsequent step of forming an interconnection stack 235.

[0089] In the example illustrated in [Fig.2E], the interconnection stack 235 covers the faces of the interconnection stack 105 and the dielectric layer 225 opposite the wafer 221 (the upper faces of the interconnection stack 105 and the dielectric layer 225 in the orientation of [Fig.2E]). The interconnection stack 235 comprises, for example, alternating dielectric layers, for example made of silicon dioxide, and conductive layers, for example made of copper, inside which are formed electrical connection tracks and / or terminals symbolized, in [Fig.2E], by disjoint rectangles.

[0090] By way of example, the interconnection stack 235 is produced by implementing steps of a “damascene” type method. The interconnection stack 235 is, in the example shown, aligned with respect to the alignment marks 229 previously formed in the wafer 221. This makes it possible in particular to ensure that the electrical connection tracks and / or terminals of the interconnection stack 235 are connected to the connection tracks and / or terminals of the underlying interconnection stack 105.

[0091] In the example shown, alignment marks 237 are formed in the interconnection stack 235, on the side of a face of the interconnection stack 235 opposite the wafer 221. In [Fig.2E], the alignment marks 237 have been symbolized by stars, it being understood that the alignment marks 237 may, in practice, have any shape.

[0092] [Fig.2F] illustrates more particularly a structure obtained at the end of a subsequent step of transfer, onto the structure previously described in relation to [Fig.2E], of the CMOS substrate 157 previously described in relation to [Fig.1G].

[0093] As an example, the CMOS substrate 157 is brought into contact, by the face of the interconnection stack 155 opposite the wafer 151 (the lower face of the interconnection stack 155, in the orientation of [Fig.2F]), with the interconnection stack 235. During this step, the CMOS substrate 157 is fixed to the plate 221. For example, the fixing on the plate 221 is obtained by molecular bonding between the two surfaces brought into contact.

[0094] During the bonding step, the CMOS substrate 157 is for example aligned with respect to the structure previously described in relation to [Fig. 2E]. For this, alignment marks 247 are for example previously formed in the interconnection stack 155 so that, at the end of the transfer step, the alignment marks 247 are located substantially opposite the alignment marks 237. The CMOS substrate 157 is for example, as illustrated in [Fig. 2F], devoid of the alignment marks 159.

[0095] The method described above in relation to Figures 2A to 2F has advantages similar to the method described previously in relation to Figures 1A to 1G. The method of Figures 2A to 2F makes it possible in particular to overcome drawbacks linked to the development of a method for forming a stack of light-emitting diodes on a wafer having a diameter strictly greater than 150 mm, for example of the order of 200 or 300 mm. The method of Figures 2A to 2F also makes it possible to implement molecular bonding of the active stack of light-emitting diodes 103 on the CMOS substrate 157.

[0096] Subsequent steps of the manufacturing method of the optoelectronic device can then be implemented from the structure illustrated in [Fig.2F], the CMOS substrate 157 being for example intended to be kept at the end of these steps.

[0097] [Fig.3A] and [Fig.3B] are sectional views illustrating, schematically and partially, structures obtained at the end of successive steps of a variant of the method for producing an optoelectronic device of FIGS. 2A to 2F.

[0098] [Fig.3A] illustrates more particularly a structure obtained at the end of a formation step, from a structure similar to that previously described in relation to [Fig.2C], of interconnection stacks 301 located respectively directly above the vignettes 211.

[0099] By way of example, openings extending from the upper face of the dielectric layer 225 to the interconnection stack 105 of each sticker 211 are first made directly above each sticker 211. The interconnection stacks 301 are for example then made inside the openings, directly above the stickers 211. The interconnection stacks 301 are, in the example shown, aligned with alignment marks 303 previously formed in the interconnection stack 105. This makes it possible in particular to ensure that the electrical connection tracks and / or terminals of the interconnection stack 301 are connected to the connection tracks and / or terminals of the underlying interconnection stack 105.

[0100] In the example shown, the plate 221 is devoid of alignment marks. 229 and alignment marks 305 are formed in the dielectric layer 225. In [Fig.3A], the alignment marks 305 have been symbolized by stars, it being understood that the alignment marks 305 may, in practice, have any shape.

[0101] [Fig.3B] illustrates more particularly a structure obtained at the end of a subsequent step of transfer, onto the structure previously described in relation to [Fig.3A], of the CMOS substrate 157 previously described in relation to [Fig.1G].

[0102] By way of example, the CMOS substrate 157 is brought into contact, by the face of the interconnection stack 155 opposite the wafer 151 (the lower face of the interconnection stack 155, in the orientation of [Fig.2F]), with the interconnection stacks 301 and the upper face of the layer 225. During this step, the CMOS substrate 157 is fixed to the wafer 221. By way of example, the fixing on the wafer 221 is obtained by molecular bonding between the two surfaces brought into contact.

[0103] During the bonding step, the CMOS substrate 157 is for example aligned with respect to the structure previously described in relation to [Fig. 3A]. For this, the alignment marks 247 are for example previously formed in the interconnection stack 155 so that, at the end of the transfer step, the alignment marks 247 are located substantially opposite the alignment marks 305. The CMOS substrate 157 is for example, as illustrated in [Fig. 3B], devoid of the alignment marks 159.

[0104] Subsequent steps of the manufacturing method of the optoelectronic device can then be implemented from the structure illustrated in [Fig.3B], the CMOS substrate 157 being for example intended to be kept at the end of these steps.

[0105] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. Although embodiments have been described above in relation to an exemplary embodiment of an optoelectronic device comprising a diode stack, the embodiments of the present description apply more generally to any method of producing an electronic device using a substrate considered to be unconventional, for example a substrate having a diameter less than or equal to approximately 150 mm and / or a substrate made of sapphire or an inorganic semiconductor material other than silicon, for example an IILV semiconductor material.

[0106] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above. In particular, the embodiments described are not limited to the examples particular materials and dimensions mentioned in this description.

Claims

Claims

1. A method for producing an electronic device comprising the following successive steps: a) forming a structure comprising a first wafer (101), an active stack (103) arranged on the first wafer, and a first interconnection stack (105) covering a face of the active stack opposite the first wafer; and b) transferring the structure onto a second wafer (111) by molecular bonding on the side of a face of the first interconnection stack opposite the first wafer, the second wafer having a diameter strictly greater than that of the first wafer, the method further comprising, after step b), a step c) of cutting the active stack (103) and the first interconnection stack (105) into vignettes (141; 211).

2. A method according to claim 1, further comprising, between steps b) and c), a step of removing the first wafer (101).

3. Method according to claim 2, further comprising, after the step of removing the first wafer (101) and prior to step c), steps of depositing a dielectric layer (115) coating the first interconnect stack (105) and the active stack (103) and of planarizing said layer.

4. Method according to claim 3, further comprising, after the step of planarizing the dielectric layer (115) and prior to step c), a step of transferring the structure comprising the second wafer (111), the first interconnection stack (105), the active stack (103) and the dielectric layer (115) onto a third wafer (131) by molecular bonding on the side of a face of the dielectric layer opposite the second wafer.

5. Method according to claim 4, in which the third wafer (131) has a diameter strictly greater than that of the first wafer (101).

6. Method according to claim 4 or 5, further comprising, after the step of bonding to the third wafer (131) and prior to step c), a step of removing the second wafer (111).

7. The method of claim 6, further comprising, after the step of removing the second wafer (111) and before in step c), a step of forming a second interconnection stack (135) on the side of a face of the first interconnection stack (105) opposite the third wafer (131).

8. Method according to claim 7, further comprising, after step c), a step of transferring the vignettes (141) onto a fourth wafer (151) by molecular bonding on the side of a face of the second interconnection stack (135) opposite the third wafer (131).

9. Method according to any one of claims 1 to 3, further comprising, after step c), a step d) of transferring the vignettes (211) onto a fifth wafer (221) by molecular bonding on the side of a face of the active stack (103) opposite the second wafer (111).

10. The method of claim 9, further comprising, after step d), a step of removing the second wafer (111).

11. Method according to claim 10, further comprising, after step d), a step e) of forming a third interconnection stack (235; 301), covering a face of the first interconnection stack (105) opposite the fifth wafer (221).

12. Method according to claim 11, further comprising, after step e), a step f) of transferring the structure comprising the fifth wafer (221), the first interconnection stack (105), the active stack (103) and the third interconnection stack (235; 301) onto a sixth wafer (151) by molecular bonding on the side of a face of the third interconnection stack opposite the second wafer.

13. A method according to any one of claims 1 to 12, wherein the first wafer (101) has a diameter equal to approximately 150 mm.

14. A method according to any one of claims 1 to 13, wherein the second wafer (111) has a diameter equal to approximately 200 or 300 mm.

15. A method according to any one of claims 1 to 14, wherein the active stack (103) is a light emitting diode active stack.

16. A method according to any one of claims 1 to 15, wherein the first wafer (101) is made of sapphire or an inorganic semiconductor material other than silicon, preferably a III-V semiconductor material.

Images