Unique programmable memory cell and method for managing the logic state of the memory cell

Abstract

In one embodiment, the memory cell (CEL) comprises a three-contact PIN diode (DPIN) (CT1, CT2, CT3). A breakdown voltage (HV) is applied to break a gate oxide located between a region of the PIN diode and a substrate region, and the broken or unbroken state of the gate oxide is determined by applying a read voltage between the anode and cathode of the diode and determining the corresponding current flowing through the diode. (See Figure 10 for abbreviations.)

Description

Description Title of the invention: Unique programmable memory cell and Method for managing the logical state of the memory cell

[0001] Implementation and embodiment methods of the invention relate to the cells non-volatile memories of the type with unique programming, known to man of profession under the Anglo-Saxon acronym "OTP" ("One Time Programmable").

[0002] — Classically, a memory cell of the one-time programmable type operates like a fuse or a fuse breaker whose state is irreversibly altered, by for example, by breaking down a dielectric, by applying a programming voltage high, or breakdown voltage, to the memory cell, so that the memory cell passes from a non-conducting state to a conducting state, which is equivalent to changing its re- resistance.

[0003] — For example, a memory cell of the type uniquely programmable in the form of a An anti-fuse typically includes a capacitor with a di- layer. electrical current flows between its two electrodes. This capacitor can be formed by a transistor MOSFET whose source and drain are connected. Depending on the programming voltage Applied and with the programming time, one can obtain a conductive channel which completely passes through the dielectric layer of the capacitor, a known phenomenon by the expert under the Anglo-Saxon term "Hard Breakdown". The di- layer electrical is then said to be (electrically) "broken".

[0004] — Consequently, this conductive channel permanently changes the state of the capacitor which changes from non-conductor to conductor, in other words the resistance of the cell memory. The logical value of the memory cell, for example, is initially equal to "O" then becomes "1" when the conducting channel created completely passes through the dielectric layer of the capacitor.

[0005] — Usually, an anti-fuse structure includes a first MOS transistor having a fine grid oxide, mounted as a capacitor, so as to allow breakdown of this oxide, as well as a second transistor having a thicker gate oxide designed to manage the breakdown of the oxide of the first transistor and read the structure in a way to determine its logical state.

[0006] — However, such an OTP memory cell structure uses two transistors which is detrimental from a silicon bulk perspective.

[0007] There is therefore a need to offer an OTP memory cell plus compact.

[0008] = According to one aspect, an integrated memory device is proposed comprising a programmable memory cell (one-time program). This memory cell includes -a first semiconductor bar having a lower face and an upper face opposite to the lower face, -a first electrically insulating region, for example a thin dielectric layer located between a first zone on the lower face of the bar and a semiconducting region, for example an active substrate zone, -a second electrically insulating region, for example a dielectric layer comprising a stack of the silicon dioxide-silicon nitride-silicon dioxide type (known to those skilled in the art by the Anglo-Saxon acronym ONO), thicker than the first insulating region and located between a second zone of the lower face and said semiconductor region. The memory cell has a first logic state in the presence of a first electrically non-split insulating region and a second logic state in the presence of a first electrically split insulating region. The integrated memory device also includes -the first means configured to apply a breakdown potential difference between the semiconductor region and the semiconductor bar so as to break the first insulating region, and -second means configured to apply a read voltage between two locations on the top face of the silicon bar and to determine the value of the current flowing between the two locations in order to determine the logic state of the memory cell. The memory cell thus includes, for example, at least -a first electrically conductive contact, -a second electrically conductive contact, and -a third electrically conductive contact, -the first means being configured to apply the breakdown potential difference between the third contact and the first or second contact and -the two means being configured to apply the reading voltage and determine the value of said current between the first contact and the second contact. According to one possible variant, the first semiconductor bar may have a unique type of conductivity, preferably opposite to the type of conductivity of the semiconductor region. The first bar, for example, has the conductivity type P. Such a bar then forms a resistive element. The first bar overlaps a portion of the semiconductor region, for example a substrate region, to allow the breakdown of the oxide located between this overlapping portion and the substrate semiconductor region. And we use the same bar to determine the logical state of the memory cell. We therefore obtain an OTP memory cell with a reduced footprint compared to a prior art two-transistor memory cell. According to another possible variant, the first bar may include a PIN diode. A PIN diode (for "Positive Intrinsic Negative" in English) is a diode comprising an intrinsic polysilicon region, i.e. undoped, sandwiched between two doped regions of type P (anode region) and type N (cathode region). The first area of ​​the lower face of the PIN diode includes at least a portion of the lower face of the intrinsic polysilicon region, or of the anode region or of the cathode region depending on the embodiment envisaged. The first means are configured to apply the breakdown potential difference between the semiconductor region and the anode region and / or the cathode region (depending on the embodiment envisaged), and the second means are configured to apply the read voltage between a location on the upper face of the anode region and a location on the upper face of the cathode region. Thus, here again, the bar containing the PIN diode overlaps a part of the semiconductor region, for example a substrate region, to allow the breakdown of the oxide located between this overlapping part and the substrate semiconductor region. And we also use the same bar to determine the logical state of the memory cell. This also results in a reduced footprint. Furthermore, the use of a PIN diode is more advantageous than the use of a resistive bar as mentioned above. Indeed, the PIN diode is read directly and delivers a first forward current when the first insulating region is not broken, corresponding to a first logic state of the memory cell. The PIN diode delivers a second forward current when the first insulating region is broken, corresponding to a second logic state. This second forward current is significantly lower, for example by 5 decades, than the first forward current because the PIN diode is no longer operational. The use of a PIN diode therefore makes it easy to distinguish between the two logic states of the memory cell. Several implementation methods for this alternative variant using a PIN diode are possible. Thus, according to one embodiment, the semiconductor region comprises a substrate semiconductor region, the first area of ​​the lower face of the PIN diode includes at least part of the lower face of the anode region and the second area of ​​the lower face of the PIN diode is located next to the first area and includes the remainder of the lower face of the PIN diode, the first insulating region includes an insulating layer, for example a silicon dioxide film, and the second insulating region includes a shallow insulating trench (STI: Shallow Trench Isolation) extending next to this insulating layer under the second area of ​​the lower face of the PIN diode. Thus in this embodiment it is the anode region which overlaps the semiconducting region of the substrate. According to another possible embodiment, the semiconductor region comprises a substrate semiconductor region, the first area of ​​the bottom face of the PIN diode includes at least a portion of the bottom face of the cathode region and the second area of ​​the bottom face of the PIN diode is located next to the first area and includes the remainder of the bottom face of the PIN diode, the first insulating region includes an insulating layer, and the second insulating region includes a shallow insulating trench extending next to this insulating layer under the second area of ​​the bottom face of the PIN diode. In this embodiment, it is the cathode region that overlaps the semiconductor region of the substrate. The inventor nevertheless observed that it was more effective in distinguishing during reading the first forward current (unslammed oxide) from the second forward current (slammed oxide) when the anode region overlaps the substrate region. Regardless of the embodiment, the semiconductor substrate region preferably has a type of conductivity opposite to the type of conductivity of the anode region. According to yet another possible embodiment, the semiconductor region comprises a second semiconductor bar located between the lower face of the PIN diode and a third electrically insulating region, the first area of ​​the lower face of the PIN diode includes at least a portion of the lower face of the intrinsic poly-silicon region and the second area of ​​the lower face of the PIN diode is located on either side of the first area, the first insulating region includes a first insulating layer and the second insulating region includes a second insulating layer that is thicker than the first insulating layer. Thus in this embodiment, the oxide intended to be slashed is located between the intrinsic semiconductor region and the second semiconductor bar on which the PIN diode rests. The third insulating region includes, for example, a shallow insulating trench. The second bar preferably has a type of conductivity opposite to that of the anode region. According to yet another possible embodiment of this variant, compatible with the fabrication of non-volatile memory cells with floating gates and selection transistors buried in the substrate, the first zone of the lower face of the PIN diode comprises at least a portion of the lower face of the intrinsic polysilicon region, and the second zone of the lower face of the PIN diode is located on either side of the first zone. The first insulating region comprises a first insulating layer, for example, a silicon dioxide layer, and the second insulating region comprises a second insulating layer, for example, a silicon dioxide-silicon nitride-silicon dioxide stack, thicker than the first insulating layer. The semiconductor region comprises a semiconductor trench in contact with the first insulating layer and extending through a fourth insulating region.for example, comprising a shallow trench. The semiconductor trench preferably has a type of conductivity opposite to the type of conductivity of the anode region. According to another aspect, a method for managing the logic state of a once programmable integrated memory cell is proposed, the memory cell comprising a first semiconductor bar having a lower face and a upper face opposite to the lower face, a first electrically insulating region located between a first area of ​​the lower face and a semiconductor region, a second electrically insulating region thicker than the first insulating region located between a second area of ​​the lower face and said semiconductor region, a method in which the memory cell is given a first logic state in the presence of a first insulating region not electrically broken and a second logic state in the presence of a first insulating region electrically broken, and the first insulating region is broken by applying a breakdown potential difference between the semiconductor region and the semiconductor bar. According to another aspect, a method is proposed for managing the logic state of a once-programmable integrated memory cell. The memory cell comprises a first semiconductor bar having a lower face and an upper face opposite the lower face, a first electrically insulating region located between a first zone of the lower face and a semiconductor region, and a second electrically insulating region thicker than the first insulating region located between a second zone of the lower face and said semiconductor region. In this method, the memory cell is given a first logic state in the presence of a first electrically unbroken insulating region and a second logic state in the presence of a first electrically broken insulating region, and the state is determined. logic of the memory cell by applying a read voltage between two locations on the top face of the silicon bar and determining the value of the current flowing between the two locations. According to one embodiment, wherein the first bar comprising a PIN diode having an intrinsic polysilicon region between an anode region and a cathode region, the first area of ​​the lower face of the PIN diode having at least a portion of the lower face of the intrinsic polysilicon region, or of the anode region and / or the cathode region, the breakdown potential difference is applied between the semiconductor region and the anode region and / or the cathode region, and the readout voltage is applied between a location on the upper face of the anode region and a location on the upper face of the cathode region. Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments and implementations, which are by no means limiting, and the accompanying drawings in which: [Fig.1] ; [Fig.2]; [Fig.3]; [Fig.4]; [Fig.5]; [Fig.6]; [Fig.7]; [Fig.8]; [Fig.9]; [Fig.10]; [Fig.11A]; [Fig.11B]; [Fig.12] and [Fig.13] illustrate methods of implementation and execution of the invention. In [Fig.1], the reference DIS designates an integrated memory device including here a memory cell programmable once CEL (called "OTP" cell). As will be seen in more detail below, this CEL memory cell has a first electrically insulating region intended to be either slammed or not, the CEL memory cell having a first logic state in the presence of a first insulating region not slammed and a second logic state in the presence of a first insulating region slammed. The DIS memory device also includes initial MTI1 means of classic and known structure in itself, configured to apply a HV breakdown potential difference on the CEL cell so as to break this first insulating region if one wishes to confer the second logic state to the CEL cell. The DIS device also includes second means MT2, also of classic structure and known per se, configured to apply a read voltage RV between two locations of the memory cell so as to determine the value of the current IRV flowing between these two locations and thus determine the logic state of the memory cell. As illustrated in [Fig.2], the DIS memory device may include a PM memory plane comprising a matrix of CELi.j memory cells arranged in rows and columns. Thus each CELi,j memory cell is connected to a WL word line to receive the RV read voltage. The CELij memory cell is also connected to a BL bit line on which the IRV read current will flow. The second MT2 means therefore include a CTR2 circuit connected to the WL word line, of classic and known structure, and intended to deliver the RV reading voltage. Furthermore, the second MT2 means include, for example, a reading amplifier SA2 of classic and known structure allowing the determination of the value of the reading current IRV. We now refer more specifically to figures 3 to 10 to describe several embodiments of a first variant. In this first variant, the CEL memory cell includes a PIN diode referenced DPIN schematically illustrated in [Fig.10]. More specifically, this PIN DPIN diode is a three-contact diode. A first contact CT1, connected to the anode region is connected to the WL word line. A second contact CT2, connected to the cathode region, is connected to the BL bit line, while a third contact CT3 is intended to receive the breakdown voltage HV. If we now refer more particularly to [Fig.3], we see that the programmable memory cell once CEL has a first semiconductor bar BRI, for example in silicon, having a lower face FI and an upper face FS opposite to the lower face. This first bar here includes the PIN DPIN diode having an intrinsic poly-silicon region RINT between the anode region RAN and the cathode region RCAT. The intrinsic polysilicon region (RINT), for example, has a concentration of dopants less than 10!5 atoms / cm3. The P+ doped RAN anode region, for example, has a dopant concentration on the order of 10° atoms / cm3. The N+ doped cathode region, for example, also has a dopant concentration of the order of 10° atoms / cm3. The lower face FI of the first bar has a first zone FIZ1 comprising at least a part of the lower face of the anode region RAN. A first insulating region RIS1, formed here of a thin layer of silicon dioxide having for example a thickness of the order of twenty Angstroms, is located between the first zone FIZ1 and a semiconductor region of substrate SB having for example a conductivity type N. This semiconductor substrate region can be the substrate itself or an N-doped well in a P-type substrate. The CEL memory cell also includes a second electrically insulating region RIS2, here a shallow trench known to those skilled in the art under the Anglo-Saxon acronym STI (Shallow Trench Isolation) located between a second FIZ2 area of ​​the lower face FI of the PIN diode and the substrate semiconductor region SB. This second FIZ2 zone on the underside of the PIN diode is located next to the first FIZ1 zone and includes the rest of the underside of the PIN diode. The shallow insulating trench RIS2 extends alongside the first insulating region RISI. The first BR1 bar also has ESP insulating spacers on its sides with a classic and well-known structure. The upper face FS of the first bar has, above the anode region RAN, a layer of metal silicide ZS, for example in CoSiz, as well as the first electrically conductive contact CTI, for example in copper or tungsten, coming into contact with the silicided area ZS. Similarly, the upper face FS of the first bar also has above the cathode region a metal silicide zone ZS, for example also in CosSi, as well as the second electrically conductive contact CT2 coming into contact with this silicide zone ZS. The remainder of the upper FS layer of the first bar is covered with a protective layer referenced Siprot intended, during the manufacture of the memory cell, to protect the underlying part of the upper face of the bar from silicification. This protective layer includes, for example, silicon dioxide or a stack of a layer of silicon dioxide topped with silicon nitride. The CEL cell also includes, within the SB substrate region, an area overdoped ZSP, having the type of conductivity P and for example a concentration of dopants on the order of 10? atoms / cm3, covered with a zone of metal silicide ZS, as well as the third electrically conductive contact CT3 coming into contact with this silicided zone ZS. It is also possible to provide, next to this overdoped zone ZSP, an insulating region RIS 10 for example of the shallow trench type, in order to electrically isolate it from other components of the integrated circuit. As we will see in more detail below, we will apply the high breakdown voltage HV between the first contact CT and the third contact CT3, for example by putting the voltage HV on one of these two contacts and ground on the other. On the other hand, the reading voltage RV will be applied between the two contacts CTI and CT2, for example by applying the voltage RV on the first contact CT1 and ground on the second contact CT2 so as to bias the DPIN diode forward and read the corresponding IRV current. Of course, it would be possible to place the third CT3 contact in another location. For example, as illustrated in [Fig. 4], it would be possible to place two third CT3 contacts on either side of the RAN anode region. We now refer more specifically to [Fig.5] to describe another embodiment of a CEL memory cell also using a PIN DPIN diode. Only the differences from the embodiment illustrated in [Fig.3] will now be described. The CEL memory cell of [Fig.5] also includes a first semiconductor bar BR1O, for example in silicon, incorporating the PIN DPIN diode comprising the anode region RAN, the intrinsic polysilicon region RINT and the cathode region RCAT. One difference compared to the CEL cell of [Fig.3] lies in the location of the first insulating region RISI. Indeed, in [Fig.5], the first FIZ1 area of ​​the lower face of the PIN DPIN diode includes part of the lower face of the RCAT cathode region and the second FIZ2 area of ​​the lower face of the PIN diode is located next to the first FIZ1 area and includes the rest of the lower face of the PIN DPIN diode. Thus, in this embodiment, the first insulating region RISI (thin layer of silicon dioxide) is located between the cathode region and the substrate region SB while the second insulating region RIS2 (for example of the shallow trench type) is located between the rest of the PIN diode and the substrate region SB. Furthermore, here, the substrate region SB includes a heavily N+ doped ZSN region with, for example, a dopant concentration on the order of 107 atoms / cm3, and the third contact CT3 contacts this overdoped ZSN region via the metal silicide zone ZS. Another insulating region RIS1O, is located next to the heavily doped ZSN area to possibly isolate this ZSN area from other components. In this embodiment, the high breakdown voltage HV is applied between the second contact CT2 and the third contact CT3. The RV reading voltage is always applied between the first contact CTI and the second contact CT2. This is illustrated more particularly in figures 11A and 11B. Thus, as illustrated in [Fig. 11A], to break the first insulating zone RIS1 (the thin grid oxide-type layer), the first means MT1 apply the breakdown voltage HV, for example, on the order of 7.5 volts, for a duration on the order of 100 microseconds, either between the first contact CT1 and the third contact CT3, or between the second contact CT2 and the third contact CT3. For example, the HV voltage can be applied to either of the contacts CT1 and CT2 and ground to the third contact CT3 (step ST110). This results in the ST111 step in the breakdown of the first insulating region RIS1. The result is that the DPIN diode is no longer operational. The determination of the logic state of the CEL memory cell is more particularly illustrated in [Fig.11B]. Thus, the second MT2 means apply the RV reading voltage in the ST112 stage between the first CTI contact and the first CT2 contact so as to read the diode forward. This reading voltage can be on the order of 1 volt. In step ST113, the SA2 readout amplifier determines the value of the IRV current resulting from the application of the RV readout voltage. We then obtain two possible values ​​of current IRV1 and IRV2, the value of current IRV1 being greater than the value of current IRV2. If the IRV!1 current is detected, it means that the CEL memory cell has the first logic state ETLI corresponding to the first insulating region RIS1 (gate oxide) not slammed. On the other hand, if it is the IR V2 current that is detected, then this corresponds to a second logic state ETL2 of the CEL memory cell corresponding to the first slammed insulating region RIS1. If we now refer more particularly to [Fig.6] which illustrates the evolution of the IRV read current as a function of the RV read voltage applied to the anode of the PIN diode, we see that the IRV current follows the CV1 curve when the PIN diode is operational, i.e. with an unbroken RIS1 gate oxide. More specifically, the CV1 curve, which corresponds to the evolution of the IRV1 current, decreases from an initial value greater than 10 picoamperes until reaching a value of the order of 1 picoampere then, when the diode becomes conducting, the IRVI current increases abruptly to reach a value of the order of 10 microamperes around a reading voltage RV of the order of 1 volt. On the other hand, if the gate oxide RIS1 is broken, then the diode is no longer operational and the IR V2 current follows the CV2 curve in the embodiment of [Fig.3] or the CV3 curve in the embodiment of [Fig.5]. We can therefore see that there is a significant difference between the value of the current IRV]1 and the value of the current IRV2, which allows for easy selection between the two logic states. We also see that the localization of the RIS1 grid oxide under the anode region is more efficient than the localization of the RIS1 grid oxide under the cathode region, because in the first localization the difference between the IRV1 and IRV2 values ​​is greater than in the second localization. We now refer more specifically to [Fig.7] to illustrate another embodiment of the CEL memory cell also using a BR1 bar, for example in silicon, comprising a PIN DPIN diode. Again, only the differences between [Fig.7] and [Fig.3] will now be described. Unlike the embodiment of [Fig.3], the PIN DPIN diode here rests via the insulating regions RIS1 and RIS2 on a second semiconductor bar BR2, for example made of silicon having conductivity type N, this second bar itself resting on a third insulating region RIS3, for example of the shallow trench type, made within a substrate SB having conductivity type N. The first FIZ1 zone on the lower face of the PIN diode now includes a portion of the lower face of the intrinsic polysilicon region RINT, and the second FIZ2 zone on the lower face of the PIN diode is located on either side of the first FIZ1 zone. The first insulating region RISI has a first insulating layer of the grid oxide type while the second insulating region RIS2 has a second insulating layer thicker than the first insulating layer, and formed here of a stack of silicon dioxide 10, silicon nitride 11 and silicon dioxide 12. The third contact CT3 is connected to an edge of the second bar BR2 via a silicified zone ZS. The implementation of the possible breakdown of the RIS1 area and the determination of the logic state of the CEL memory cell, described with reference to Figures 11A and 11B, also apply to this embodiment of [Fig.7]. Fig. 8 and Fig. 9, which is a cross-sectional view along line IX - IX of Fig. 8, illustrate yet another embodiment of the CEL memory cell using a PIN DPIN diode. Compared to the embodiment of [Fig.7], the semiconductor region to which the third contact CT3 connects is this time not the second bar BR2 of [Fig.7] but a semiconductor trench TRN extending under the first insulating region RIS1 through a fourth insulating trench RIS4 for example of the shallow trench type. This TRN semiconductor trench, for example in heavily doped N-type silicon with, for example, a dopant concentration of the order of 107 atoms / em3, is also isolated from the underlying SB substrate by an electrically insulating RISS envelope. In this embodiment, although only one third contact CT3 could have been provided, as illustrated in [Fig.9], two can be provided located on either side of the intrinsic semiconductor region RINT of the diode PIN. It should be noted that in Figures 7 to 9, the Siprot region and the ESP spacers have not been shown for the purpose of simplifying these figures, but of course this region and these spacers are present on the BR bar in a manner analogous to their presence on the BR bar of [Fig.3]. We now refer more specifically to [Fig.12] to illustrate yet another embodiment of a CEL memory cell. In this embodiment, a three-contact PIN diode is no longer used, but a first BR100 semiconductor bar, for example made of silicon, having a uniform conductivity type, for example of P+ conductivity type with a dopant concentration of the order of 10 atoms / cm3. Apart from this difference, the structure of the CEL cell in [Fig.12] is analogous to that of [Fig.3]. The breakdown of the first insulating region RISI is achieved by applying, for example, the high voltage HV between the first contact CT] and the third contact CT3, and the reading of the current IRV is achieved after applying the reading voltage RV between the contacts CT1 and CT2. The BR 100 bar is a resistive bar. The embodiment of [Fig.12] is certainly simpler to implement than embodiments using a PIN diode. If the first RIS1 region is not slammed, the resistance between the two contacts CTI and CT2 has a first resistive value. However, if the first insulating region RIS1 is broken, the resistance between the two contacts CT1 and CT2 have a value greater than the resistive value of the BR100 bar. Therefore, if the first insulating region RIS1 is not broken, the value of the IRV current will be higher than that of the IRV current in the presence of a broken RIS1 region. That being said, the difference between these two values ​​is smaller than in the case of using a PIN diode. Thus, this embodiment is less efficient in terms of selecting the logic state of the CEL memory cell than embodiments using a PIN diode. The invention is not limited to the embodiments and implementations just described. Thus it is possible, as illustrated in [Fig.13], to combine the implementation methods of figures 3 and 5. More specifically, the semiconductor region includes a substrate semiconductor region SB and the first FIZ1 area of ​​the bottom face of the PIN DPIN diode includes at least a portion of the bottom face of the anode region RAN and at least a portion of the bottom face of the cathode region RCAT. The second FIZ2 area of ​​the lower face of the PIN diode is located between said at least a portion of the lower face of the anode region RAN and said at least a portion of the lower face of the cathode region RCAT and includes the remainder of the lower FI face of the PIN diode. The second insulating region RIS2 includes a shallow insulating trench extending below the second FIZ2 area of ​​the lower face of the PIN diode. The first insulating region RISI comprises two insulating layers, for example gate oxide dielectric layers, respectively located on either side of the shallow insulating trench RIS2. The CEL cell has a third contact CT3 coming into contact with the silicate zone ZS covering the overdoped zone ZSP within the substrate region SB and another third contact CT3 coming into contact with the silicate zone ZS covering the overdoped zone ZSN also within the substrate region SB. In this embodiment, the high breakdown voltage HV can be applied - a) either only between the first contact CT1 and the third contact CT3, - b) either only between the second contact CT2 and the other third contact CT3, - €) either between the first CTI contact and the third CT3 contact and between the second CT2 contact and the other third CT3 contact, and this successively or simultaneously. Case c) helps to better differentiate the two logical states of the cor- memory cell responding to the "slammed" and "unslammed" states of the first RISI insulating region. The RV reading voltage is always applied between the first contact CTI and the second contact CT2.

Claims

Claims

1. An integrated memory device comprising -a one-time programmable memory cell (CEL) comprising a first semiconductor bar (BR1) having a lower face and an upper face opposite the lower face, a first region electrically insulating (RIS1) located between a first zone of the face lower and a semiconductor region (SB), a second region electrically insulating (RIS2) thicker than the first region insulating material located between a second zone of the lower face and said semiconductor region, the memory cell having a first state logic in the presence of a first non-electrically insulating region slammed and a second logical state in the presence of a first region electrically broken insulator, - first means (MT1) configured to apply a difference breakdown potential between the semiconductor region and the first semiconductor bar so as to break down the first insulating region, And - second means (MT2) configured to apply a voltage of reading between two locations on the upper face of the bar silicon and to determine the value of the current flowing between the two locations to determine the logical state of the cell memory.

2. A device according to claim 1, wherein the memory cell (CEL) comprises at least one first electrically conductive contact (CT1), a second electrically conductive contact (CT2) and a third electrically conductive contact (CT3), the first means (MT1) being configured to apply the potential difference breakdown between the third contact and the first or second contact and the two means (MT2) state configured to apply the reading voltage and determine the value of said current between the first contact (CT1) and the second contact (CT2).

3. A device according to claim 1 or 2, wherein the first bar includes a PIN (DPIN) diode having a polysilicon region intrinsic between an anode region and a cathode region, the first area of ​​the lower face of the PIN diode comprising at least a portion of the underside of the intrinsic polysilicon region, or the anode region or the cathode region, the first means (MT!) are configured to apply the potential difference of breakdown between the semiconductor region (SB) and the anode region (RAN) and / or the cathode region (RCAT), and the second means (MT2) are configured to apply the read voltage between an em- placement of the upper face of the anode region and a location from the upper face of the cathode region.

4. The device of claim 3, wherein the semicon- conductive comprises a substrate semiconductor region (SB), the first area of ​​the lower face of the PIN diode comprises at least a part of the lower face of the anode region (RAN) and the second area of ​​the lower face of the PIN diode is located next to the first area and includes the rest of the lower face of the diode PIN, the first insulating region (RIS1) comprises an insulating layer, and the second insulating region (RIS2) comprises an insulating trench shallow extending beside this insulating layer under the second area of ​​the lower face of the PIN diode.

5. The device of claim 3, wherein the semicon- conductive comprises a substrate semiconductor region (SB), the first area of ​​the lower face of the PIN diode comprises at least a part of the lower face of the cathode region (RCAT) and the second area of ​​the lower face of the PIN diode is located next to the first area and includes the rest of the lower face of the diode PIN, the first insulating region comprises an insulating layer, and the second insulating region includes a shallow insulating trench extending next to this insulating layer under the second zone of the bottom face of the PIN diode.

6. A device according to claim 3, wherein the semicon- conductive comprises a substrate semiconductor region (SB), the first area of ​​the lower face of the PIN diode comprises at least a portion of the lower face of the anode region (RAN) and at least a part of the lower face of the cathode region (RCAT), and the second area of ​​the lower face of the PIN diode is located between said at least a portion of the [lower ace of the anode region (RAN) and said at least a portion of the lower face of the region of cathode (RCAT) and includes the rest of the bottom face of the diode PIN, the second insulating region (RIS2) includes an insulating trench shallow extending below the second zone of the underside of the PIN diode and the first insulating region (RIS1) comprises two insulating layers located respectively on either side of the trench shallow insulation.

7. A device according to claim 4, 5 or 6, wherein the semi- substrate (SB) conductor has a conductivity type opposite to the type of conductivity of the anode region.

8. A device according to claim 3, wherein the semicon- conductive bar comprises a second semiconductor bar (BR2) located between the lower face of the PIN diode and a third electri- trically insulating (RIS3), the first zone of the lower face of the PIN diode has at least a portion of the underside of the intrinsic polysilicon region (RINT) and the second area of ​​the The lower face of the PIN diode is located on either side of the first zone, the first insulating region comprises a first insulating layer and the second insulating region comprises a second insulating layer thicker than the first insulating layer.

9. The device of claim 8, wherein the third region insulating (RIS3) comprises a shallow insulating trench.

10. Device according to claim 8 or 9, in which the second bar (BR2) has a conductivity type opposite to that of the anode region.

11. | A device according to claim 3, wherein the first area of ​​the bottom face of the PIN diode comprises at least a portion of the face lower intrinsic polysilicon region (RINT) and the second area of ​​the lower face of the PIN diode is located on either side on the other side of the first zone, the first insulating region (RIS1) comprises a first insulating layer and the second insulating region comprises a second insulating layer (RIS2) thicker than the first insulating layer, the semiconductor region has a semi- conductive (TRN) in contact with the first insulating layer and extending through a fourth insulating region (RIS4).

12. | Device according to claim 11, in which the fourth region insulating (RIS4) has a shallow trench.

13. A device according to claim 10 or 11, wherein the semi-trench conductive (TRN) has a conductivity type opposite to the type of conductivity of the anode region.

14. A device according to claim 1 or 2, wherein the first bar semiconductor (BR100) has a single conductivity type.

15. The device of claim 14, wherein the conductivity type of the first bar (BR100) is opposite to the conductivity type of the semiconductor region (SB).

16. Method for managing the logical state of an integrated memory cell pro- grammable once, the memory cell comprising a first bar semiconductor (BR1) having a lower face and a upper face superior opposite to the lower face, a first electrical region strictly insulating located between a first zone of the lower face and a semiconductor region, a second electrically thicker insulating region than the first insulating region located between a second area of ​​the lower face and said semiconductor region, process in which the memory cell is given a first state logic (ETL1) in the presence of a first non-elec- trically slammed and a second logical state (ETL2) in presence of a first insulating region slammed, and we slam the first region insulating by applying a breakdown potential difference (HV) between the semiconductor region and the semiconductor rod.

17. | Method for managing the logic state of an integrated memory cell pro- grammable once, the memory cell comprising a first bar semiconductor (BR1) having a lower face and a upper face superior opposite to the lower face, a first electrical region strictly insulating located between a first zone of the lower face and a semiconductor region, a second electrically thicker insulating region than the first insulating region located between a second area of ​​the lower face and said semiconductor region, process in which the memory cell is given a first state logic (ETLI1) in the presence of a first non-elec- insulating region trically slammed and a second logical state (ETL2) in presence of a first electrically broken down insulating region, and we determine the logical state of the memory cell by applying a voltage of reading (RV) between two locations on the upper face of the bar silicon and determination of the value of the current (IRV) circulating between the two locations.

18. A method according to claim 16 or 17, wherein the first bar (BR1) comprising a PIN diode having a poly- region intrinsic silicon between an anode region and a cathode region, the first area of ​​the lower face of the PIN diode comprising at at least a portion of the underside of the polysilicon region in- intrinsic, or of the anode region and / or of the cathode region, we applies the breakdown potential difference (HV) between the region se- microconductive and the anode region and / or the cathode region, and the read voltage (RV) is applied between a location on the upper face of the anode region and a location on the upper face of the cathode region.