Charge pump regulator

Abstract

Charge Pump Regulator This description relates to a regulator (104), comprising a first transistor (NPOWER) connecting an application node (NV33) of a first supply voltage (V33) to an output node (NV11) of the regulator for providing a first regulated voltage (V11); a feedback loop providing a control signal (VGATE) to the first transistor and comprising a first charge pump circuit (202); a control signal generator for the first charge pump circuit; and a step-down circuit (302) between the control signal generator and the charge pump circuit. Figure for the abstract: Fig. 3

Description

Title of the invention: Charge pump regulator technical field

[0001] This description relates generally to charge pump regulators and integrated circuits comprising such regulators. Previous technique

[0002] Charge pump regulators, in particular low power regulators, are used to supply loads whose consumption can vary, for example, from a hundred nanoamperes to several tens of milliamperes.

[0003] In low power applications, preference is given to either switch-mode power supply (SMPS) regulators, which require additional external connections and components, or charge pump regulators to limit the quiescent current (consumption) of their control loop. Summary of the invention

[0004] There is a need for improvement of charge pump regulators, and of integrated circuits comprising these regulators.

[0005] One embodiment overcomes all or part of the drawbacks of known regulators.

[0006] One embodiment provides a regulator, comprising: - a first transistor connecting a node applying a first supply voltage to an output node of the regulator intended to provide a first regulated voltage; - a feedback loop providing a control signal to the first transistor and comprising: - a first charging pump circuit; - a control signal generator for the first charging pump circuit; and - a level step-down circuit between the control signal generator and the charging pump circuit.

[0007] In one embodiment, the control signal generator includes a clock signal generator linking the output node and the level-decreasing circuit.

[0008] In one embodiment, the step-down circuit includes a power supply node configured to receive a voltage lower than the first supply voltage.

[0009] In one embodiment, the step-down circuit comprises a circuit buffer configured to be controlled as input by the clock signal.

[0010] In one embodiment, said buffer circuit includes a first inverting stage having a PMOS transistor in series with an NMOS transistor, their respective control nodes being configured to be controlled by the clock signal, a midpoint between said PMOS transistor and said NMOS transistor of the first stage being connected to the charge pump circuit.

[0011] In one embodiment, said buffer circuit comprises a second inverting stage having a PMOS transistor in series with an NMOS transistor, their respective control nodes being connected to said midpoint of the first stage.

[0012] In one embodiment, a midpoint between said PMOS transistor and said NMOS transistor of the second stage is connected to the charge pump circuit.

[0013] In one embodiment, a conduction node of the PMOS transistors of the first and / or second stage is connected to said power supply node of the level-decreasing circuit.

[0014] In one embodiment, the output node is connected to said power node of the step-down circuit.

[0015] In one embodiment, the step-down circuit comprises a second and a third transistor, each having a conduction node connected to the supply node of the step-down circuit and another conduction node connected to the application node of the first supply voltage.

[0016] In one embodiment, a control node of the second transistor is configured to receive the control signal from the first transistor.

[0017] In one embodiment, a control node of the third transistor is connected to an application node of a reference voltage lower than the first supply voltage.

[0018] In one embodiment, the feedback loop includes a comparator circuit configured to compare the first voltage to a first reference voltage; the first charging pump circuit being activated or deactivated depending on said comparison.

[0019] In one embodiment, the regulator includes a second charge pump circuit configured to provide a control signal to the first transistor when the first charge pump circuit is turned off.

[0020] In one embodiment, the regulator comprises: - a second comparator circuit configured to compare the first voltage to another reference voltage lower than the first reference voltage; and - a second control signal generator; the second charging pump circuit being controlled by the second generator control signals based on the comparison between the first voltage and the other reference voltage lower than the first reference voltage.

[0021] One embodiment provides an integrated circuit comprising a regulator as described above. Brief description of the drawings

[0022] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0023] [Fig.1] represents in a very schematic way and in block form, an example of an integrated circuit of the type to which the described embodiments apply;

[0024] [Fig.2] schematically represents an example of a regulator;

[0025] [Fig.3] schematically represents a regulator according to one embodiment;

[0026] [Fig.4] schematically represents a regulator according to another embodiment;

[0027] [Fig.5] schematically represents a regulator according to yet another embodiment;

[0028] [Fig.6] schematically represents a regulator according to yet another embodiment;

[0029] [Fig.7] schematically represents a regulator circuit according to one embodiment;

[0030] [Fig. 8] is a set of graphs representing the temporal variations of signals from a regulator according to the example of [Fig. 2] and according to the embodiment of [Fig. 6]; and

[0031] [Fig.9] is a set of graphs illustrating the operation of the embodiment of [Fig.6]. Description of the implementation methods

[0032] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0033] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0034] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked by through one or more other elements.

[0035] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0036] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0037] Fig. 1 represents, in a very schematic way and in block form, an example of an integrated circuit 100 of the type to which the described embodiments apply.

[0038] The circuit 100 includes, for example, a power supply unit 101 configured to provide the rest of the circuit 100 with different voltages and / or currents according to their requirements. The power supply unit 101 includes, for example, a low drop out linear regulator 102 (LDO), a low power regulator 104 (LPREG), a switched mode power supply 108 (SMPS), an oscillator 110 (OSC) generating a reference frequency, a finite state machine 112 (FSM), and a reference voltage supply module 106 (REF). State machine 112 is configured to control the operation of the other blocks of the power supply unit 101.Module 106 (REF) provides one or more reference voltages, for example from the band gap voltage between the valence and conduction bands (bangap voltage). Blocks 102, 104, 106, 108, 110 and 112 are, for example, connected to each other and / or to the rest of the integrated circuit 100 via a bus 114 carrying the required signals.

[0039] This description relates more particularly to the regulator 104 which is dedicated to operation at lower consumption than the regulator 102.

[0040] A regulator, for example linear or charge-pump, is based on a transistor, typically a power MOSFET, in series with the load between a power supply (voltage source) and a reference potential, typically ground. The MOSFET is driven in saturation, so that the gate-source voltage (Vgs) applied to it determines the drain-source current (Ids) flowing through it. The maximum power of the regulator is determined by the size of the transistor (or transistors connected in parallel).

[0041] In a regulator of the type of regulator 102, a feedback loop for controlling the output voltage to a reference value (i.e., maintaining an output voltage of the same value despite fluctuations in the load current draw) is based on a comparison of the output voltage to a reference value to make The gate voltage of the power transistor is varied continuously via an amplifier.

[0042] The described embodiments relate to another category of regulators (104, [Fig. 1]) whose feedback loop, while remaining continuously active, is only activated when the voltage falls below a predefined threshold. It therefore generates a lower quiescent current than a continuous feedback regulator, such as a linear regulator (amplifier regulator). These capacitive charge pump regulators are thus particularly well-suited to operation during periods of low power consumption in the circuit that houses them.

[0043] Fig. 2 represents schematically an example of a charge pump regulator 104 of the type to which the described embodiments apply.

[0044] The regulator 104 is connected, preferably connected, to a voltage source V33 and provides on an output node (NV 11) a regulated voltage (Vil) and / or a regulated current (Iload) to a load 212 external to the regulator 104. In [Fig.2], the load 212 is represented by a current source (Iload) associated in parallel with a load capacitance (Cload), both being referenced to ground.

[0045] The regulator 104 includes a first MOS transistor 204 (NPOWER) whose drain is connected, preferably connected, to a node (NV33) for applying a first supply voltage (V33) and whose source is connected, preferably connected, to the output node NV 11 of the regulator 104. The first transistor 204 is, for example, an NMOS transistor whose gate (NVGATE) is connected, preferably connected, to an output of a gate voltage control loop according to the load requirements.

[0046] In the described embodiments, the control loop includes a charge pump circuit 202 (Charge Pump LP) referenced to ground. The charge pump circuit 202 is typically a capacitive, switched-capacitor charge pump circuit and is configured to provide a control signal (VGATE) to the NVGATE of the first transistor 204.

[0047] A storage capacitor (Ctank) connects the NVGATE gate of the transistor to ground in order to smooth the NVGATE control voltage supplied by the charge pump.

[0048] The use of a charge pump requires that its control signal be a switching signal. The control loop therefore includes a clock signal oscillator or generator 208 (ClockGen) to activate the charge pump in order to increase the VGATE voltage during current inrush by the load 212 or more generally to compensate for internal leakage which causes VGATE to decrease during discharge, particularly in retention modes (without dynamic activity).

[0049] The regulator 104 shown further includes, in the control or feedback loop 220, a comparator 210 (COMP0V9) of the output node voltage NV 11 to a reference voltage RefOV9_ech. The output of the comparator 210 is connected to an enabling input (EN_OSC) of the clock signal generator 208. Inverted signals are often required to control the switches of the charge pump circuit 202. The clock signal generator 208 then provides two signals, forward 232 and reverse 234, to the charge pump circuit. These signals are generated by an output buffer circuit BF33 of the generator 208, configured to forward and invert the generated clock signal. If the voltage Vil is less than the reference voltage RefOV9_ech, then comparator 210 changes the state of the EN_OSC signal, which activates the generation of the clock signal.The charge pump circuit is then activated to raise the VGATE voltage level, and therefore the VIL voltage level

[0050] . Activating generator 208 and charge pump 202 only when comparator 210 detects a demand significantly reduces the quiescent current of the control loop, which is then essentially limited to the comparator's consumption. The RefOV9_ech voltage can be a fixed level but is, for example, sampled to further reduce consumption.

[0051] However, the VGATE gate control signal is likely to exhibit ripples related to a discharge of the smoothing capacitance Ctank under the effect of a parasitic leakage current (Ileakvgate) to the charge pump circuit as well as under the effect of the recharging of the capacitance by the charge pump.

[0052] In order to enable the regulator to start when V33 is energized, the regulation loop is usually, as illustrated in [Fig.2], powered by the voltage V33. Thus, the clock generator 208, the charge pump circuit 202, and the comparator 210 are powered by the voltage V33.

[0053] However, the ripple on the gate of the power transistor is all the more significant as the amplitude of signals 232 and 234 is related to the supply voltage level, given that this can vary considerably by more than a factor of two (for example, between 1.58V and 3.6V). In other words, the ripple on the gate of the power transistor is all the more significant as the difference between the high and low states of signals 232 and 234 is large. It is nevertheless essential that the regulator remain efficient over the range of possible supply voltage values.

[0054] According to the described embodiments, a level shifter circuit is integrated into the charge pump regulator 104 between the switching signal generator, or clock signal generator 208, and the charge pump circuit 202. This makes it possible to obtain input signals to the charge pump circuit with a difference between high and low levels that is smaller than that of the signals obtained with the supply voltage V33 and with less variation than the supply voltage V33. Residual oscillations are thus limited at the output of the charge pump circuit.

[0055] According to one embodiment, the output voltage VI1 of the regulator is used to power a buffer circuit for shaping the control signals of the charge pump. One advantage is that, unlike the supply voltage V33, which can vary by several volts in the case of battery power, for example, the voltage Vil is regulated and therefore more stable. However, a starting mode must then be provided in the step-down circuit to allow operation and startup of the charge pump. Nevertheless, the switching of transistors within the signal-shaping buffer circuit can disturb the voltage Vil through current surges.

[0056] According to another embodiment, the voltage of the step-down amplifier is generated by a dedicated circuit, from the voltage V33. This ensures the starting function and does not disturb the regulated voltage Vil.

[0057] Fig. 3 schematically represents a charge pump regulator 104 according to one embodiment.

[0058] The charge pump regulator 104 of [Fig.3] is similar to that of [Fig.2] except that a level step-down circuit 302 is added between the switching signal generator 208, or clock signal generator 208, and the charge pump circuit 202.

[0059] In the example shown, the clock signal generator 208 has a single output 306, and the step-down circuit 302 includes two outputs 310 and 312, from which inverted signals are generated for the charge pump circuit 202. In another example not shown, only one output, instead of two, is implemented. In yet another example not shown, the clock signal generator 208 has two inverted outputs, and the step-down circuit 302 includes two outputs.

[0060] The level step-down circuit 302 is configured to receive as input the clock signal generated by the clock signal generator 208, therefore with an amplitude which varies according to the supply voltage V33, and then provide as output a clock signal propagating with high and low levels separated by an amplitude less than the supply voltage V33.

[0061] Fig. 4 represents schematically the charge pump regulator 104 according to one embodiment.

[0062] In particular, [Fig. 4] illustrates an embodiment of the level-decreasing circuit 302 of [Fig. 3]. According to this embodiment, the circuit 302 comprises an amplifier or buffer circuit (BF11) with two inverted outputs, configured to be controlled at the input by a clock signal from the clock signal generator 208, and supplied by the output voltage VI1 of the regulator, applied to a supply NV node of the circuit 302. The other (not shown) supply terminal of the buffer circuit BF11 is connected, preferably connected to ground.

[0063] Since the voltage Vil is already regulated by the action of the feedback loop 220, this makes it possible to limit the residual oscillations at the output of the charge pump circuit without needing to generate the reduced supply voltage of the circuit 302 separately.

[0064] To enable the start-up of the control loop, the regulator 104 includes, according to this embodiment, a second charge pump circuit 410 (Charge Pump HP) whose output is connected, preferably connected, to the output of the charge pump circuit 202, i.e., to the gate of the NPOWER transistor, and whose inputs are connected, preferably connected, to a second clock generator 230 (CLOCK GEN 2). This second charge pump circuit 410 is controlled, for example, directly by the signals from the second generator 230, which is energized V33 to establish the voltage VI1 and thus start the feedback loop including the circuit 302. A control circuit (not shown) cuts off the charge pump circuit 410 when the voltage Vil is established, and the circuit 202 then takes over. This control circuit includes, for example, a comparator of the voltage Vil to a desired reference level (Ref0V85_ech).According to the example shown, this comparator (COMP0V85) generates another signal EN_OSC2 which is fed into the second clock generator circuit. The second clock signal generator is thus controlled by the EN_OSC2 signal so that it can generate a frequency other than that of the clock signal generator 208.

[0065] The presence of this starting circuit 410 also allows for a response to sudden current demands on the load 212. Indeed, in such a situation, the voltage VI1 tends to collapse. It is then anticipated that the control circuit (not shown) will activate the charge pump 410 when it detects that the voltage V1 falls below the desired reference level Ref0V85_ech. This desired reference level is chosen to be lower than the threshold RefOV9_ech in order to allow steady-state operation with the charge pump 202.

[0066] Fig. 5 represents schematically a charge pump regulator according to yet another embodiment.

[0067] The regulator in the example of [Fig. 5] is similar to that of [Fig. 4] except that the voltage applied to the NV node is a voltage V12CK obtained by a secondary charge-pump regulator 510 of the amplifier type from the voltage V33. This makes the use of circuit 410 for starting the charge-pump regulation loop optional. In the example shown, the optional circuit 410 is shown alone for clarity, but it is, for example, connected in a similar way to [Fig. 4].

[0068] In the example shown, a PO transistor, for example of the PMOS type, connects the NV node to the V33 power supply node. This transistor is controlled by an amplifier A differential inverter whose inverting input (labeled -) receives a reference voltage ReflV2_ech, for example 1.2V, and / or sampled to reduce power consumption. The non-inverting input (labeled +) is connected, preferably directly, to the NV node. The voltage V12CK applied to NV is therefore regulated to approach the ReflV2_ech reference voltage, which is lower than V33, thus reducing residual ripple at the output of the charge pump circuit 202.

[0069] The embodiment of [Fig.5] allows a supply voltage for the BF11 circuit to be chosen independently of the value of the VI1 voltage. However, it requires a non-negligible static consumption.

[0070] Figure [Fig. 6] schematically represents a charge pump regulator according to yet another embodiment.

[0071] The regulator of [Fig.6] is similar to that of [Fig.5] but illustrates another embodiment of the voltage generation circuit (V11CK2) applied to the NV node.

[0072] In the example shown, the 302 level step-down circuit comprises two transistors N0 and NI, for example of the NMOS type, in parallel between the node applying the first supply voltage V33 and the node NV, the sources of transistors N0 and N1 being interconnected to the node NV.

[0073] One of the transistors, here N0, is controlled by the VGATE voltage, output of the charge pump circuit 202. The other transistor, here NI, is controlled by a ReflV2_ech reference voltage, of the type described in relation to [Fig.5].

[0074] The NI transistor branch constitutes a branch not only useful for starting but also allows maintaining a minimum supply V11CK2 to the BF11 circuit in the case where the VGATE signal discharges faster than Vil (Ileakvgate / Ctank > Iload / Cload).

[0075] The branch of transistor N0, controlled by the VGATE level, increases the V11CK2 voltage in the event of a significant current inrush from the load 212 and ensures a faster response from the charge pump circuit to increase the VGATE level. This also improves operation at high temperatures where the current draw at the output Vil is high. This allows the VGATE voltage to be increased and, in turn, the V11CK2 voltage to be increased. The result is a more powerful charge pump circuit. The proposed regulator therefore allows adaptation to variations in the Iload current over a wide range. Furthermore, the activity of circuit 302 does not disturb the VIL supply.

[0076] In the example shown, circuit 410 is optionally implemented similarly to the examples in Figures 4 or 5 to aid startup or to compensate for high current inrush. Circuit 410 is shown alone for clarity, but it is, for example, connected similarly to [Fig. 4].

[0077] Figure 7 schematically represents a regulator circuit according to one embodiment. More particularly, Figure 7 represents a voltage converter circuit of an example embodiment where the voltage converter circuit is the buffer circuit BF11 of Figures 4, 5 and 6.

[0078] In this example, the BF11 circuit includes a first inverting stage having a PMOS transistor 702 in series with an NMOS transistor 704 between the supply NV node and ground, their respective gates being interconnected and configured to be driven by the clock signal from the clock signal generator 208. The midpoint (NM1) between transistors 702 and 704 of the first stage provides a signal inverse to the input signal and having a excursion equal to the voltage applied to the NV node (V12CK, VI1, VI1CK2 depending on the embodiment). The BF11 circuit includes a second inverting stage having a PMOS transistor 716 in series with an NMOS transistor 714 between the NV node and ground, their respective gates being interconnected at the midpoint NM1 of the first stage. The midpoint (NM2) between transistor 716 and transistor 714 of the second stage provides the inverse of the signal present at node NM1 with the same excursion amplitude.

[0079] The nodes are connected to the charge pump circuit 202, with node NM1 constituting the reverse output of the buffer circuit BF11 and node NM2 its direct output.

[0080] Fig. 8 is a set of graphs representing the time variations of signals from a charge pump regulator according to the example of Fig. 2 and according to the embodiment of Fig. 6.

[0081] More particularly, [Fig.8] is a set of graphs 8A, 8B and 8C representing, for graphs 8A and 8B the time variations of voltage of signals of a charge pump regulator according to the example of [Fig.2] and the embodiment of [Fig.6], and representing for graph 8C the voltage V11CK2 present at node NV of [Fig.6].

[0082] Graph 8A represents the residual oscillations of the VGATE signal from the example in [Fig.2] and [Fig.6] for a voltage V33 of 1.58V (respectively (VGATE)_[Fig.2]_1V58 and (VGATE)_[Fig.6]_1V58)) and 3.6V (respectively (VGATE)_[Fig.2]_3V6 and (VGATE)_[Fig.6]_3V6).

[0083] Graph 8B represents the residual oscillations of the output voltage VI1 of the example in [Fig. 2] and [Fig. 6] for a voltage V33 of 1.58V (respectively (V11)_[Fig. 2]_1V58 and (V11)_[Fig. 6]_1V58) and a voltage of 3.6V (respectively (V11)_[Fig. 2]_3V6 and (V11)_[Fig. 6]_3V6). Graph 8C represents the voltage V11CK2 of the example in [Fig. 6] for a voltage V33 of 1.58V and 3.6V.

[0084] It is thus visible that the peak-to-peak value of the residual oscillations of the output voltage VI1 of the regulator is reduced by half in the case of the example in [Fig.6] compared to the example in [Fig.2], thus going from 38.429mV to 19.598mV. It is also visible that the voltage V11CK2 varies very little regardless of the level 1.58 ((V11CK2)_1V58)) or 3.6V ((V11CK2)_3V6O)) of the supply voltage V33.

[0085] Fig.9 is a set of graphs illustrating the operation of the embodiment of Fig.6.

[0086] Figure 9 is a set of graphs 9A, 9B, and 9C representing a comparison between the time variation of signals from a charge pump regulator according to the embodiment of Figure 6 and the time variation of signals from a regulator of Figure 6 in which part of the regulator circuit is missing. More particularly, graphs 9A, 9B, and 9C represent the difference in behavior of the voltages VGATE, V1, and V1CK2 respectively in the case where transistor N1 is present (respectively (VGATE)_withN1, (V1)_withN1, and (V1CK2)_withN1)) and in the case where N1 is not present (respectively (VGATE)_withoutN1, (V1)_withoutN1, (V1CK2)_withoutN1).

[0087] It is evident that if NI is not present in the 302 step-down circuit, a loss of regulation can occur (shown here around times 120 to 140 ms). This can happen, for example, when the capacitance of the load Cload discharges more slowly than the capacitance Ctank. The presence of the NI transistor prevents this scenario by maintaining the voltage level at the level present at time 40 ms.

[0088] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will be apparent to those skilled in the art. In particular, the second charge pump circuit 410 can be optionally implemented in each of the embodiments shown in Figures 3 to 6 to facilitate, for example, the starting of the feedback loop 202.

[0089] Finally, the practical implementation of the described embodiments and variants is within the grasp of a person skilled in the art, based on the functional specifications given above. In particular, the implementation of a capacitive charge pump circuit is within the grasp of a person skilled in the art, as the described embodiments are compatible with any type of charge pump circuit, preferably capacitive. Furthermore, with regard to the BF11 circuit, a person skilled in the art can implement a circuit powered by the voltages VI1, V12CK, or VI1CK2, providing an output of a clock signal whose high-to-low level difference is on the order of V11, V12CK, or VI1CK2, respectively, or inverted signals whose high-to-low level difference is on the order of VI1, V12CK, or VI1CK2, respectively.

Claims

Demands

1. Regulator (104), comprising: - a first transistor (NPOWER) connecting an application node (NV33) of a first supply voltage (V33) to an output node (NV 11) of the regulator intended to provide a first regulated voltage (Vil); - a feedback loop providing a control signal (VGATE) to the first transistor and comprising: - a first charge pump circuit (202); - a control signal generator for the first charge pump circuit; and - a step-down circuit (302) between the control signal generator and the charge pump circuit; the control signal generator comprising a clock signal generator (208) between the output node (NV 11) and the step-down circuit (302).

2. Regulator according to claim 1, wherein the step-down circuit (302) includes a supply node (NV) configured to receive a voltage (VI1, V12CK, V11CK2) lower than the first supply voltage (V33).

3. Regulator according to claim 2, wherein the level-decreasing circuit (302) includes a buffer circuit (BF11) configured to be controlled at input by the clock signal.

4. Regulator according to claim 3, wherein said buffer circuit (BF11) comprises a first inverting stage having a PMOS transistor in series with an NMOS transistor, their respective control nodes being configured to be controlled by the clock signal, a midpoint (NM1) between said PMOS transistor and said NMOS transistor of the first stage being connected to the charge pump circuit (202).

5. Regulator according to claim 4, wherein said buffer circuit (BF11) comprises a second inverting stage having a PMOS transistor in series with an NMOS transistor, their respective control nodes being connected to said midpoint (NM1) of the first stage.

6. Regulator according to claim 5, wherein a midpoint (NM2) between said PMOS transistor and said NMOS transistor of the second stage is connected to the charge pump circuit.

7. Regulator according to claim 5 or 6, wherein a node of conduction of the PMOS transistors of the first and / or second stage is connected to said power supply node (NV) of the level step-down circuit (302).

8. Regulator according to any one of claims 2 to 7, wherein the output node (NV 11) is connected to said power node (NV) of the step-down circuit (302).

9. Regulator according to any one of claims 2 to 8, wherein the step-down circuit comprises a second and a third transistor (NO,NI) each having a conduction node connected to the supply node (NV) of the step-down circuit (302) and another conduction node connected to the application node (NV33) of the first supply voltage.

10. Regulator according to claim 9, wherein a control node of the second transistor (NO) is configured to receive the control signal (VGATE) from the first transistor (NPOWER).

11. Regulator according to any one of claims 9 or 10, wherein a control node of the third transistor (NI) is connected to an application node of a reference voltage (ReflV2_ech) lower than the first supply voltage (V33).

12. Regulator according to any one of claims 1 to 11, wherein the feedback loop (220) includes a comparator circuit (210) configured to compare the first voltage (Vil) to a first reference voltage (RefOV9_ech); the first charge pump circuit (202) being switched on or off as a function of said comparison.

13. Regulator according to any one of claims 1 to 12, comprising a second charge pump circuit (410) configured to provide a control signal to the first transistor (NPOWER) when the first charge pump circuit (202) is turned off.

14. Regulator according to claim 13 in its dependence on claim 12, comprising: - a second comparator circuit (COMP0V85) configured to compare the first voltage (VI1) to another reference voltage (Ref0V85_ech) lower than the first reference voltage (RefOV9_ech); and - a second control signal generator (230); the second charge pump circuit (410) being controlled by the second control signal generator as a function of the com- comparison between the first voltage (VI1) and the other reference voltage lower than the first reference voltage (RefOV9_ech).

15. Integrated circuit comprising a regulator according to any one of claims 1 to 14.

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