Bipolar transistor
The bipolar transistor design with a conductive element surrounding the collector region and a specific manufacturing process addresses current and frequency modulation challenges, enabling flexible operation and integration with MOSFET transistors on a single substrate.
Patent Information
- Application Number
- FR2023004036
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2023-04-21
- Publication Date
- 2025-04-25
- Estimated Expiration
- 2043-04-21
AI Technical Summary
Existing bipolar transistors face challenges in efficiently modulating current and transition frequency without significantly altering the collector voltage, and there is a need for improved manufacturing processes that can integrate both bipolar and MOSFET transistors on a single substrate.
The proposed solution involves a bipolar transistor design with a conductive element surrounding the collector region, made of polycrystalline silicon, and a manufacturing process that includes forming a conductive region within a substrate, followed by epitaxial growth and doping to create a transistor with an isolated grid field effect, allowing for voltage modulation between -5 V and 5 V to control current and frequency.
This design enables effective modulation of current and transition frequency, allowing for flexible operation without substantial changes in collector voltage, and supports integration of bipolar and MOSFET transistors on a single substrate, enhancing device versatility.
Smart Images
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Abstract
Description
Title of the invention: Bipolar transistor Technical field
[0001] The present description relates generally to electronic devices and more particularly to devices comprising bipolar transistors and their manufacturing methods. Prior art
[0002] A bipolar transistor is a semiconductor-based electronic device from the transistor family. Its operating principle is based on two PN junctions, one forward and the other reverse. Polarizing the reverse PN junction with a small electric current (sometimes called the transistor effect) allows a larger current to be controlled, following the principle of current amplification. Summary of the invention
[0003] One embodiment overcomes all or part of the drawbacks of electronic devices comprising known bipolar transistors.
[0004] One embodiment provides an electronic device comprising a bipolar transistor, the collector of the bipolar transistor comprising first and second regions, the second region being between the first region and the base of the bipolar transistor, the bipolar transistor comprising a conductive element at least partially surrounding the second portion and being located between the first portion and the base.
[0005] Another embodiment provides a method of manufacturing an electronic device comprising a bipolar transistor, the collector of the bipolar transistor comprising first and second regions, the second region being between the first region and the base of the bipolar transistor, the method comprising manufacturing a conductive element at least partially surrounding the second portion and being located between the first portion and the base.
[0006] According to one embodiment, the conductive element completely surrounds the second part.
[0007] According to one embodiment, the conductive element is made of polycrystalline silicon.
[0008] According to one embodiment, the bipolar transistor comprises a polarization pad connected to the conductive element.
[0009] According to one embodiment, the device comprises a MOSFET transistor in and on a portion of the substrate in and on which the bipolar transistor is formed.
[0010] According to one embodiment, the method comprises forming a first insulating layer in a substrate, etching a first cavity in the first layer and filling the first cavity with a conductive material so as to form a conductive region.
[0011] According to one embodiment, the method comprises forming a second insulating layer covering the conductive region, forming a second cavity passing through the conductive region so as to form the conductive element from the conductive region and forming a third insulating layer covering the exposed side walls of the conductive element.
[0012] According to one embodiment, the method comprises forming the first region of the collector by doping the substrate and forming the second region of the collector in the second cavity by epitaxial growth from the first portion.
[0013] According to one embodiment, the method comprises forming an insulated gate field effect transistor, portions of the insulated gate field effect transistor being formed during the step of doping the first region.
[0014] According to one embodiment, the method comprises forming the base on the second insulating layer.
[0015] According to one embodiment, the method comprises polarizing the conductive element to a positive potential if the bipolar transistor is of the NPN type and to a negative potential if the bipolar transistor is of the PNP type.
[0016] According to one embodiment, the potential has an absolute value less than 5V.
[0017] According to one embodiment, the value of the potential is independent of the value applied to the base, collector and emitter of the bipolar transistor.
[0018] According to one embodiment, the device comprises two bipolar transistors, the device being configured so that the conductive element of one of the transistors is biased at a voltage between 0 V and 5 V and the conductive element of the other transistor is biased at a voltage between -5 V and 0 V. Brief description of the drawings
[0019] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
[0020] [Fig.l] represents an embodiment of a device comprising a bipolar transistor; and
[0021] [Fig.2], [Fig.3], [Fig.4], [Fig.5], [Fig.6], [Fig.7], [Fig.8], [Fig.9], [Fig.10], [Fig.11], [Fig.12], [Fig.13], [Fig.14], [Fig.15] represent steps of a method of manufacturing the device of [Fig.l]. Description of the embodiments
[0022] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.
[0023] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.
[0024] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.
[0025] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.
[0026] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.
[0027] [Fig.l] shows an embodiment of a device 10 comprising a bipolar transistor 12. The device 10 may also comprise, for example, an insulated gate field effect transistor 14 or MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
[0028] Transistors 12 and 14 are formed in and on a substrate 16. Substrate 16 is a semiconductor substrate, for example made of silicon.
[0029] Portions 17a and 17b of the substrate 16 in which the transistor 12 and the transistor 14 are located, respectively, are separated from each other by insulating trenches 18, for example so-called deep trenches. The trenches 18 further separate the portions 17a and 17b from other portions of the substrate 16. Thus, the portions 17a and 17b are, for example, surrounded by the trenches 18. The trenches 18 are, for example, made of silicon oxide.
[0030] The portion of the substrate in which the transistor 14 is located comprises a semiconductor well 20, for example made of the material of the substrate, doped with a first conductivity type, for example P type. The well 20 is for example laterally surrounded by insulating regions, for example regions made of the same material as the trenches 18, for example silicon oxide. The well 20 is for example separated from the rest of the substrate by a semiconductor well 24, for example made of the same material as the well 20, doped with the conductivity type opposite to that of the well 20, for example N type.
[0031] The transistor 14 is formed in and on the well 20. In other words, the well 20 comprises regions 26 doped with the conductivity type opposite to that of the well 20, forming source and drain regions. The transistor 14 further comprises a gate 28 located on an upper face of the substrate 16.
[0032] The transistor 12 comprises collector regions 30, 32, and 34. The regions 30 are located in the substrate 16, and more precisely in the portion 17a. The regions 30 are for example doped with the same type as the region 24. Alternatively, the regions 30 may for example be doped with the opposite doping type to the type of the region 24. The regions 30 are for example doped with the N type. The transistor 12 comprises for example two regions 30 extending in parallel directions. Alternatively, the transistor 12 comprises a single region 30 forming a ring in the portion 17a. The single portion 30 then surrounds a region of the substrate that is preferably not doped.
[0033] Region 32 is located on regions 30. In other words, a lower face of region 32 is in contact with upper faces of regions 30. Region 32 electrically connects regions 30. Region 32 is for example doped with the same conductivity type as region 30. Region 32 preferably comprises a central part 32a and a peripheral part 32b. The peripheral part forms for example a ring surrounding part 32a.
[0034] The part 32a has for example a height less than the height of the part 32b. The parts 32a and 32b have for example a flat lower face. The lower faces of the parts 32a and 32b are therefore for example coplanar. The upper face of the part 32b is for example coplanar with the upper face of the trenches 18.
[0035] Region 34 is in contact with region 32. Region 34 extends from the upper face of portion 32a. For example, the height of region 34 is greater than the height difference between portions 32a and 32b. Thus, the upper face of region 34 is preferably at a higher level than the upper face of portion 32b.
[0036] Preferably, regions 30 have a substantially constant dopant concentration. Preferably, region 32 has a substantially constant dopant concentration. Regions 30 and 32 preferably have a dopant concentration greater than the dopant concentration of region 34, for example at least one hundred times greater, for example at least one thousand times greater. For example, the dopant concentration of regions 30 and 32 is for example greater than 1018 atoms / cm2, for example greater than 1020 atoms / cm2. For example, the dopant concentration in region 34 is less than 1016 atoms / cm2, for example between 1014 atoms / cm2 and 1016 atoms / cm2.
[0037] Transistor 14 comprises a conductive element 36 surrounding region 34. Element 36 is separated from the collector by an insulating region 38.
[0038] More precisely, the insulating region 38 is located on the upper faces of the parts 32a and 32b. The region 38 for example completely covers the upper face of the part 32a and partially the upper face of part 32b. The upper face of region 38 is for example planar. The upper face of region 38 is preferably coplanar with an upper face of region 34.
[0039] The conductive element 36 is buried in the region 38. In other words, the element 36 is separated from the region 34 by a portion of the region 38 and is separated from the region 32 by another portion of the region 38. The element 36 is preferably located opposite the upper face of the part 32a. For example, the element 36 is located opposite the portion of substrate surrounded by the regions 30. For example, the element 36 is not opposite the regions 30.
[0040] The conductive element 36 is for example made of polycrystalline silicon. The insulating region 38 is for example made of silicon oxide.
[0041] The element 36 comprises for example a portion (not shown) extending, for example in the layer 38, to a polarization pad (not shown). The polarization pad and the element 38 are connected to each other and electrically isolated from the base 40 and the collector 30, 32, 34.
[0042] The transistor 12 comprises a base 40. The base 40 comprises a central portion 40a and a peripheral portion 40b. The central portion 40a is laterally surrounded by the peripheral portion. The peripheral portion 40b thus forms a ring around the central portion 40a.
[0043] The central portion extends from region 34. In other words, the lower face of portion 40a is in contact with the upper face of portion 34. The upper portion of the lateral faces of portion 40a is in contact with portion 40b. The lower portion of the lateral faces of portion 40a is separated from portion 40b by an insulating element 42. Portion 40a and portion 40b are thus electrically connected. The entire base, i.e. portions 40a and 40b, is therefore electrically connected. Element 42 extends for example from layer 38. Element 42 extends for example in alignment with the part of layer 38 separating element 36 from region 34.
[0044] The base 40 preferably extends entirely over the layer 38 and the region 34. The layer 38 and the region 34 are entirely covered by the base 40 and the insulating element 42. Preferably, the lateral faces of the portion 40b and of the layer 38 are coplanar.
[0045] The base 40 is entirely separated from the element 36 by a portion of the layer 38. The element 36 is thus located between the base 40 and the region 32 of the collector. An upper face of the element 36 is thus opposite the base 40, for example only separated from the base by a portion of the insulating layer 38. Similarly, a lower face of the element 36 is opposite the region 32, for example only separated from the region 32 by a portion of the insulating layer 38. A lateral face of the element 36, more precisely the inner face, that is to say the face closest to the region 34, surrounds the region 34 and is preferably separated from the region 34 only by a portion of the layer 38.
[0046] The base 40 is made of a semiconductor material, for example silicon. The doping type of the base 40 is the opposite type to the doping of the collector, for example P type.
[0047] The transistor 12 further comprises an emitter region 44. The region 44 rests on the base 40. In particular, the region 44 extends above at least a part of the portion 40a and for example above a part of the portion 40b. Thus, a portion of the portion 40b is not covered by the emitter. A portion of the base 40 is therefore not covered by the emitter.
[0048] The region 44 is surrounded laterally by an insulating region 46. The region 46 thus covers, for example entirely, the lateral faces of the emitter region 44. The lower face of the emitter is entirely covered by insulating regions 48 and 50, with the exception of a portion of the lower face in contact with the part 40a. Said portion of the lower face is for example surrounded by the region 50, having for example an L-shaped profile. The region 48 surrounds for example the region 50 and is in contact with the region 46.
[0049] The emitter 44 is made of a semiconductor material, for example silicon. The doping type of the emitter 44 is the opposite type to the doping of the base, i.e. the same type as the collector, for example N type.
[0050] The transistor 12 further comprises metallizations 51, 52, 54 resting respectively on portions of the collector, the base and the emitter. The metallizations 51, 52, 54 are more precisely located respectively on the upper face of a portion of the portion 32b, on the upper face of a portion of the portion 40b and on the upper face of the emitter 44. The metallizations 51 are separated from the region 38 and from the portion 40b by spacers 51'. Similarly, the metallizations 52 are separated from the region 54 by spacers 52'.
[0051] During operation of the transistor, a potential is applied to the contact pad (not shown), and therefore to the element 36. The applied potential makes it possible to modulate the current in the collector, as well as the gain and the transition frequency of the transistor 12.
[0052] The value of the potential applied to the element 36 depends on the structure of the transistor 12. More precisely, the value of the potential depends on the thickness of the portion of the layer 38 located between the element 36 and the region 34 of the collector. In addition, the potential applied to the element 36 is for example a positive potential in the case where the collector, the base and the emitter have N-type, P-type and N-type dopings respectively, and is for example a negative potential in the case where the collector, the base and the emitter have P-type, N-type and P-type dopings respectively. For example, the absolute value of the potential is less than 5V, for example less than 3V.
[0053] According to one embodiment, the device 10 comprises two bipolar transistors 12. The transistors 12 are for example part of different circuits or are used for different applications, for example applications among: low noise amplifier or a bandgap reference voltage generator. For example, the element 36 of one of the transistors 12 is biased to a voltage between -5 V and 0 V and the element 36 of the other transistor 12 to a voltage between 0 V and 5 V.
[0054] Figures 2 to 15 represent a device resulting from the steps, preferably successive, of a method of manufacturing the device of [Fig.l]. More precisely, Figures 2 to 15 represent a device resulting from the steps, preferably successive, of a method of manufacturing a device comprising the bipolar transistor 12 and the MOSFET transistor 14.
[0055] [Fig.2] represents a device resulting from a step of a manufacturing process of the device of [Fig.l].
[0056] During this step, the trenches 18 are formed in the substrate 16. In addition, the insulating regions 22 are formed in the portion 17b of the substrate.
[0057] The step of [Fig.2] further comprises the formation of an insulating layer 56. The layer 56 is located at the location of the element 36 and the region 34 of the collector. Layer 56 is flush with the upper face of substrate 16. Layer 56 is preferably made of the material of layer 38.
[0058] [Fig. 3] represents a device resulting from another step of a method of manufacturing the device of [Fig. 1].
[0059] During this step, a cavity 58 is formed in the layer 56 from the upper face of the substrate. The height of the cavity 58 is preferably less than the height of the layer 56. Thus, the bottom of the cavity 58 is formed by the layer 56. Similarly, the side walls of the cavity 58 are formed by the layer 56.
[0060] [Fig.4] represents a device resulting from another step of a method of manufacturing the device of [Fig.l].
[0061] During this step, an insulating layer 60 is formed conformally on the structure resulting from the step of [Fig. 3], preferably over the entire structure. The layer 60 thus covers the side walls and the bottom of the cavity 58. The layer 60 does not fill the cavity 58. The layer 60 further covers the upper face of the substrate 16, the walls 18 and the regions 22.
[0062] [Fig.5] represents another step of a method of manufacturing the device of [Fig.l].
[0063] During this step, the cavity 58 is filled with a conductive region 62. The cavity 58 is for example entirely filled with the region 62. Preferably, the face upper face of region 62 is for example coplanar with the upper face of layer 60.
[0064] The conductive region 62 is for example made of polycrystalline silicon. The region 62 is for example doped. The region 62 has for example a concentration of dopants between 118 and 122 atoms per cm3.
[0065] [Fig.6] represents a device resulting from another step of a method of manufacturing the device of [Fig.l].
[0066] The step of [Fig.6] comprises a step of oxidation of the layer 62. Thus, the upper part of the layer 62 is oxidized and is replaced by an insulating layer 64. The layer 64 is for example made of silicon oxide. The upper face of the layer 64 is preferably coplanar with the upper face of the layer 60.
[0067] [Fig.7] represents a device resulting from another step of a method of manufacturing the device of [Fig.l].
[0068] The step of [Fig.7] comprises doping steps. More specifically, the step of [Fig.7] comprises the formation, by doping, of regions 20, 24 and 30. The step of [Fig.7] comprises the formation, by doping, of a layer 32', doped with the same type as region 32 and with the same concentration as region 32. Layer 32' preferably has a substantially constant thickness. Layer 32' preferably extends over the entire width of portion 17a of the substrate. Layer 32' extends above regions 30.
[0069] During this step, an etching mask 66 is further formed on the structure resulting from the doping step. The mask 66 comprises an opening at the location of the portion 17a of the substrate. The mask 66 preferably covers the structure entirely with the exception of the portion 17a of the substrate. In particular, the mask 66 covers the portion 17b of the substrate.
[0070] [Fig.8] represents a device resulting from another step of a method of manufacturing the device of [Fig.l].
[0071] During this step, a stack 68 of layers is formed on the structure, preferably over the entire structure, resulting from the step of [Fig.7]. The stack 68 is preferably formed conformally on the structure. The stack 68 thus covers the mask 66, the region 64 and the layer 60.
[0072] The stack 68 comprises a lower insulating layer 70. The layer 70 is for example made of silicon oxide. The layer 70 covers the upper face of the mask 66, the side walls of the mask 66 and the upper faces of the region 64 and of the layer 60.
[0073] The stack 68 comprises a semiconductor layer 72. The layer 72 is made of the material of the base of the transistor 12 of [Fig.l]. The layer 72 is for example made of silicon or polycrystalline silicon. The layer 72 preferably covers en- entirely layer 70.
[0074] The stack 68 comprises an insulating layer 74. The layer 74 is for example made of silicon nitride. The layer 74 preferably completely covers the layer 72.
[0075] The stack 68 comprises an insulating layer 76. The layer 76 is preferably made of a material that can be selectively etched relative to the material of the layer 74, i.e., etched at least twice as fast, for example at least five times as fast. The layer 76 is, for example, made of silicon oxide. The layer 76 preferably completely covers the layer 74.
[0076] The stack 68 comprises an insulating layer 78. The layer 78 is preferably made of a material that can be selectively etched relative to the material of the layer 76, i.e., etched at least twice as fast, for example at least five times as fast. The layer 78 is, for example, made of the material of the layer 74. The layer 78 is, for example, made of silicon nitride. The layer 78 preferably completely covers the layer 76.
[0077] [Fig.9] represents a device resulting from another step of a method of manufacturing the device of [Fig.l].
[0078] During this step, a cavity 80 is formed in the stack 68, in the region 64 and in the element 62. The cavity 80 is located at the location of the portion 40a and of the region 34. The cavity 80 extends from the upper face of the layer 78, that is to say the upper layer of the stack 68. The cavity 80 passes through the layers of the stack 68, the region 64, the element 62 and the layer 60. The cavity 80 thus extends to the upper face of the layer 32' under the region 62. The cavity 80 does not reach the layer 32'.
[0079] The cavity 80 has horizontal dimensions, that is to say in the plane of the upper face of the element 62, smaller than the dimensions of the element 62. The cavity 80 is formed so as to be surrounded by the non-etched portions of the element 62.
[0080] The step of [Fig.9] further comprises the formation of spacers 82 on the walls side walls of the cavity 80. The spacers 80 are preferably made of the material of the layer 60, for example silicon oxide. The spacers 82 cover the side walls of at least the layers 70 and 72.
[0081] The spacers 82 further cover the side walls of the element 62, so as to form the element 36.
[0082] The step of [Fig.9] further comprises the formation, by epitaxial growth, of a region 84 at the location of region 34. Region 84 is for example made of an intrinsic semiconductor material, for example made of the material of region 34, for example made of intrinsic silicon.
[0083] The step of [Fig.9] further comprises the formation, by epitaxial growth, of the portion 40a. Portion 40a is located on the upper face of portion 84. Portion 40a extends over the upper faces of the spacers 82. In other words, the upper face of the portion 40 is located at a level higher than the level of the upper face of the spacers 82.
[0084] [Fig. 10] represents a device resulting from another step of a method of fa construction of the device of [Fig.l].
[0085] During this step, the region 50 is formed. More precisely, the step of [Fig. 10] comprises the formation of a layer (not shown) made of the material of the layer 76, for example silicon oxide. Said layer (not shown) is formed conformally on the structure resulting from the step of [Fig. 9]. In particular, the layer (not shown) covers the upper face of the portion 40a and the side walls of the cavity 80 not covered by the region 84 and of the portion 40a
[0086] The step of [Fig. 10] comprises the formation of unrepresented spacers. The unrepresented spacers are made of a material selectively etchable relative to the material of the unrepresented layer. The unrepresented spacers cover the portions of the unrepresented layer corresponding to region 50. The portions of the unrepresented layer not covered by the spacers are then etched and the spacers are removed.
[0087] Layer 78 is then removed.
[0088] [Fig. 11] represents a device resulting from another step of a method of fa construction of the device of [Fig.l].
[0089] During this step, a layer 86 made of the material of the emitter 44 of [Fig. 1] is formed on the structure resulting from the step of [Fig. 10]. The layer 86 is thus formed on the layer 76. The layer 86 preferably completely covers the layer 76. The layer 86 covers at least the layer 76 in the portion 17a. The upper face of the layer 86 is preferably flat.
[0090] The step of [Fig. 11] further comprises the formation of an insulating layer 88. The layer 88 is for example made of silicon oxide. The layer 88 preferably completely covers the upper face of the layer 86.
[0091] [Fig. 12] represents a device resulting from another step of a method of fa construction of the device of [Fig.l].
[0092] During this step, layers 76, 86 and 88 are etched so as to form region 48, emitter region 44 and a region 90. Region 48 is formed from layer 76. Region 44 is formed from layer 86. Region 90 is formed from layer 88. The side faces of regions 48, 44, 90 are preferably coplanar.
[0093] [Fig. 13] represents a device resulting from another step of a method of fa construction of the device of [Fig.l].
[0094] During this step, the insulating region 46 is formed on the side walls of the regions 44, 48 and 90. Region 44 is thus surrounded by insulating material. Region 44 is entirely surrounded by insulating material, except for the part of the lower face of region 44 in contact with portion 40a.
[0095] Further, the step of [Fig. 13] includes removing the insulating layer 74.
[0096] [Fig. 14] represents a device resulting from another step of a method of manufacturing the device of [Fig.l].
[0097] The step of [Fig. 14] comprises epitaxial growth of the layer 72, for example throughout the structure, for example at least in the portion 17b. The layer 72 grows at least up to the level of the upper face of the portion 40a. Thus, the layer 72 is in contact with the portion 40a.
[0098] The step of [Fig. 14] further comprises etching layers 72 and 70 so as to form portion 40b and region 38.
[0099] [Fig. 15] represents a device resulting from another step of a method of manufacturing the device of [Fig.l].
[0100] During this step, the spacers 51' and 52' are formed on the walls of the region 46 and on the walls of the layer 38 and of the portion 40b.
[0101] The step of [Fig. 15] further comprises the removal of the insulating layer 90, located on the upper face of the region 44.
[0102] The step of [Fig. 15] further comprises the formation of the metallizations 51, 52 and 54.
[0103] The method of manufacturing the device of [Fig.l] comprises steps not illustrated by Figures 2 to 15. In particular, the method of manufacturing the device of [Fig.l] comprises, following the steps illustrated by Figures 2 to 15, the steps of forming the transistor 14 in the portion 17b.
[0104] An advantage of the described embodiments is that it is possible to modulate the current flowing through the collector of the bipolar transistor by applying a voltage in the element 36, for example a voltage between -5 V and 5 V. It is thus possible to modulate the transition frequency and the gain of the bipolar transistor. In addition, the transition frequency can be modified without significantly modifying the open collector breakdown voltage.
[0105] Another advantage of the described embodiments is that it is possible to modulate these characteristics during the life of the device, after manufacture.
[0106] Another advantage of the described embodiments is that it is possible to form in and on the same substrate bipolar transistors as described and MOSFET transistors as described.
[0107] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, according to one embodiment, the conduction element 36 could only partially surround region 34. For example, element 36 could only face one, two or three side faces of region 34.
[0108] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.
Claims
Demands
1. A method for manufacturing an electronic device (10) comprising a bipolar transistor (12), the collector (30, 32, 34) of the bipolar transistor comprising first (30, 32) and second (34) regions, the second region (34) being between the first region (30, 32) and the base (40, 40a, 40b) of the bipolar transistor, the method comprising manufacturing a conductive element (36) at least partially surrounding the second part (34) and being located between the first part (30, 32) and the base (40, 40a, 40b), the method comprising forming a first insulating layer (56) in a substrate (16), etching a first cavity (58) in the first layer (56) and filling the first cavity (58) with a conductive material so as to form a conductive region (62), the method comprising forming a second layer insulating (64) covering the conductive region (62),the formation of a second cavity (80) passing through the conductive region (62) so as to form the conductive element (36) from the conductive region and the formation of a third insulating layer (82) covering the exposed lateral walls of the conductive element (36).
2. Method according to claim 1, wherein the conducting element (36) completely surrounds the second part (34).
3. Method according to claim 1 or 2, wherein the conducting element (36) is made of polycrystalline silicon.
4. A method according to any one of claims 1 to 3, wherein the bipolar transistor includes a biasing pad connected to the conducting element (36).
5. A method according to any one of claims 1 to 4, wherein the device comprises a MOSFET transistor (14) in and on a portion (17b) of the substrate (16) in and on which the bipolar transistor is formed.
6. A method according to any one of claims 1 to 5, wherein the method comprises the formation of the first region (30, 32) of the collector by substrate doping and the formation of the second region (34) of the collector in the second cavity (80) by epitaxial growth from the first part (30, 32).
7. A method according to claim 6, wherein the method comprises the formation of an insulated-gate field-effect transistor (14), portions of the insulated-gate field-effect transistor being formed during the first region doping step.
8. A method according to any one of claims 1 to 7, wherein the method comprises the formation of the base on the second insulating layer (64).
9. Electronic device (10) comprising a bipolar transistor (12), the collector (30, 32, 34) of the bipolar transistor comprising first (30, 32) and second (34) regions, the second region (34) being between the first region (30, 32) and the base (40, 40a, 40b) of the bipolar transistor, the bipolar transistor comprising a conductive element (36) at least partially surrounding the second part (34) and being located between the first part (30, 32) and the base (40, 40a, 40b), the device being obtained by a method according to any one of claims 1 to 8.
10. A method of using a device according to claim 9, wherein the method comprises biasing the conductive element (36) to a positive potential if the bipolar transistor is of the NPN type and to a negative potential if the bipolar transistor is of the PNP type.
11. Method according to claim 10, wherein the potential has an absolute value less than 5V.
12. A method according to claim 10 or 11, wherein the potential value is independent of the value applied to the base, collector and emitter of the bipolar transistor.
13. A method according to any one of claims 10 to 12, wherein the device comprises two bipolar transistors (12), the device being configured so that the conductive element (36) of one of the transistors (12) is biased at a voltage between 0 V and 5 V and the conductive element of the other transistor (12) is biased at a voltage between -5 V and 0 V.