SUBSTRATE COMPRISING A THICK BURIED DIELECTRIC LAYER AND METHOD FOR PREPARING SUCH A SUBSTRATE

Abstract

The invention relates to a final substrate (S) comprising, successively in contact with each other, a top layer (5) of semiconductor material, a dielectric layer (4) having a thickness greater than 200 nm, an electrical charge trapping layer (2), and a base substrate (3). The final substrate (S) has a curvature of less than 60 micrometers, preferably less than 40 micrometers. An exposed surface of the top layer (5) has a roughness of less than 0.3 nm in root mean square measurement over a 30-micrometer by 30-micrometer area. The invention also relates to a method for preparing such a substrate. Figure 3

Description

Title of the invention: SUBSTRATE COMPRISING A THICK BURIED DIELECTRIC LAYER AND METHOD FOR PREPARING SUCH A SUBSTRATE FIELD OF INVENTION

[0001] The present invention relates to a semiconductor-on-insulator substrate comprising a charge-trapping layer, the insulating (or dielectric) layer having a relatively large thickness, greater than 200 nm. These substrates find notable application in the field of radio frequency integrated devices, i.e., electronic devices processing signals with frequencies between approximately 3 kHz and 300 GHz, for example in the field of telecommunications (telephony, Wi-Fi, Bluetooth, etc.). These substrates also find application in the field of photonics. The invention also relates to a method for manufacturing such a substrate. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Document WO2022023630 reveals that the formation of a final semiconductor-on-insulator substrate comprising a charge-trapping layer and a thick dielectric layer (greater than 200 nm according to this document) is particularly challenging. According to the introduction of this document, it is industrially preferable to place this dielectric layer on the substrate supporting the final substrate, and the dielectric layer, made of silicon oxide, can be obtained by oxidizing a superficial portion of the charge-trapping layer. The oxidation step tends to deform the substrate supporting and create a significant curvature (referred to by the English term "bow" in semiconductor terminology, which is defined as the deviation between a central point on the substrate's median surface and a reference plane).This curvature is generally measured by interferometry, for example using equipment such as the Wa-ferSight™ from KLA. The presence of such curvature makes the transfer of the top layer of the substrate difficult, and more generally, the handling of the substrate in the production line with conventional equipment. The aim is generally to limit this curvature to less than 60 micrometers or, preferably, less than 40 micrometers for a disc-shaped substrate with a diameter of 300 mm.

[0003] Furthermore, in many applications, it is essential that the exposed surface of the top layer be very smooth, and have a roughness well below 0.5 nm in root mean square measurement on an atomic force measurement field of 30 micrometers by 30 micrometers. To obtain a top layer with such roughness, it is known to apply to the substrate, after transferring the top layer onto the support substrate, one or a plurality of thermal annealing(s) in neutral or reducing atmospheres.

[0004] This may involve so-called "rapid thermal annealing" (or "rapid thermal anneau," as it is known in English), which consists of exposing the exposed surface of the top layer to the annealing atmosphere at temperature for a very short time, less than 2 minutes. The neutral or reducing atmosphere of the annealing chamber is rapidly heated to the treatment temperature, which can reach 1200°C, and then cooled during heating / cooling ramps that can exceed 50° / s. During this treatment, the substrate is held by its rear face in the furnace chamber, on a plurality of supports. The applicant has observed, however, that this type of annealing generates lines or planes of dislocations at the points of contact between the substrate and the support. These lines or planes of dislocations result from thermal and gravitational stresses experienced by the substrate during the very rapid thermal excursion it undergoes.They sometimes render the substrate unsuitable for use in subsequent stages of microelectronic component manufacturing or, at the very least, can lead to the formation of non-functional components when these are placed directly over these defects.

[0005] As an alternative to rapid annealing, a long annealing process, often referred to in the field as "batch annealing" (using the English term "batch annealing"), can be applied during the finishing stage of substrate preparation. This process is known as batch annealing because the substrates are generally placed in batches in the furnace chamber, in a horizontal or vertical arrangement. The chamber atmosphere is gradually raised in gentle ramps of a few degrees per minute to reach a treatment temperature typically around 1100°C. The treatment is continued for an extended period at this temperature, from a few minutes to several hours. The gentle ramps limit the thermal stresses experienced by the substrate and reduce the appearance of dislocation lines or planes observed after rapid heat treatment.

[0006] The applicant observed, as shown in the graph in [Fig. 1], that the substrate curvature (on the y-axis of this graph) caused by the curvature of the supporting substrate after oxidation of the trapping layer could be compensated for by exposing the substrate during the finishing step to a high temperature (abscissa of the graph), strictly above 1050°C to reduce this curvature to below 40 micrometers, and approaching 1100°C to reduce it to below 30 micrometers. In the graph in [Fig. 1], the data collected at 1050°C, 1075°C, and 1100°C were obtained after long annealing cycles, while the data collected at 1200°C were obtained after rapid annealing cycles.

[0007] The applicant also observed that the roughness of the exposed surface of the top layer of the substrate tended to decrease with increasing temperature when the dielectric layer (formed by oxidation of the support's trapping layer) had a thickness greater than 200 nm. This is shown in the measurements plotted in [Fig. 2], which shows the roughness of the exposed surface of the top layer (measured by atomic force over a 30-micrometer by 30-micrometer measurement field) at the center (reference point "C") and at the edge (reference point "B"), for increasing annealing temperatures. These annealings were carried out on final substrates, each with a buried dielectric layer of 400 nm, obtained by oxidation of the support substrate's trapping layer as described above. In this case, the roughness tends to increase almost exponentially with the annealing temperature.It appears that the stack forming the substrate becomes thermally unstable when the dielectric layer has a significant thickness, exceeding 200 nm, this instability leading to a degradation of the substrate's free surface state. The finishing heat treatment causes this thermal instability, possibly through stress relaxations stored in this stack, this relaxation manifesting on the surface of the top layer as increased roughness.

[0008] Also, it does not appear easy to obtain a final substrate of the semiconductor-on-insulator type comprising a thick dielectric layer, with a thickness greater than 200 nm, exhibiting both low roughness (below the limit indicated in a previous passage) and low curvature, less, for example, than 60 micrometers and, advantageously, free from an excessive number of dislocation planes or lines. OBJECT OF THE INVENTION

[0009] One object of the invention is to provide a solution to this problem. More specifically, the invention provides a substrate comprising a thick buried dielectric layer, greater than 2000 nm, which exhibits both low roughness and low curvature. The invention also provides a method for preparing such a substrate. BRIEF DESCRIPTION OF THE INVENTION

[0010] To achieve this goal, the object of the invention proposes a method for preparing a final substrate comprising a thick buried dielectric layer, the method comprising: - a step of preparing a support substrate comprising an electrical charge trapping layer disposed on a base substrate; - a step of forming a dielectric layer with a thickness greater than 200 nm on the electrical charge trapping layer; - a step of transferring a top layer comprising a semiconductor material onto the dielectric layer; - a finishing step on the exposed face of the top layer.

[0011] According to the invention, the dielectric layer formation step is carried out by high-density plasma chemical vapor deposition and the finishing step includes a first annealing conducted in a neutral or reducing atmosphere at a temperature above 1050°C for a period of more than 30 minutes.

[0012] Surprisingly, this process makes it possible to obtain a final substrate exhibiting both reduced curvature and a satisfactory surface condition.

[0013] According to other advantageous and non-limiting features of the invention, taken alone or in any technically feasible combination: • the dielectric layer formation step includes, after high-density plasma chemical vapor deposition of the dielectric layer, a densification annealing of the support substrate; • densification annealing is carried out in a neutral atmosphere at a temperature below 1000°C and for a duration of less than Ih; • the finishing stage includes, before and / or after the first annealing, a thinning of the top layer; • Thinning is achieved by sacrificial oxidation. • the finishing stage includes a second annealing, the second annealing being carried out in a neutral or reducing atmosphere at a temperature above 1050°C for a period of less than 2 minutes; • the neutral or reducing atmosphere of the first annealing includes or is made up of argon; • the dielectric layer formation step does not involve polishing the exposed face of the dielectric layer; • the semiconductor material is silicon; • the dielectric layer is made of silicon dioxide; • the dielectric layer has a thickness greater than or equal to 400 nm; • The top layer transfer step includes an implantation step of so-called "light" species in a donor substrate to form a fragile plane, the assembly of the donor substrate with the support substrate, and the fracturing of the donor substrate at the level of the fragile plane.

[0014] According to another aspect, the invention proposes a final substrate comprising, successively in contact with each other, a top layer of semiconductor material, a dielectric layer having a thickness greater than 200 nm, an electrical charge trapping layer and a base substrate.

[0015] According to the invention, the final substrate has an exposed surface of the layer in semiconductor material having a roughness of less than 0.3 nm in root mean square measurement over a field of 30 micrometers by 30 micrometers and a curvature of less than 60 micrometers, preferably less than 40 micrometers.

[0016] According to other advantageous and non-limiting features of this other aspect of the invention, taken alone or in any technically feasible combination: • the top layer is made of silicon; • the dielectric layer is made of silicon oxide; • the final substrate is in the form of a disc of 300 mm or more diameter ; • the final substrate has a cumulative length of planes or lines of dislocations, measured by deflectometry, of less than 20 mm. Brief description of the drawings

[0017] Other features and advantages of the invention will become apparent from the detailed description of the invention which follows with reference to the accompanying figures in which:

[0018] [Fig.1]

[0019] Fig. 1 represents a graph relating the curvature of a silicon-on-insulator substrate to the temperature of an anneal applied during a finishing step in the preparation of this substrate;

[0020] [Fig.2]

[0021] Fig. 2 represents a graph relating, for a buried dielectric layer of 400nm, the roughness of the exposed surface of the top layer of a final substrate to the temperature of an anneal applied during a finishing step of preparation of this substrate;

[0022] [Fig.3]

[0023] Figure [Fig.3] represents a substrate according to the invention;

[0024] [Fig.4a]

[0025] [Fig.4b]

[0026] [Fig.4c]

[0027] [Fig.4d]

[0028] Figures 4a, 4b, 4c, 4d represent a method for preparing a final substrate according to the present invention;

[0029] [Fig.5a]

[0030] [Fig.5b]

[0031] Figures 5a, 5b respectively represent measurements of curvature and roughness carried out during experiments which led to the invention;

[0032] [Fig.6]

[0033] Figure 6 illustrates the benefit of using a "long" annealing process, rather that a "rapid" annealing in terms of dislocation-type defects in a manufacturing process according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0034] With reference to [Fig.3], a substrate S of an embodiment comprises a base substrate 3, an electrical charge trapping layer 2 (referred to as the "trapping layer" in the remainder of this description) disposed on the base substrate 3, a dielectric layer 4 disposed on and directly in contact with the trapping layer 2 and a top layer 5 disposed on the dielectric layer 4. The base substrate 3 provided with the charge trapping layer and the dielectric layer 4 forms a support substrate 1 for the final substrate S.

[0035] The substrate S (and therefore the support substrate 1) can take the form of a wafer, for example in the form of a disc with a diameter of 300 mm. The substrate has a curvature of less than 60 micrometers, preferably less than 40 micrometers, to make it compatible with subsequent component manufacturing steps.

[0036] The base substrate 3 has a thickness of several hundred microns. Preferably, the base substrate 3 has a high resistivity, greater than 100 or 1000 ohms·cm, and even more preferably greater than 3000 ohms·cm. This limits the density of charges, holes or electrons, that are likely to move within the base substrate 3, and thus degrade the radio frequency performance of the final substrate S. However, the invention is not limited to a base substrate 3 with such a high resistivity, and it also provides RF performance advantages when the base substrate 3 has a more compliant resistivity, less than 1000 ohms·cm, on the order of a few hundred ohms·cm, or 100 ohms·cm or less.

[0037] For reasons of availability and cost, the basic substrate 3 is preferably made of silicon, and in particular single-crystal silicon. It may, for example, be a CZ substrate with a low interstitial oxygen content, which, as is well known, has a resistivity that can exceed 1000 ohms·cm. Alternatively, the basic substrate 3 may be made of another material: for example, sapphire, silicon carbide, silicon-germanium, III-V materials, glass, etc. It may also be a more standard single-crystal CZ substrate with a resistivity of less than 1000 ohms·cm, or a CZ substrate with a high or medium interstitial oxygen content, which may be n- or p-doped and has a resistivity of approximately 500 ohms·cm or less.

[0038] The support substrate 1 also includes a trapping layer 2, disposed on and in direct contact with the base substrate 3. The trapping layer 2 has a resistivity greater than 500 ohm.cm and preferably greater than 1000 ohm.cm, and even more preferably greater than 10 kohm.cm. As is well known The trapping layer itself functions to trap charge carriers that may be present in the support 1 and to limit their mobility. This is particularly relevant when the substrate S includes a semiconductor structure emitting an electromagnetic field that penetrates the support substrate 1, and is therefore capable of interacting with and causing these charges to move. The trapping layer 2 typically has a thickness between 1 micron and 15 microns, or even 20 microns.

[0039] The trapping layer 2 can generally be made of a non-single-crystal semiconductor layer with structural defects such as dislocations, grain boundaries, amorphous zones, gaps, inclusions, pores, etc. These structural defects trap charges that may circulate in the material, for example, at incomplete or dangling chemical bonds. This prevents conduction in the trapping layer, which consequently exhibits high resistivity.

[0040] For the same reasons of availability and cost already mentioned, the trapping layer 2 is preferably made of polycrystalline silicon. However, it may be made of or comprise another polycrystalline semiconductor material. This charge-trapping layer 2 can, of course, be formed by techniques other than those involving a layer made of polycrystalline silicon. This layer may also include carbon or be made of or comprise silicon carbide or a silicon-carbon alloy, for example, in the form of interlayers inserted within a layer of polycrystalline silicon. When the trapping layer 2 is made of silicon carbide or a silicon-carbon alloy, its thickness is preferably from a few nm (for example, 2 nm) to a few tens of nm (for example, 50 nm).Alternatively, the electrical traps in layer 2 can be created by bombarding a surface area of ​​the base substrate 3 with relatively heavy ions (e.g., argon) to create crystalline defects capable of trapping electrical charges. A charge-trapping layer 2 can also be formed from a porous material, for example, by porosification of a surface area of ​​the base substrate 3 when it is silicon. The trapping layer can also comprise a silicon-rich oxide with an atomic concentration of silicon between 50% and 99.9%. This silicon-rich oxide may also contain nitrogen. It may also include crystalline silicon inclusions smaller than 10 nm, and preferably smaller than 5 nm. Alternatively, it can be polycrystalline and include amorphous inclusions.

[0041] In any event, the trapping layer 2 has a high resistivity greater than 500 ohm.cm. To this end, the trapping layer 2 is not intentionally- It is doped, meaning that it has a concentration of charge-carrying dopant less than 10¹⁴ atoms per cubic centimeter. It can be rich in nitrogen or carbon to improve its resistivity characteristic.

[0042] Returning to the general description of [Fig. 3], the support substrate 1 also includes a dielectric layer 4 directly disposed on the trapping layer 2. By way of example, the dielectric layer 4 may be made of or comprise silicon dioxide or silicon nitride. It may also be a stack of these materials. The thickness of the dielectric layer 4 can usually be between 1 µm and 10 microns, but for the purposes of this description, this layer has a substantial thickness, greater than 200 nm, and preferably between 200 nm and 1000 nm.

[0043] The substrate S comprises an upper layer 5, on and in contact with the dielectric layer 4 of the supporting substrate 1. The thin layer is usually made of monocrystalline silicon, but it could be any other material depending on the nature of the device intended to be formed on it. When the substrate S is intended to receive semiconductor integrated components in the fields of electronics or photonics, the thin layer 5 can thus be composed of monocrystalline silicon, or of any other monocrystalline semiconductor material such as germanium, silicon germanium, or silicon carbide.

[0044] In all cases, and regardless of the nature of the upper layer, it is very slightly rough, and its exposed surface has a roughness of less than 0.3 nm in mean square measurement over a field of 30 micrometers by 30 micrometers.

[0045] The ability to have a thick (over 200 nm) buried dielectric substrate exhibiting both low surface roughness and low curvature is a very remarkable aspect of the present invention. Furthermore, this substrate exhibits a low density of dislocation planes or lines. These dislocation planes or lines can be measured by inspection equipment employing a deflectometry technique, as described, for example, in US patent 7812942. The aim is generally to minimize the cumulative length of these dislocation planes or lines, for example, below the threshold value of 20 mm, which is indeed the case for a substrate according to the invention. Substrate preparation

[0046] A method for preparing the substrate shown in Figures 4a to 4d is now presented.

[0047] In a first preparation step shown in [Fig. 4a], the support substrate 1 is prepared. The fabrication of the trapping layer 2 on the base substrate 3, when it is made of polycrystalline silicon or formed of a silicon-rich oxide, can be carried out with standard industrial deposition equipment. It can thus This could be a deposition of the RPCVD type (Remote Plasma Enhanced Chemical Vapor Deposition) or the PECVD type (Plasma Enhanced Chemical Vapor Deposition). It could also be an LPCVD (Low Pressure Chemical Vapor Deposition). However, as previously discussed, the formation of the trapping layer on or within the base substrate 3 can be achieved in many other ways, for example, by implanting heavy species or by porosification of a surface layer of the base substrate 3.

[0048] Optionally, during this preparation step, the formation of a thin dielectric layer on the base substrate 3 may be provided for, for example by oxidation or deposition of a thickness of oxide, before forming the trapping layer 2.

[0049] In a second step of the preparation process shown in [Fig. 4b], the dielectric layer 4, having a thickness greater than 200 nm, is formed. In general, there are many possibilities for forming this dielectric layer 4 so that it is ultimately embedded in the substrate S. It can be formed on the side of the supporting substrate 1 by deposition or by treatment (oxidation, for example) of the trapping layer 2. It can also be formed on the side of a so-called "donor" substrate that provides the upper layer 5. According to the present invention, and for reasons that will become apparent in the remainder of this description, the dielectric layer 4 is produced on the trapping layer 3 by high-density plasma chemical vapor deposition (HDP).This technique simultaneously involves the deposition and ion sputtering (or "sputtering," as it is known in the industry) of this dielectric layer 4. Its main advantage is that it produces a thick, smooth layer, meaning that its formation stage can be completed without any smoothing treatment such as polishing. Following this dielectric layer formation stage, the substrate 1 is available. This substrate can exhibit significant curvature, sometimes exceeding 60 micrometers when the substrate 1 is circular and has a diameter of 300 mm.

[0050] It should be noted that the process for preparing the support substrate 1 can also incorporate an annealing step for the dielectric layer 4. This annealing, known as densification annealing, is advantageously carried out in a neutral atmosphere. It is performed at a temperature exceeding the deposition temperature of the dielectric layer 4, and preferably in less than 1000°C, for a relatively short period of less than 1h, such as 30 minutes.

[0051] Continuing the description of the manufacturing process for the final substrate S, this process includes, in a third step following the second step, the transfer of the upper layer 5, comprising a semiconductor material, onto the dielectric layer 4. As is well known, this transfer can be achieved by assembling a free face of a donor substrate 1' to the support substrate 1, preferably by molecular adhesion. Since the dielectric layer 4 has been previously formed on the support substrate 1, it is not necessary for the donor substrate 1' to itself have such a dielectric layer. However, it can be provided that this donor substrate has a thin layer of dielectric (for example, less than 150 nm). Preferably, though, the donor substrate is devoid of any intentionally formed surface dielectric layer.The nature of the donor substrate 1' is chosen according to the desired nature of the top layer 5, as already described in a previous section of this presentation. It can therefore be a substrate made of a single-crystal semiconductor, for example silicon.

[0052] After this assembly step, the donor substrate is reduced in thickness to form the top layer 5, as shown in [Fig. 4d]. This reduction step can be carried out by mechanical and / or chemical thinning. Preferably, however, the thickness reduction of the donor substrate 1' is achieved by fracturing at a previously introduced weakening plane, for example, according to the principles of Smart Cut™ technology. In accordance with the principles of this technology, the transfer of the top layer 5 includes a step of implanting so-called "light" species, for example, hydrogen and / or helium ions, into the donor substrate 1' to form a weak plane. This weak plane, together with the free surface of the donor substrate, defines the top layer 5 that will be transferred.After assembly of the donor substrate 1' with the support substrate 1, the donor substrate is fractured at the level of the brittle plane by application of mechanical or thermal force.

[0053] After this thinning or, preferably, fracturing step, finishing steps of the thin film 5, such as heat treatment under a reducing or neutral atmosphere, sacrificial oxidation can be linked to the thickness reduction step.

[0054] Quite surprisingly, the applicant discovered that it was possible to obtain both reduced curvature and a satisfactory surface finish when the dielectric layer 4 is formed by high-density plasma chemical vapor deposition and when the finishing step includes annealing conducted in a neutral or reducing atmosphere at a temperature above 1050°C for a duration exceeding 30 minutes.

[0055] Figures 5a and 5b thus show the measured characteristics of the curvature of the final substrate S ([Fig. 5a]) and the roughness of the exposed surface of the upper layer 5 ([Fig. 5b], this roughness measurement, expressed in nm, being obtained by atomic force on a measurement field of 30 micrometers by 30 micrometers) of a substrate prepared according to the process just described. Figure 5a shows that it is possible to reduce the curvature of the final substrate S by increasing the annealing temperature of the finishing step. When this annealing heats the substrate to 1050°C, this curvature is on the order of 55 micrometers, which is already very satisfactory. It is noted that the results at 1200°C obtained using rapid annealing also allow the reduction of the substrate curvature, but can generate dislocation-type defects, as mentioned in the introduction to this request.

[0056] It is also observed in [Fig. 5b], and unexpectedly, that the measured roughness of the upper layer 5 after the application of the finishing step annealing is stable with increasing temperature and remains below 0.3 nm in root mean square measurement, which is also very satisfactory, both at the substrate edge (mark "B") and at its center (mark "C"). It should be noted that the applicant's preliminary observations, reported in [Fig. 2], showed increasing roughness of the exposed surface of this upper layer 5 with increasing temperature.

[0057] A preparation process according to the invention therefore exploits these results to propose different finishing sequences for a finishing step. In all these possible sequences, there is at least one annealing, designated "first annealing," this first annealing being carried out in a neutral or reducing atmosphere at a temperature above 1050°C for a duration exceeding 30 minutes. In all cases, the dielectric layer 4, embedded in the final substrate, was obtained by high-density plasma chemical vapor deposition on the charge-trapping layer 2.

[0058] Thus, the finishing step may include at least one thinning step of the top layer 5. This at least one thinning step may be carried out before and / or after the first annealing. The finishing sequence carried out during the finishing step may therefore correspond to a thinning-annealing, annealing-thinning, or thinning-annealing-thinning sequence. This thinning of the layer may, in particular, be carried out by sacrificial oxidation (i.e., the oxidation of a surface thickness of this layer, followed by the removal of this oxidized thickness) of the top layer.

[0059] Furthermore, the finishing step may include annealing steps other than the first annealing already described. Thus, in one embodiment, the finishing sequence may in The process includes a second rapid annealing, this second annealing being carried out in a neutral or reducing atmosphere at a temperature above 1050°C for a duration of less than 2 minutes. The second annealing may be carried out before or after the first annealing.

[0060] Preferably, the neutral or reducing atmosphere used during the first annealing and, where applicable, during the second annealing is composed mainly or exclusively of Argon.

[0061] The temperature of the first annealing can preferably be chosen in the range of 1050°C to 1100°C, so as not to affect the quality of the trapping layer 2. An excessive thermal budget applied during the finishing step could indeed alter its crystallinity and electrical efficiency. To further improve the smoothing effect of this first annealing, even at the lower end of the preferred temperature range, the equipment in which this annealing is carried out can follow the guidelines of document EP3011590B1.

[0062] To avoid generating dislocation-type defects in the final substrate, it is preferable to avoid introducing rapid annealing in the finishing sequence, although this is not entirely excluded.

[0063] Figure 6 illustrates the benefit of using a "long" anneal only in the finishing sequence, rather than a "fast" anneal, in terms of dislocation defects. The left-hand side of this figure shows a map of the dislocations present in a final substrate for which the finishing sequence, including annealing in a neutral or reducing atmosphere at a temperature above 1050°C for more than 30 minutes, is performed without a fast anneal. The absence or near absence of such defects can be observed in this left-hand side.

[0064] The right-hand side of this figure shows a map of the dislocations present in a final substrate that has undergone rapid heat treatment. The difference, in terms of defects, compared to the left-hand side is clearly visible.

[0065] These dislocation maps can be prepared by inspection equipment implementing a deflectometry technique, as shown for example in document US7812942.

[0066] Regardless of the finishing sequence used, the preparation process just described makes it possible to produce a final substrate comprising, successively in contact with each other, a top layer 5 of semiconductor material, for example silicon, a dielectric layer with a thickness greater than 200 nm, an electrical charge trapping layer, and a base substrate. The dielectric layer may, in particular, have a thickness greater than or equal to 400 nm. The exposed surface area of ​​the top layer of semiconductor material of this The final substrate exhibits a roughness of less than 0.3 nm in root mean square measurement over a 5 micrometer by 5 micrometer field and a curvature of less than 60 micrometers, preferably less than 40 micrometers. Advantageously, this final substrate has a cumulative length of dislocation planes or lines of less than 20 mm.

[0067] Of course the invention is not limited to the modes of implementation described and alternative embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

Demands

1. A method for preparing a final substrate (S) comprising a thick buried dielectric layer (4), the method comprising: - a step of preparing a support substrate (1) comprising an electrical charge trapping layer (2) disposed on a base substrate (3); - a step of forming the dielectric layer (4) having a thickness greater than 200 nm on the electrical charge trapping layer (2); - a step of transferring a top layer (5) comprising a semiconductor material onto the dielectric layer (4); - a step of finishing the exposed face of the top layer (5);the preparation process being characterized in that the dielectric layer formation step (4) is carried out by high-density plasma chemical vapor deposition and in that the finishing step includes a first annealing conducted in a neutral or reducing atmosphere at a temperature above 1050°C for a period of more than 30 minutes.

2. A preparation method according to the preceding claim in which the dielectric layer formation step (4) comprises, after high-density plasma vapor phase chemical deposition of the dielectric layer, a densification annealing of the support substrate.

3. A preparation method according to the preceding claim, wherein the densification annealing is carried out in a neutral atmosphere at a temperature below 1000°C and for a duration of less than 1h.

4. A preparation method according to any one of the preceding claims wherein the finishing step includes, before and / or after the first annealing, a thinning of the top layer (5).

5. A preparation process according to any one of the preceding claims, wherein the finishing step comprises a second annealing, the second annealing being carried out in a neutral or reducing atmosphere at a temperature above 1050°C for a period of less than 2 minutes.

6. A preparation method according to any one of the preceding claims, wherein the neutral or reducing atmosphere of the first annealing comprises or is made of argon.

7. A preparation method according to any one of the preceding claims wherein the step of forming the dielectric layer (4) is devoid of polishing the exposed face of the dielectric layer (4).

8. A preparation method according to any one of the preceding claims wherein the semiconductor material of the top layer (5) is silicon.

9. A preparation method according to any one of the preceding claims wherein the dielectric layer (4) is made of silicon dioxide.

10. A preparation method according to any one of the preceding claims wherein the dielectric layer (4) has a thickness greater than or equal to 400 nm.

11. A method according to any one of the preceding claims wherein the top layer transfer step comprises a step of implanting so-called "light" species into a donor substrate (1') to form a brittle plane, the assembly of the donor substrate with the support substrate (1), and the fracturing of the donor substrate at the level of the brittle plane.

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