Managing the start-up of the conversion of an analog-to-digital converter within an integrated circuit, for example a microcontroller.

Abstract

An analog-to-digital converter (ADC1) is clockable by a converter clock signal (CLKADC). A first clock signal (CLKT) has a frequency that is a multiple of the converter clock signal frequency. A counter (CNT), clockable at the rate of the first clock signal, has a counting period that is a multiple of the converter clock signal period. Processing means (MTR) are configured to control the converter based on the counting signal delivered by the counter, and have a first operating mode (ADS=1) in which they are further configured to clock the counter synchronously with the converter clock signal and to deliver, from the counting signal, a first conversion control signal (TRGS) of the converter, which is periodic, having a period that is a multiple of the converter clock signal period, and a first constant phase difference with the converter clock signal (CLKADC).Figure for the abridged version: Fig 1.

Description

Title of the invention: Management of the start of the conversion of an analog / digital converter within an integrated circuit, for example a microcontroller.

[0001] Embodiments of the invention relate to integrated circuits, in particular microcontrollers, for example those incorporating one or more analog-digital converters as well as a counter ("timer"), and more particularly the management of the start of the conversion periods of the converter(s).

[0002] Some current microcontrollers offer a so-called “fixed trigger latency” feature, i.e. a fixed duration or latency between the moment of the command or triggering of a conversion and the moment when this conversion actually begins.

[0003] Such a faculty is useful in particular in motor control or audio processing applications.

[0004] The counter (“timer”) then controls the application on the basis of a width modulated signal (“PWM: Pulse Width Modulation” in English).

[0005] The analog-to-digital conversions are controlled regularly at each period of the PWM signal and for certain applications it is important that the latency mentioned above does not change from one period to another, i.e. that there is no jitter.

[0006] This is guaranteed by construction when the converter and the counter are respectively clocked by synchronous clocks.

[0007] It is possible to obtain a fixed latency when the converter and the counter are respectively clocked by pseudo-synchronous clocks with low frequency ratios (2 or 4) but at the cost of degrading the performance of the converter.

[0008] Currently, the maximum clocking frequency of an analog / digital converter is around 75 MHz, while that of a counter can go up to several hundred MHz.

[0009] As a result, the conversion trigger signal, emitted by the counter, can occur at any time during a period of the clock signal timing the converter.

[0010] As a result, the latency between the trigger time and the actual start time of the conversion may change.

[0011] There is therefore a need to provide a fixed latency between the trigger time and the actual start time of the conversion, even for high frequency ratios between the clocking frequency of the counter and the clocking frequency of the converter, without degrading the converter's performance.

[0012] According to one aspect, there is provided an integrated circuit, for example a microcontroller, comprising -at least one first analog-digital converter clockable by a converter clock signal -a clock input for receiving a first clock signal having a frequency multiple of the frequency of the converter clock signal, - a counter, clockable at the rate of the first clock signal and having a counting period which is a multiple of the period of the converter clock signal, and - processing means configured to control said at least one first converter from the counting signal delivered by the counter.

[0013] The processing means have a first operating mode in which they are further configured to clock the counter synchronously with the converter clock signal and to deliver, from the counting signal delivered by the counter, a first converter conversion control signal, periodic having a period that is a multiple of the period of the converter clock signal and a first constant phase difference with the converter clock signal.

[0014] A fixed (constant) and predictable latency is therefore obtained between the triggering time and the actual start time of the conversion, even for high frequency ratios between the clocking frequency of the counter and the clocking frequency of the converter.

[0015] According to one embodiment, the integrated circuit further comprises a control input for receiving an external conversion control signal, for example a bit.

[0016] The processing means are configured, in their first operating mode, to in response to the external conversion control signal: -generate an edge, for example a rising edge, of the first periodic conversion control signal, each time the counter reaches a chosen counting value, for example but not necessarily the value corresponding to the value of the counting period.

[0017] The first converter is configured to periodically start conversions after a first fixed and constant duration after said edge of the first periodic conversion control signal.

[0018] This fixed duration may be equal to an integer number of periods of the converter clock signal. It may also be equal to a fraction of a period of the converter clock signal or equal to x cycles or periods of the first clock signal increased by y cycles or periods of the converter clock signal.

[0019] The processing means are further advantageously configured to deliver the converter clock signal as well as a synchronization signal indicating a first instant, for example but not necessarily the start, of each period of the converter clock signal, said first instant being identical for each period, and to, in the presence of the external conversion control signal, delay the triggering of the counter until the next first instant, for example the start of the next period of the converter clock signal.

[0020] According to one embodiment, the processing means are configured to choose said counting value from among several predefined counting values.

[0021] In the first operating mode, the counter can advantageously be reset synchronously with the converter clock signal.

[0022] According to one embodiment, the integrated circuit may comprise at least one second analog / digital converter, and possibly more than two converters, clockable by the converter clock signal and the processing means are configured, in their first configuration, to deliver a second periodic conversion control signal having a period that is a multiple of the period of the converter clock signal and a second constant phase difference with the converter clock signal.

[0023] Thus the same clock signal clocks all the converters.

[0024] This is particularly advantageous because aligning the clocks of all the converters makes it possible to reduce disturbances on the common reference, for example a common reference voltage, of the converters.

[0025] Indeed, the inventors have observed that when several converters present on the same integrated circuit operate mutually asynchronously, they disturb each other by injecting noise into the reference.

[0026] And the fact of delivering the same clock signal to all the converters makes it possible to predict the moment when each converter injects noise and consequently to control this disturbance with a view to reducing it, which was not possible in the solutions of the prior art.

[0027] Furthermore, the constant phase differences (constant latency) associated with the different converters may be identical or different for at least some of them.

[0028] The processing means may advantageously have a second operating mode in which they are configured to clock the counter asynchronously with the converter clock signal.

[0029] Indeed in certain applications it can be useful not to have constant latency.

[0030] It is then particularly advantageous for the integrated circuit to include an input selection to receive a selection signal, for example a bit, the two operating modes of the processing means then being selectable by the selection signal.

[0031] Other advantages and characteristics of the invention will appear on examining the detailed description of non-limiting modes of implementation and embodiment, and the appended drawings in which: [Fig.l] [Fig.2] [Fig.3] [Fig.4] [Fig.5] [Fig.6] [Fig.7] [Fig.8] and [Fig.9]

[0032] schematically illustrate modes of implementation and embodiment of the invention.

[0033] In [Fig.l], the reference MC designates an integrated circuit forming here for example a microcontroller.

[0034] Very schematically, and in this simplified embodiment, the microcontroller MC comprises processing means MTR, of which we will return in more detail below on an example of structure and operation, cooperating with a counter or “timer” CNT.

[0035] The microcontroller MC also includes an analog-to-digital converter ADC1 which can be clocked by a converter clock signal CLKADC.

[0036] The microcontroller MC comprises a clock input El for receiving a first clock signal CLKT having for example a frequency between 250 MHz and 400 MHz.

[0037] This first clock signal has a frequency that is a multiple of the frequency of the CLKADC converter clock signal which can for example be between 10MHz and 70MHz.

[0038] The counter CNT can be clocked at the rate of the first clock signal CLKT and has, as will be seen in more detail below, a counting period which is a multiple of the period of the converter clock signal CLKADC.

[0039] The processing means MTR, which cooperate with the counter CNT, are configured to control the ADC converter from the counting signal delivered by the counter CNT.

[0040] As will be seen in more detail below, the processing means have a first operating mode in which they are further configured to -clock the CNT counter synchronously with the converter clock signal CLKADC and to -deliver from the counting signal delivered by the counter, a first conversion control signal TRGS, on a first output terminal BS1, this signal TRGS being intended for the converter ADC1.

[0041] As will be seen in more detail below, the processing means MTR have a second operating mode in which they are configured to clock the counter CNT asynchronously with the converter clock signal CLKADC.

[0042] In this second operating mode, the processing means MTR deliver on a second output terminal BS2 a conversion control signal TRGA intended for the converter ADC1.

[0043] The processing means MTR also deliver on a third output terminal BS3 a logic signal SYNC, for example a bit, intended for the converter ADC1, so that the latter can, depending on the logic value of the bit SYNC, process either the signal TRGS or the signal TRGA.

[0044] These two operating modes are selectable by an ADS selection signal, received on a selection input E3.

[0045] The microcontroller also includes a control input E2 intended to receive an external signal SWCEN which will in fact, as will be seen in more detail below, make it possible to control, with a certain delay, the activation of the counter CNT.

[0046] But the activation of the counter will allow, as we will see in more detail below, to activate a conversion command of the ADC1 converter.

[0047] The SWCEN signal can therefore be designated as an external conversion control signal.

[0048] Finally, another input E4 is intended to receive an external signal for resetting the CNT counter, this external signal being referenced SWCRST.

[0049] Reference is now made more particularly to [Fig. 2] to illustrate an embodiment of the MTR processing means, which is provided here solely by way of non-limiting example.

[0050] The processing means MTR comprise a first stage ET1 comprising a divider counter CLKDC clocked by the first clock signal CLKT and receiving a division factor DVF.

[0051] This divider counter has an overflow bit which controls, by its logic value, the two inputs 0 and 1 of a DPX1 duplexer.

[0052] The output of the duplexer DPX1 is connected to a first input of an AND logic gate, referenced PLI, the second input of which is an inverting input.

[0053] The output of the duplexer DPX1 is also connected to the D input of a flip-flop BSC1 of type D, clocked by the first clock signal CLKT and whose output Q is connected to the inverting input of the logic gate PLI, to input 0 of the duplexer DPX1 and, after inversion, to input 1 of the duplexer DPX1.

[0054] The Q output of the BSC1 flip-flop is also connected to the 0 input of a DPX2 duplexer whose 1 input receives the first clock signal CLKT.

[0055] The output of the duplexer DPX2 forms the output terminal BS4 which delivers the converter clock signal CLKADC.

[0056] The output of the logic gate PLI is connected to a first input of an OR logic gate referenced PL2, a second input of which receives the division factor DVF in the case where this is equal to 1 due to a bypass BYP.

[0057] The control input of the DPX2 duplexer is connected to the second input of the PL2 gate.

[0058] The output of logic gate PL2 delivers a synchronization signal CADCS, the role of which will now be explained with particular reference to Figures 3 and 4.

[0059] In [Fig.3], we see that the divider counter increases until it reaches the value of the division factor DVF then decreases and so on, each time with the emission of the overflow bit OVF.

[0060] When the overflow bit OVF is transmitted, there is a pulse of the synchronization signal CADCS which here marks the start of a period of the converter clock signal CLKADC.

[0061] We see in [Fig.4], in which the division factor DVF is taken for example equal to 4, that the synchronization signal CADCS is synchronous with the first clock signal CLKT.

[0062] Furthermore, this synchronization signal CADCS indicates, for example on its falling edge, a first instant INST of each period of the converter clock signal CLKADC.

[0063] In this example, this first instant INST is the start of each period of the converter clock signal CLKADC.

[0064] Furthermore, the rising edge of the synchronization signal CADCS, preceding the falling edge indicating the instant INST, provides the indication IND that the rising edge of the converter clock signal CLKADC will occur at the next rising edge of the first clock signal CLKT.

[0065] We now refer again to [Fig.2] to continue the description of the MTR processing means.

[0066] These comprise a second stage ET2 comprising a duplexer DPX3 whose input 0 is connected to the control input E2 receiving the external control signal SWCEN and whose input 1 is connected to the output Q of a flip-flop D re- BSC2 referenced.

[0067] The D input of this flip-flop is connected to the output of the DPX3 duplexer.

[0068] This flip-flop BSC2 is clocked by the first clock signal CLKT.

[0069] The Q output of the BSC2 flip-flop is connected to the EN (“enable”) input of the CNT counter.

[0070] The DPX3 duplexer is controlled by the logic value of the output of an AND logic gate referenced PL3.

[0071] A first input of this logic gate PL3 is connected to the selection input E3 which receives the selection signal ADS.

[0072] The CADCS synchronization signal is delivered, after inversion, to the other input of the logic gate PL3.

[0073] The second stage ET2 also includes a logic AND gate with three inputs referenced PL4.

[0074] A first input of this gate PL4 receives, after inversion, the synchronization signal CADCS.

[0075] A second input of this gate PL4 receives the selection signal ADS and a third input of this gate PL4 is looped back to the output Q of a D flip-flop referenced BSC3, which is also clocked by the first clock signal CLKT.

[0076] The output of logic gate PL4 is connected to a first input of an OR logic gate referenced PL5.

[0077] The second input of this logic gate PL5 is connected to input E4 to receive the signal SWCRST.

[0078] The output of logic gate PL5 is connected to input D of flip-flop BSC3.

[0079] The Q output of the BSC3 flip-flop is also connected to the RST reset input of the CNT meter.

[0080] It should already be noted that the logical value of the ADS selection signal (bit) defines the operating mode of the MTR processing means.

[0081] Thus, for example, if the signal ADS has the logic value 1, then the processing means MTR are in their first operating mode in which the counter CNT is in particular synchronous with the converter clock signal CLKADC.

[0082] On the other hand, if the synchronization signal ADS has the logic value 0 then the processing means MTR are in their second operating mode in which they are configured to clock the counter CNT asynchronously with the converter clock signal CLKADC.

[0083] If the logic value of the ADS selection signal is equal to 1, then the value of the SYNC bit delivered by the output terminal BS3 is equal to 1, whereas if the logic value of the ADS signal is equal to 0, then the value of the SYNC bit is equal to 0.

[0084] The MTR processing means also comprise a third stage ET3 connected to the output of the CNT counter.

[0085] More precisely, this stage ET3 comprises, in this embodiment, a first register RG1, a second register RG2 and a third register RG3.

[0086] The first register RG1 contains, for example, the value of the counting period of the counter, for example the value 7 if the counter counts from 0 to 7.

[0087] The second register RG2 can contain another counting value of the counter CNT, for example the value 2, while the register RG3 can contain yet another counting value of the counter, for example the value 5.

[0088] The third stage ET3 then comprises three comparison means CMP1, CMP2 and CMP3.

[0089] The first comparison means CMP1 is configured to compare the count value of the counter CNT with the value of the first register RG1 and deliver an event pulse when the count value of the counter CNT reaches the value 7.

[0090] The second comparison means CMP2 is configured to compare the counting value of the counter CNT with the counting value contained in the register RG2, here the value 2, and deliver the event pulse each time the counter CNT delivers the counting value 2.

[0091] The third comparison means CMP3 is configured to compare the count value of the counter CNT with the count value stored in the third register RG3 and deliver the event pulse each time the count value reaches the value stored in the register RG3, in this case the value 5.

[0092] MCM control means, for example software or hardware, are intended to control a multiplexer MX whose three inputs are connected to the three outputs of the comparison means CMP1, CMP2 and CMP3 so as to select one of the three inputs to connect it to the output of the multiplexer MX.

[0093] The MTR processing means also comprise a fourth stage ET4.

[0094] This ET4 stage includes a three-input AND logic gate, referenced PL6.

[0095] A first input of logic gate PL6 receives the ADS selection signal which is also delivered to output terminal BS3 to become the SYNC bit.

[0096] A second input of logic gate PL6 receives the inverted CADCS synchronization signal.

[0097] A third input of the logic gate PL6 is looped back to the output Q of a D-type flip-flop BSC4.

[0098] The output of logic gate PL6 is connected to a first input of an OR logic gate, referenced PL7, the second input of which is connected to the output of multiplexer MX of stage ET3.

[0099] The output of logic gate PL7 is connected to the D input of flip-flop BSC4 which is clocked by the first clock signal CLKT.

[0100] The fourth stage ET4 also includes an AND logic gate referenced PL8, a first input of which is connected to the Q output of the BSC4 flip-flop and a second input of which receives the ADS selection signal.

[0101] The output of logic gate PL8 forms output terminal BS1 and delivers the conversion control signal TRGS.

[0102] The fourth stage ET4 also includes an AND logic gate, referenced PL9, a first input of which is connected to the Q output of the BSC4 flip-flop and a second input of which receives the inverted ADS selection signal.

[0103] The output of this logic gate PL9 delivers the conversion control signal TRGA.

[0104] Depending on the logic value of the SYNC bit, the analog-to-digital converter ADC1 will select either the TRGS signal or the TRGA signal.

[0105] We now refer more particularly to [Fig.5] which illustrates a timing diagram relating to the operating mode of the device of [Fig.2] when the selection signal ADS has the logic value 1 (counter synchronous with the converter clock signal CLKADC).

[0106] The upper part of the timing diagram in [Fig.5] illustrates the first clock signal CLKT.

[0107] The synchronization signal CADCS indicates, for example when a falling edge occurs, the first instant INST, in this case the start of each period of the converter clock signal CLKADC.

[0108] In this diagram, the period of the clock signal CLKADC is four times larger than the period of the first clock signal CLKT.

[0109] Furthermore, the activation signal EN of the counter CNT is delayed relative to the external control signal SWCEN, to coincide with the first instant INST.

[0110] In other words, the activation of the EN of the counter begins at the beginning of a period of the converter clock signal CLKADC.

[0111] The PER period of the counter is in this example equal to 8, the counter counting from 0 to 7.

[0112] This counting period is a multiple of the period of the converter clock signal CLKADC.

[0113] In this implementation example, it is assumed that the multiplexer MX has selected the output of the first comparison means CMP1 connected to the first register RG1 which contains the value of the counting period reduced by 1, in this case the value 7.

[0114] So, each time the counter reaches the value 7, the third stage ET3 emits the PER VT event pulse which, when it falls back to 0, causes a rising edge FM2 of the periodic conversion control signal TRGS.

[0115] In this exemplary embodiment, at the end of a period of the converter clock signal CLKADC, a falling edge FMI of the signal TRGS occurs which triggers a conversion phase CONV1 of the converter ADC1.

[0116] This is repeated regularly at each PER VT event pulse so as to cause the CONV2, CONV3 conversion periods...

[0117] We note that the duration DD between a rising edge FM2 and a falling edge of the TRGS signal is constant and fixed.

[0118] The conversion control signal TRGS of the converter is therefore a periodic signal having a period that is a multiple of the period of the converter clock signal, here a period equal to the period of the converter clock signal, and a constant phase difference with the converter clock signal.

[0119] This phase difference corresponds to the duration DD and it is also the latency.

[0120] In the example just described, the conversion is triggered directly at the end of the DD period.

[0121] Alternatively, instead of directly triggering the conversion, it would be possible to provide one or more flip-flop stages, crossed by the TRGS signal and clocked by the CLKADC signal, before triggering this conversion.

[0122] Thus by adding 2 flip-flop stages, we add to the duration DD, two periods of the CLKADC signal before triggering the conversion, which brings the fixed and constant latency to three periods of the CLKADC signal. On the other hand, the phase difference between the TRGS signal and the CLKADC signal remains constant and equal to the duration DD, i.e. here one period of the CLKADC signal. We will see in more detail below with reference to [Fig.9], that it would be possible, as a variant, to have a phase difference DD between the TRGS signal and the CLKADC signal, constant and equal to one period of the CLK clock signal (and therefore to a fraction of the period of the CLKADC signal) and a fixed latency equal to DD but possibly increased for example by several periods of the CLKADC signal.

[0123] Reference is now made more particularly to Figures 6 and 7 to illustrate timing diagrams relating respectively to the second operating mode (ADS = 0) and to the first operating mode (ADS = 1) of the MTR processing means.

[0124] As illustrated in [Fig.7] and recalled above, in the first operating mode of the processing means (ADS = 1) the counter CNT is clocked synchronously with the converter clock signal CLKADC.

[0125] Thus, the activation signal EN is delayed relative to the external control signal SWCEN so as to coincide with each period of the converter clock signal CLKADC.

[0126] Similarly, the actual reset RST of the counter is also delayed relative to the external reset request signal SWCRST, so as to also coincide with the start of a period of the converter clock signal CLKADC.

[0127] And, this is not the case in the second operating mode (ADS = 0) in which the counter is clocked asynchronously with respect to the converter clock signal CLKADC.

[0128] We see in fact that the effective activation signal EN of the counter follows the signal SWCEN (after a period of the signal CLKT) without it being synchronized with the converter clock signal CLKADC.

[0129] The same applies to the effective reset signal RST which immediately follows the external signal SWCRST, without also being synchronized with the converter clock signal CLKADC.

[0130] We now refer more particularly to [Fig.8] which illustrates an MC microcontroller comprising several analog-to-digital converters (here only two converters ADC1 and ADC2 have been shown for simplification purposes).

[0131] The converter clock signal CLKADC clocks the two converters ADC1 and ADC2 which therefore receive the same clock signal.

[0132] Furthermore, the multiplexer MX and the fourth stage ET4 are duplicated.

[0133] More precisely, a first multiplexer MX is connected to the comparison means CMP1-CMP3, followed by a stage ET4 which will deliver the signals TRGS1, TRGA1, SYNC1 to the first converter DC1.

[0134] And, a second multiplexer MX is also connected to the outputs of the comparison means CMP1-CMP3 followed by another stage ET4 which will deliver the signals TRGS2, TRGA2 and SYNC2 to the second converter ADC2.

[0135] In general, the SYNC1 and SYNC2 signals are identical because the two converters will operate either in the first operating mode or in the second operating mode.

[0136] And, the control means MCM will control the multiplexers MX in a first way to deliver the signals TRGA1 and TRGS1 while the control means will control the second multiplexer MX in a second way to deliver the signals TRGS2 and TRGA2.

[0137] Thus, for example, the first multiplexer MX could be controlled so as to select the first input connected to the first register RG1 while the second multiplexer could for example be controlled so as to select another input connected to one or other of the registers RG2 and RG3.

[0138] It would also be possible to duplicate the CNT counter as well as the ET3 stages and ET4.

[0139] The invention is not limited to the embodiments and implementations which have just been described but embraces all variants thereof.

[0140] Thus, as illustrated in the timing diagram of [Fig.9], in which the signals similar to those of [Fig.5] bear the same references, the synchronization signal CADCS is advanced by one cycle of the first clock signal CLKT relative to the timing diagram of [Fig.5].

[0141] The synchronization signal CADCS indicates, for example when a falling edge occurs, the first instant INST which is now located within each period of the converter clock signal CLKADC, and no longer as in [Fig.5] at the start of each period of the converter clock signal CLKADC.

[0142] In this diagram of [Fig.9], the period of the clock signal CLKADC is four times greater than the period of the first clock signal CLKT.

[0143] Furthermore, the activation signal EN of the counter CNT is again delayed relative to the external control signal SWCEN, to coincide with the first instant INST.

[0144] The PER period of the counter is in this example still equal to 8, the counter counting from 0 to 7.

[0145] In this example of implementation, it is also assumed that the multiplexer MX has selected the output of the first comparison means CMP1 connected to the first register RG1 which contains the value of the counting period reduced by 1, in this case the value 7.

[0146] Therefore, each time the counter reaches the value 7, the third stage ET3 emits the event pulse PER VT which, when it falls back to 0, causes a rising edge FM2 of the periodic conversion control signal TRGS.

[0147] In this exemplary embodiment, the signal TRGS is captured in a flip-flop type latch generating a periodic signal TRGSR having at the end of a cycle of the first clock signal CLKT a rising edge FM2R.

[0148] This results in the generation of a pulse signal TRGSP whose falling edge FM2P will here directly trigger a conversion phase CONV1.

[0149] This is repeated regularly at each PER VT event pulse so as to cause the CONV2, CONV3 conversion periods...

[0150] The phase difference DD, fixed and constant, between the signal TRGS and the signal CLKADC is therefore here equal to a period of the clock signal CLKT and therefore to a fraction of the converter clock signal CLKADC.

[0151] Latency is also equal to DD here.

[0152] Again, as a variant, instead of directly triggering the conversion, it would be possible to provide one or more stages of flip-flops, crossed by the TRGS signal and clocked by the CLKADC signal, before triggering this conversion.

[0153] Thus by adding 2 flip-flop stages, we add to the duration DD, two periods of the CLKADC signal before triggering the conversion, which brings the fixed and constant latency to one period of the CLKT clock signal increased by two periods of the CLKADC signal.

[0154] On the other hand, the phase difference between the TRGS signal and the CLKADC signal remains constant and equal to the duration DD, i.e. here one period of the CLKT signal.

Claims

Claims

1. Integrated circuit, comprising - at least one first analog-to-digital converter (ADC1) clockable by a converter clock signal (CLKADC) - a clock input for receiving a first clock signal (CLKT) having a frequency multiple of the frequency of the converter clock signal, - a counter (CNT), clockable at the rate of the first clock signal and having a counting period multiple of the period of the converter clock signal, and processing means (MTR) configured to control said at least one first converter from the counting signal delivered by the counter, in which the processing means (MTR) have a first operating mode (ADS=1) in which they are further configured to clock the counter synchronously with the converter clock signal and to deliver from the counting signal, a first conversion control signal (TRGS) of the converter,periodic having a period multiple of the period of the converter clock signal and a first constant phase difference with the converter clock signal (CLKADC).,

2. Integrated circuit according to claim 1, wherein the integrated circuit further comprises a control input for receiving an external conversion control signal (SWCEN), the processing means being configured in their first operating mode, to in response to the external conversion control signal, generate an edge (FM2) of the first periodic conversion control signal (TRGS) each time the counter reaches a chosen counting value, and the first converter (ADC1) is configured to periodically start conversions after a first fixed and constant duration (DD) after said edge of the first periodic conversion control signal (TRGS).

3. Integrated circuit according to claim 2, in which the processing means (MTR) are further configured to deliver the converter clock signal as well as a synchronization signal (CADCS) indicating a first instant (INST) of each period of the converter clock signal, said first instant being identical for each period, and to, in the presence of the external conversion control signal, delay the triggering of the counter until the next first instant.

4. Integrated circuit according to claim 2 or 3, wherein the processing means (MTR) are configured to choose said counting value from among several predefined counting values.

5. Integrated circuit according to one of claims 2 to 4, in which the counter (CNT) is resettable synchronously with the converter clock signal (CLKADC).

6. Integrated circuit according to one of the preceding claims, comprising at least one second analog / digital converter (ADC2) clockable by the converter clock signal and the processing means (MTR) are configured, in their first configuration, to deliver a second periodic conversion control signal having a period multiple of the period of the converter clock signal and a second constant phase difference with the converter clock signal.

7. Integrated circuit according to one of the preceding claims, in which the processing means (MTR) have a second operating mode (ADS=0) in which they are configured to clock the counter asynchronously with the converter clock signal.

8. Integrated circuit according to claim 7, comprising a selection input for receiving a selection signal (ADS), the two operating modes of the processing means being selectable by the selection signal (ADS).

9. Integrated circuit according to one of the preceding claims, forming a microcontroller (MC).

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