Pulse counter

Abstract

Pulse Counter This description relates to a pulse counter (200) comprising an asynchronous counter (201) and a circuit (205) configured to trigger a read operation of the value of said asynchronous counter, said circuit (205) being synchronized by a clock signal. Figure for the abbreviation: Fig. 2

Description

Title of the invention: Pulse counter technical field

[0001] This description relates generally to electronic circuits and devices used in the field of audio file processing. More specifically, this description relates to a circuit for counting pulses in a signal obtained from an audio file. Previous technique

[0002] Audio file processing, and in particular the processing of audio files representing the human voice, is an important issue in many scientific fields.

[0003] It would be desirable to be able to improve, at least in part, certain aspects of the circuits and devices used in the field of audio file processing, and, in particular, certain aspects of the circuits enabling the counting of pulses of a signal obtained from an audio file. Summary of the invention

[0004] There is a need for more efficient circuits and devices used in the field of audio file processing.

[0005] There is a need for circuits and devices used in the field of audio file processing and operating at low frequency.

[0006] There is a need for more efficient circuits to count pulses of a signal obtained from an audio file.

[0007] There is a need for circuits enabling the counting of pulses of a signal obtained from an audio file and operating at low frequency.

[0008] An embodiment overcomes all or part of the drawbacks of known circuits and devices used in the field of audio file processing.

[0009] An embodiment overcomes all or part of the drawbacks of known circuits for counting pulses of a signal obtained from an audio file.

[0010] One embodiment provides a pulse counter comprising an asynchronous counter and a circuit configured to trigger an operation to read the value of said asynchronous counter, said circuit being synchronized by a clock signal.

[0011] According to one embodiment, the counter further includes a flip-flop adapted to receive said value of said asynchronous counter during a reading phase.

[0012] According to one embodiment, a reading phase is triggered by an edge of a first synchronization signal.

[0013] According to one embodiment, a reading phase is stopped by an edge of a second synchronization signal.

[0014] According to one embodiment, said edge of the second synchronization signal also triggers the reset of said value of said asynchronous counter.

[0015] Another embodiment provides a circuit adapted for word recognition from an audio file comprising a pulse counter described above.

[0016] According to one embodiment, the circuit has a clock frequency between 30 and 40 kHz.

[0017] According to one embodiment, the clock frequency is equal to 32.728 kHz.

[0018] According to one embodiment, the circuit further comprises a first adapted circuit to implement a function for extracting an acoustic characteristic.

[0019] According to one embodiment, the circuit further comprises a second circuit adapted to integrate a signal supplied by the first circuit.

[0020] According to one embodiment, the circuit further comprises a third circuit configured to implement digital processing of a signal supplied by said pulse counter.

[0021] Another embodiment provides a device adapted to process an audio file comprising a circuit described above.

[0022] According to one embodiment, the device further comprises a microphone.

[0023] According to one embodiment, the device further comprises a network of neurons.

[0024] According to one embodiment, the device is adapted to detect the human voice. Brief description of the drawings

[0025] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0026] [Fig.1] represents, very schematically and in block form, an embodiment of a device for processing an audio file;

[0027] [Fig. 2] represents an electrical diagram of an embodiment of a pulse counter of the embodiment of [Fig. 1]; and

[0028] [Fig.3] represents timing diagrams illustrating the operation of the embodiment of [Fig.2]. Description of the implementation methods

[0029] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0030] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0031] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0032] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0033] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0034] Fig. 1 represents, very schematically and in block form, an embodiment of a device 100 for processing an audio file.

[0035] According to one embodiment, the device 100 is adapted to acquire an audio file and then process it. For this purpose, and according to one example, the device 100 comprises: - a microphone 101 (Microphone); - a circuit 102 (aMFCC) adapted for the recognition of certain audio data; and - a neural network 103 (DNN).

[0036] According to a preferred embodiment, the device 100 is adapted to acquire and process an audio file containing a human voice. More particularly, the device 100 is adapted to detect the human voice.

[0037] According to one example, the microphone 101 is an electronic device adapted to acquire an audio file. The microphone 101 is configured to provide a raw audio file.

[0038] According to one example, the circuit 102 is adapted to recognize certain audio data from the raw audio file provided by the microphone 101. According to the preferred embodiment, the circuit 102 is adapted to recognize words.

[0039] According to one example, circuit 102 comprises: - a 1021 (AFE) circuit adapted to implement an extraction function of an acoustic characteristic; - a 1022 circuit (IAF) adapted to filter an acoustic characteristic extracted by the 1021 circuit; - a 1023 pulse counter (Ripple Counter) according to one embodiment; and - a 1024 circuit (Digital processing) configured to implement digital processing of a signal supplied by said pulse counter 1023.

[0040] According to one example, the 1021 (AFE) circuit is adapted to extract a characteristic acoustics from the raw audio file supplied by the 101 microphone. More specifically, the 1021 circuit is adapted to extract certain properties from the raw audio file it receives from the 101 microphone.

[0041] According to one example, the circuit 1022 (IAF) is adapted to filter an acoustic characteristic extracted by the circuit 1021, and more particularly to integrate a signal provided by the circuit 1021. The circuit 1022 provides a signal comprising pulses to the counter 1023. According to one example, the circuit 1022 is an analog-to-digital converter driven by a software event.

[0042] According to one embodiment, the pulse counter 1023 is an asynchronous counter operating in the analog domain of the circuit 102, and which is adapted to count the number of pulses of the signal supplied by the circuit 1022 during a given duration. This given duration generally corresponds to a calculation window defined by the duration of the raw audio file acquired by the microphone 101.

[0043] According to one embodiment, the circuits 1021 and 1022 and the counter 1023 are all part of the analog domain of the circuit 102, and are all adapted to operate at low frequency, i.e. at a frequency for example between 30 and 40 kHz, for example on the order of 32.726 kHz.

[0044] According to one example, the circuit 1024 is configured to implement digital processing of a signal supplied by said pulse counter 1023. The circuit 1024 is part of a digital domain of the circuit 102.

[0045] According to one example, neural network 103 is adapted to receive data from circuit 1024 and to process it. According to one example, neural network 103 is a deep neural network.

[0046] [Fig.2] is an electrical diagram of an embodiment of a pulse counter 200 of the type of the pulse counter 1023 described in relation to [Fig.1].

[0047] The pulse counter 200 is a pulse counter adapted to operate at low frequency. For this purpose, the pulse counter is adapted to count pulses asynchronously, and is adapted to provide the result of its count synchronously, that is to say, synchronized with a clock signal.

[0048] According to one embodiment, the pulse counter 200 includes an asynchronous counter circuit 201 (Count) comprising an input terminal, an output terminal providing an AC signal, and an inverting reset terminal receiving an AC_NRST reset signal.

[0049] The pulse counter 200 further includes, for example, a flip-flop 202 (Sync) for reading the value of the asynchronous counter 201. The flip-flop 202 includes an input terminal receiving the AC signal from the asynchronous counter 201, and an output terminal providing a DI_CA output signal from the counter 200 pulses. The DI_CA signal represents the pulse counter value during a read phase. The flip-flop 202 also includes an enable terminal and an inverting reset terminal receiving a DO_NRSTA reset signal.

[0050] The pulse counter 200 further includes an inverter circuit 203 receiving as input a synchronization signal DO_CA_SYNC2, and whose output is connected, preferably connected, to the reset terminal of the asynchronous counter 201. Thus, a rising edge of the synchronization signal DO_CA_SYNC2 allows the value of the asynchronous counter 201 to be reset to an initial value, for example to zero.

[0051] The pulse counter 200 further comprises an AND logic gate 204 having a first input terminal receiving a signal to be analyzed, and a second inverting input terminal receiving a CA_SCREEN signal. An output terminal of the gate 204 is connected, preferably connected, to the input terminal of the asynchronous counter 201.

[0052] According to one embodiment, the pulse counter 200 further comprises a circuit 205 (Power Screen) configured to trigger a pulse counter read operation. The circuit 205 comprises: - a power supply terminal receiving a supply voltage VDDD; - an inverting reset terminal; - an input terminal receiving a DO_CA_SYNC1 synchronization signal; and - an output terminal providing the CA_SCREEN signal.

[0053] The pulse counter 200 further includes an inverter circuit 206 receiving the DO_CA_SYNC1 synchronization signal as input, and whose output is connected, preferably connected, to the input terminal of the flip-flop 202.

[0054] The pulse counter 200 further includes an inverter circuit 207 receiving the DO_CA_SYNC2 synchronization signal as input, and whose output is connected, preferably connected to the inverting reset terminal of the circuit 205.

[0055] The operation of the pulse counter 200 is as follows. The asynchronous counter 201 counts the pulses present on the signal as long as the CA_SCREEN signal is in a low state. A read phase only occurs when the CA_SCREEN signal is in a high state. The implementation of a read phase of the value of the asynchronous counter 201 is described in relation to [Fig. 3].

[0056] The [Fig.3] includes four chronograms 301, 302, 303 and 304 illustrating the operation of the embodiment of the [Fig.2].

[0057] More specifically, [Fig.3] comprises: - the chronogram 301 representing the temporal evolution of an MCLK clock signal; - the chronogram 302 representing the temporal evolution of the synchro- signal nisation DO_CA_SYNC1 ; - the timing diagram 303 representing the temporal evolution of the DO_CA_SYNC2 synchronization signal; and - the chronogram 304 representing the temporal evolution of the CA_SCREEN signal.

[0058] The MCLK clock signal synchronizes the reading phases of the value of the asynchronous counter 201 with the DO_CA_SYNC1 and DO_CA_SYNC2 synchronization signals. For example, the clock signal is at a low frequency, i.e., at a frequency between 30 and 40 kHz, for example, on the order of 32.726 kHz.

[0059] As previously stated, a reading phase is implemented when the CA_SCREEN signal is in a high state.

[0060] A rising edge of the CA_SCREEN signal is triggered by a rising edge of the DO_CA_SYNC1 synchronization signal, which is itself triggered at a rising edge of the MCLK clock signal.

[0061] Furthermore, a rising edge of the DO_CA_SYNC1 synchronization signal turns off flip-flop 202, thus fixing the data it stores. This data corresponds to the value of the asynchronous counter 201. A falling edge of the DO_CA_SYNC1 synchronization signal is triggered by a falling edge of the MCLK clock signal. The falling edge of the synchronization signal triggers the reading of the value of the asynchronous counter 201.

[0062] A falling edge of the CA_SCREEN signal is triggered by a rising edge of the DO_CA_SYNC2 synchronization signal. This rising edge of the DO_CA_SYNC2 synchronization signal also resets the asynchronous counter 201.

[0063] An advantage of this embodiment of a pulse counter is that it can be implemented by a circuit operating at a low frequency, even if the frequency of the received pulses is higher than this low frequency. In particular, this pulse counter can be integrated into a part of a low-power, always-on electronic device, commonly called the ALWAYS ON section.

[0064] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0065] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Claims

1. Pulse counter (1021; 200) comprising an asynchronous counter (201) and a circuit (205) configured to trigger an operation of reading the value of said asynchronous counter, said circuit (205) being synchronized by a clock signal.

2. Counter according to claim 1, further comprising a flip-flop (202) adapted to receive said value of said asynchronous counter (201) during a reading phase.

3. Counter according to claim 1 or 2, in which a reading phase is triggered by an edge of a first synchronization signal (DO_CA_SYNC1).

4. Counter according to any one of claims 1 to 3, in which a reading phase is stopped by an edge of a second synchronization signal (DO_CA_SYNC2).

5. Counter according to claim 4, wherein said edge of the second synchronization signal (DO_CA_SYNC2) further triggers the resetting of said value of said asynchronous counter (201).

6. Circuit (102) adapted for recognizing words from an audio file comprising a pulse counter (1023; 200) according to any one of claims 1 to 5.

7. A circuit according to claim 6, having a clock frequency of between 30 and 40 kHz.

8. The circuit of claim 7, wherein the clock frequency is 32.728 kHz.

9. Circuit according to any one of claims 6 to 8, further comprising a first circuit (1021) adapted to implement a function of extracting an acoustic characteristic.

10. A circuit according to any one of claims 6 to 9, further comprising a second circuit (1022) adapted to integrate a signal provided by the first circuit (1021).

11. Circuit according to any one of claims 6 to 10, further comprising a third circuit (1024) configured to implement digital processing of a signal provided by said pulse counter (1021; 200).

12. Device (100) adapted to process an audio file comprising a circuit (102) according to any one of claims 6 to 11.

13. The device of claim 12, further comprising a mi-

14. A microphone (101). A device according to claim 12 or 13, further comprising a neural network (103).

15. Device according to any one of claims 12 to 14, adapted to detect the human voice.

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