Gate All-Around Semiconductor Structure and Its Method of Preparation - Gate All-Around Semiconductor Structure and Its Method of Preparation

Abstract

The invention relates to a semiconductor structure (SC) comprising a support (1a) and a dielectric layer (1b) directly disposed on the support (1a). At least one pFET structure resides directly on the dielectric layer (1b), each pFET structure comprising a first stack of compression-stressed germanium silicon channel nanosheets and a pFET gate structure encapsulating each channel nanosheet of the first stack. At least one nFET structure resides directly on the dielectric layer, each nFET structure comprising a second vertical stack of silicon channel nanosheets and an nFET gate structure encapsulating each channel nanosheet of the second stack. Figure 2Q

Description

Title of the invention: SEMICONDUCTOR STRUCTURE with enveloping gate and method for its preparation FIELD OF THE INVENTION

[0001] The present invention relates to a gate-all-around semiconductor structure and a method for preparing such a structure. CONTEXT OF THE INVENTION

[0002] Wrap-around gate semiconductor structures offer many improvements over planar and non-planar transistors (e.g., FinFET). In particular, improved gate-to-channel control allows for better short-channel immunity and lower leakage currents.

[0003] Figures 1A-1K show the main steps in preparing a prior art Gate-Ail-Around semiconductor structure. To simplify the representation, only one structure is shown in the figures but, in general, a set of such structures is prepared collectively during the execution of these steps.

[0004] As shown in [Fig.lA], a pseudomorphic superlattice SL composed of silicon layers SL1 and compressively strained silicon-germanium layers SL2 is initially grown on a silicon substrate 1, for example a p-type (100) bulk silicon substrate. The silicon-germanium layers SL2 may comprise about 30% germanium and have a thickness of about 8 nm to 20 nm. The silicon layers SL1 may have a thickness of about 4 nm to 10 nm.

[0005] Next, the SL superlattice is protected by a stack of oxide and nitride formed at low temperature before using conventional photolithography and etching techniques to define a fin 2 in the pseudomorphic SL superlattice. The etching can, for example, be carried out by reactive ion etching. The intermediate structure after the etching step is shown in [Fig.lB].

[0006] In the next step of forming the shallow isolation trenches, silicon dioxide is deposited on the intermediate structure and a chemical-mechanical planarization (CMP) step is performed to make the surface flat. It is possible to anneal the shallow isolation trenches at low temperature before applying the CMP. The silicon dioxide is then etched to expose the fin 2 and preserve the isolation characteristics of the shallow trench 3 on each side of the fin. This is shown in [Fig.lC].

[0007] In a next step, a dummy gate 4 is formed above the fin 2, by depositing a stack composed of a relatively thin oxide protective film and a relatively thick layer of amorphous or polycrystalline silicon. As shown in [Fig. 1D], the dummy gate 4 is defined in the stack by photolithography and etching. Then, spacers (“spacers” in the English terminology of the field) made of silicon nitride 5 are formed by deposition and etching on each side of the dummy gate 4.

[0008] In the next step, a double source / drain 6 is formed by epitaxy on each side of the fin, against the spacer 5.

[0009] Next, a first interlayer dielectric 7 is formed on the intermediate structure of [Fig.lF], which is planarized by CMP to expose the upper part of the dummy gate 4, as shown in [Fig.lG], which can then be removed, for example by wet etching. In the resulting intermediate structure, shown in [Fig.lH], the pseudomorphic superlattice SL is partially exposed by the removal of the dummy gate 4. Next, the suspended channel nanosheets 8 of the semiconductor structure, extending between the source / drain regions 6, are defined by selectively removing the silicon-germanium layers SL2.A gate structure 9, composed of a multi-layer material with a high dielectric constant (i.e. having a dielectric constant higher than that of silicon dioxide) and metal, is then deposited, for example by an atomic layer deposition technique, to completely encapsulate each channel nanosheet 8, and form an enveloping gate structure, as illustrated in [Fig.U].

[0010] After a CMP planarization step to remove excess metal deposition ([Fig.lK]), further intercalary dielectric layers 7 may be formed on the intermediate structure ([Fig. IL]). Gate, source and drain vias (not shown) may be formed in the intercalary dielectric layers 7 to contact the corresponding electrodes respectively.

[0011] As discussed in Sun, X. et al. "A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-Around Transistors and Its Mechanism Investigation" Nanomaterials 2023, 13, 504, the principal orientation of the conduction surface in channel nanosheets is generally (100), and thus there is an unbalanced mobility between holes and electrons in these channels. To achieve current matching between a pFET structure and an nFET structure of a device, compressive stress can be introduced into the channel nanosheets of the pFET structure to enhance the hole mobility.

[0012] In document US2021 / 0151601, a constrained material is formed along a side surface of the grid. The constrained material is configured to create a de- formation in the nanosheets of the channel.

[0013] In US2023031490, a substrate is prepared and comprises a relaxed silicon germanium surface region and a silicon surface region. A pFET structure is fabricated from a strained silicon germanium material formed on the surface silicon region. An nFET structure is formed from a strained silicon material formed on the relaxed silicon germanium surface region. SUBJECT OF THE INVENTION

[0014] An object of the invention is to provide a semiconductor structure which at least partially compensates for the current imbalance between pFET and nFET structures with wrap-around gates.

[0015] Another object of the invention is to provide a method for preparing such a semiconductor structure. Summary of the invention

[0016] For this purpose, the invention relates to a semiconductor structure comprising: a. a support; b. a dielectric layer directly placed on the support; c. at least one pFET structure residing directly on the dielectric layer, each pFET structure comprising: i. a first stack of silicon-germanium channel nanosheets subjected to compressive stress; ii. a pFET gate structure encapsulating each channel nanosheet of the first stack; and d. at least one nFET structure residing directly on the dielectric layer, each nFET structure comprising: i. a second vertical stack of silicon channel nanosheets; ii. an nFET gate structure encapsulating each channel nanosheet of the second stack.

[0017] According to other non-limiting characteristics of the invention, used alone or in any technically possible combination: - The silicon of the channel nanosheets of the second vertical stack is subjected to tensile stress; - The semiconductor structure further comprises: • source and drain pFET regions formed on the support and respectively associated with the channel nanosheets of the first stack and; • source and drain nFET regions formed on the support and respectively associated with the channel nanosheets of the second stack; - the semiconductor structure further comprises a boundary trench between the pFET structures and the nFET structures; - the channel nanosheets of the first stack and the second stack have a thickness between 4 nm and 20 nm.

[0018] According to another aspect, the invention relates to a method of preparing a semiconductor structure, the method comprising the following steps: a. providing a substrate comprising a support, a dielectric layer directly disposed on the support, and an upper silicon film directly disposed on the dielectric layer; b. transforming, in a pFET region of the substrate, a portion of the upper silicon film into a compressively strained silicon germanium film, a remaining portion of the upper silicon film forming an nFET region of the substrate; c. selectively growing, on the pFET region, a first pseudomorphic superlattice composed of silicon layers and silicon-germanium layers stressed in compression; d. define at least one pFET structure residing directly on the dielectric layer by: i. selectively removing silicon layers from the first pseudomorphic superlattice to define a first stack of channel nanosheets consisting of compressively strained silicon-germanium layers; ii. forming by deposition a pFET gate structure encapsulating each channel nanosheet of the first stack.

[0019] According to other non-limiting characteristics of this aspect of the invention, used alone or in any technically possible combination: - the method further comprises: • selectively growing on the nFET region a second pseudomorphic superlattice composed of silicon layers and silicon-germanium layers; • define at least one nFET structure residing directly on the dielectric layer by: • selectively removing the silicon-germanium layers from the second pseudomorphic superlattice to define a second stack of channel nanosheets consisting of layers of silicon; • forming by deposition an nFET gate structure encapsulating each channel nanosheet of the second stack; - the upper silicon film of the substrate is subjected to a tensile stress - the method further comprises, before the step of transforming a part of the upper silicon film, a step of relaxing, at least in part, the tensile stress of the upper silicon film in the pFET region; - stress relaxation in tension includes amorphization, in the pFET region, of a portion of the upper silicon film by ion implantation and heat treatment of the substrate to recrystallize the amorphous portion; - the transformation of a part of the upper silicon film includes: • selectively forming a germanium-rich layer on the upper silicon film of the pFET region; and • oxidizing at least a portion of the germanium-rich layer to diffuse germanium species into the upper silicon film of the pFET region, thereby forming the compressively strained silicon germanium layer; - in which the germanium-rich layer is a silicon-germanium layer having a germanium concentration of between 10 and 20% and a thickness of between 5 and 10 nm; - the silicon layers of the first pseudomorphic superlattice each have a thickness of between 4 nm and 20 nm, and the silicon-germanium layers of the first pseudomorphic superlattice each have a thickness of between 4 nm and 20 nm; - the silicon-germanium layers of the second pseudomorphic superlattice each have a thickness of between 4 nm and 20 nm, and the silicon layers of the second pseudomorphic superlattice each have a thickness of between 4 nm and 20 nm. FIGURES

[0020] Numerous other features and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0021] [Fig.lA][Fig.lB][Fig.lC][Fig.lD][Fig.lF][Fig.lG][Fig.lH][Fig.lI][Fig.U][Fig.lK]

[0022] Figures 1A to 1K show a method for preparing a semi-conductor structure with an enveloping gate according to the state of the art;

[0023] [Fig. 2 A] [Fig.2B] [Fig.2C] [Fig.2D] [Fig.2E] [Fig.2F] [Fig.2G] [Fig.2H] [Fig. 21] [Fig.2J] [ Fig.2K] [Fig.2L] [Fig.2M] [Fig.2N] [Fig.2O] [Fig.2P] [Fig.2Q]

[0024] Figures 2A to 2Q represent a method of preparing a semiconductor structure with an enveloping gate according to the invention;

[0025] [Fig.3A][Fig.3B][Fig.3C][Fig.3D]

[0026] Figures 3A, 3B, 2C and 3D illustrate a particular application of a method according to the invention for manufacturing FET structures known as “forksheet” type.

[0027] DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS OF THE INVENTION

[0028] The illustrations presented herein are not actual views of any particular semiconductor structure, device, system, or process, but are merely idealized representations used to describe embodiments of the invention.

[0029] Methods that can be used to fabricate a semiconductor structure are described below with reference to Figures 2A-2Q.

[0030] In a first step of a method according to the invention, shown in [Fig.2A], a substrate 1 is provided. The substrate 1 comprises a support 1a, a dielectric layer 1b directly arranged on the support 1a, and an upper silicon film 1c directly arranged on the dielectric layer 1b. The substrate 1 may be in the form of a circular wafer with a diameter of 100, 150, 200, 300 or even 450 mm.

[0031] The support 1a typically has a thickness of a few hundred micrometers, sufficient to be self-supporting and to receive the other layers forming the substrate 1. For reasons of availability and cost, the support 1a is preferably made of monocrystalline silicon. It may comprise a surface layer for trapping charges, such as a surface layer of polysilicon, arranged under the dielectric layer 1b, and in contact with this layer 1b.

[0032] The dielectric layer 1b may have a thickness of between 10 nm and 1 micron. A thin dielectric layer 1b, less than 20 nm, may be preferred in certain embodiments to allow better thermal diffusion to the underlying support. Furthermore, if the dielectric layer 1b is intended to also replace shallow isolation trenches, as will be presented in more detail below, a greater thickness, for example 90 nm or more, may be chosen. The dielectric layer 1b may be formed of any dielectric material but, preferably, it consists of a layer of silicon dioxide.

[0033] The upper silicon film 1c is made of monocrystalline silicon. It may have a thickness of between 4 and 20 nm. In certain embodiments, the upper silicon film is not constrained. In other cases, the upper silicon film has a tensile stress, the stress typically being between 0.5 GPa and 2 GPa. Methods for preparing such a constrained upper silicon layer are well known, and for example described in US6953736B2.

[0034] A second step of a method according to the invention consists in treating the upper silicon film 1c to define two distinct regions of the substrate 1 which extend over the surface of this film. A first region, called a "pFET region", is configured to receive at least one pFET structure and a second region, called an "nFET region", is configured to receive at least one nFET structure. As known to the person skilled in the art, a pFET structure is a semiconductor device, such as a transistor, comprising a low p-doped channel arranged between high p-doped drain and source regions. The current carriers are holes in a pFET structure. Similarly, an nFET structure is a semiconductor device, such as a transistor, comprising a low n-doped channel arranged between high n-doped drain and source regions. The current carriers are electrons in an nFET structure.

[0035] The pFET and nFET regions do not necessarily have to be continuous regions. Each of these regions may be formed from unconnected sub-regions arranged on the surface of the upper silicon film to pave it.

[0036] The pFET regions of the substrate 1 are defined by transforming a portion of the upper silicon film 1e into a silicon-germanium film 1e' subjected to compressive stress. The remaining portion of the upper silicon film 1e forms an nFET region of the substrate 1. The transformation can be carried out according to the steps illustrated in FIGS. 2B to 2F.

[0037] In [Fig.2B], the upper silicon film 1e of the substrate 1 is entirely covered with a protective layer 1d. The protective layer may comprise a single layer or several layers of protective material. Typically, the protective layer 1d may comprise a relatively thin silicon oxide film in contact with the upper silicon film 1e, covered with a relatively thick silicon nitride film. The silicon oxide film may have a thickness of between 2 and 5 nm and the silicon nitride film may have a thickness of between 20 nm and 100 nm.

[0038] In a next step, shown in [Fig.2C], the protective layer Id is opened by conventional photolithography techniques, using a photoresist mask layer Id disposed on the protective layer Id, and etching techniques to selectively expose the upper silicon film Id. This opening (which may be discontinuous and formed of unconnected sub-regions, as shown above) corresponds to the pFET region of the substrate. The unexposed portion of the top silicon film forms the nFET region of substrate 1.

[0039] If the upper silicon film 1e is subjected to tensile stress, one embodiment may include, during formation of the aperture, selectively releasing the tensile stress from the upper silicon film 1e into the pFET region of the substrate, as shown in [Fig. 2D]. This may be achieved by preserving the silicon oxide film over the pFET region while selectively etching silicon nitride from the protective layer film 1d during formation of the aperture. The nFET region is protected by the photoresist mask layer 1e, such that this region is not affected by the stress-releasing operations.Atomic species such as argon, germanium, or silicon can then be selectively implanted into the lower portion of the upper silicon film 1e (i.e., the portion of the film in contact with the dielectric layer 1b) of the pFET region, through the silicon oxide film. This implantation can amorphize the lower portion of the upper silicon film 1e in the pFET region and release the tensile stress. A low-temperature annealing applied to the substrate 1 can then be applied to recrystallize the amorphous portion of the upper silicon film 1e after removing the photoresist mask layer 1e. Then, the silicon oxide film on the pFET region is removed to obtain the structure shown in [Fig.2C].

[0040] Whether or not these stress-releasing steps have been performed, the substrate 1 has an upper silicon film 1e of single-crystal silicon, the portion of the upper silicon film 1e corresponding to the pFET region being unstressed and exposed, while the portion of the upper silicon film 1e corresponding to the nFET region is disposed under the protective layer 1d. This portion may be subjected to a tensile stress if the originally provided substrate 1 included such an upper silicon layer 1e subjected to such stress.

[0041] Next, as shown in Figures 2E and 2F, a germanium If-rich layer, such as a silicon-germanium If film, is epitaxially and selectively grown on the exposed pFET region of the upper silicon film 1e. The epitaxially grown silicon-germanium If film may typically comprise between 10% and 20% germanium and may have a thickness of between 4 nm and 20 nm. The substrate 1 is then exposed to an oxygen-rich atmosphere and the epitaxially grown silicon-germanium If film is oxidized. During this oxidation step, oxygen species from the oxygen-rich atmosphere bond with the silicon of the silicon-germanium film to form a surface layer of silicon oxide 1g. The germanium species are not oxidized and are injected into the underlying upper silicon film 1e, as this phenomenon is explained in US9219150B1, to form a silicon film germanium stressed in compression.

[0042] After this oxidation step, the portion of the upper silicon film 1e in the pFET region is transformed into a silicon-germanium film 1e' subjected to compressive stress. The portion of the upper silicon film 1e in the nFET region is not affected by this step and its crystalline silicon nature is preserved. After removal of the surface silicon oxide layer 1g, the structure shown in [Fig.2G] is obtained. This structure forms a platform for providing at least one pFET structure on the pFET region of the substrate (i.e., on the silicon-germanium layer 1e' deformed by compression), the pFET structure benefiting from the exposure of the deformed germanium layer 1e'. Furthermore, at least one nFET structure is formed on the nFET region of the substrate (i.e., on the upper silicon film 1e, whether or not it is stressed).

[0043] More specifically, in a next step shown in [Fig.2H], a first pseudomorphic superlattice SL' composed of silicon layers SL1' and compressively strained silicon-germanium layers SL2' is formed on the exposed compressively strained silicon-germanium film SL'. The silicon-germanium layers SL2' of the first pseudomorphic superlattice SL' may comprise about 30% germanium and have a thickness of between 4 nm and 20 nm, while the silicon layers SL1' of this superlattice SL' may have a thickness of between 4 nm and 20 nm. The layers of the first pseudomorphic superlattice SL' may be formed without doping or with slight p-doping.

[0044] Another protective layer ld' is then disposed on the substrate 1, as shown in [Fig. 21]. This additional protective layer ld' may also comprise a thin CVD or ALD silicon oxide layer covered with a silicon nitride layer. The protective layers ld,ld' may then be selectively removed by photolithography and wet or dry etching to expose the upper silicon film le in the nFET region of the substrate 1. Advantageously, the protective layers ld,ld' are not entirely removed from the nFET region, and a residual portion ld" is preserved to encapsulate the side of the first pseudomorphic superlattice SL', as can be seen in [Fig. 2J]. Then, a second pseudomorphic superlattice SL composed of silicon layers SL1 and silicon-germanium layers SL2 is grown on the exposed upper silicon layer le of the nFET region ([Fig. 2K]).The SL2 silicon-germanium layers of the second SL pseudomorphic superlattice may comprise about 30% germanium and have a thickness between 4 nm and 20 nm, while the SL1 silicon layers of the second SL pseudomorphic superlattice may have a thickness between 4 nm and 20 nm. The layers of the second SL pseudomorphic superlattice may be grown without doping or with a slight . doping n.

[0045] The additional protective layer ld' and the remaining portion of the protective layer ld" are then removed, as shown in [Fig.2L]. On the resulting substrate 1, at least one pFET structure can be directly defined in the pFET region and at least one nFET structure can be directly defined in the nFET region, using the main steps for preparing a wrap-around gate semiconductor structure shown in Figures 1A-1K. The pFET structure and the nFET structure reside directly on the dielectric layer 1b.

[0046] More specifically, the first and second pseudomorphic superlattices SL,SL' may be processed and etched to define at least one nFET fin 2 and one pFET fin 2' in each of the first and second pseudomorphic superlattices SL,SL'. The etched opening may extend to the dielectric layer 1b (and in this case, the dielectric layer preferably has a thickness equal to or greater than 90 nm, as previously discussed). If shallow isolation trenches are desirable, the opening may be defined to penetrate the substrate 1a, through the dielectric layer 1b, and may then be filled with silicon oxide. The substrate may be polished to remove any excess silicon oxide filler.

[0047] Advantageously, at least one of the openings is formed at the boundary between the pFET and nFET regions, in order to electrically isolate the two regions from each other. This opening is filled with oxide to form a boundary trench 10 which will be preserved during the rest of the steps of the method to maintain this electrical isolation, by protecting it with a protective layer ([Fig.2M]).

[0048] In the next step, the pFET and nFET regions are processed to form the dummy gate 4, define the silicon nitride spacers on each side of the dummy gate, epitaxial deposition of the dual source / drain structure on each side of the fins 2,2' (for example, by in situ doped epitaxial formation of the source and drain), and deposition of the interlayer dielectric 7 ([Fig.2N]).

[0049] As shown in [Fig.2O], a protective layer 1d is then selectively formed over the nFET region, and the pFET fin 2' is partially exposed by selectively removing the dummy gate 4. The suspended channel nanosheets of the pFET semiconductor structure, extending between the source / drain regions, are defined by selectively removing the silicon layers SL1', for example by wet etching. The etching reveals a first stack of silicon-germanium channel nanosheets 8' SL2' under compressive stress. A 9' pFET gate structure, composed of a multilayer material with a high dielectric constant k (such as hafnium oxide) and a p work function metal, is then deposited, e.g., by atomic layer deposition, to completely encapsulate each 8' channel nanosheet and form a wrap-around gate pFET structure ([Fig.2P]).

[0050] The same process is repeated on the nFET region, while the pFET region is protected by a selectively formed protective layer. The suspended channel nanosheets 8 of the nFET semiconductor structure, extending between the source / drain regions, are defined by selectively removing the SL2 silicon-germanium layers of the nFET fin, for example by wet etching. The etching reveals a first stack of SL1 silicon channel nanosheets 8. The channel nanosheets 8 can be strained if the original top silicon layer 1e was initially strained. An nFET gate structure 9, composed of a multi-layer material with a high dielectric constant k (such as hafnium oxide) and a work function metal n, is then deposited, for example by atomic layer deposition, to completely encapsulate each nanochannel sheet 8 and form a wrap-around gate nFET structure.

[0051] After removing the protective layer Id, and as illustrated in [Fig.2Q], a method according to the invention makes it possible to obtain a semiconductor structure SC comprising a support 1a and a dielectric layer 1b directly arranged on the support 1a. At least one pFET structure is directly arranged on the dielectric layer 1b. Each pFET structure comprises a first stack of channel nanosheets 8' made of compressively strained silicon-germanium and a pFET gate structure 9' encapsulating each channel nanosheet 8 of the first stack. The semiconductor structure SC also comprises at least one nFET structure residing directly on the dielectric layer 1b. Each nFET structure comprises a second vertical stack of channel nanosheets 8 made of silicon and an nFET gate structure 9 encapsulating each channel nanosheet 8 of the second stack.The pFET structures and the nFET structures are separated by a boundary trench 10. .

[0052] Although not visible in the figures, the SC semiconductor structure also comprises source and drain pFET regions (n-doped) formed on the support and respectively associated with the channel nanosheets of the first stack, and source and drain nFET regions (p-doped) formed on the support and respectively associated with the channel nanosheets of the second stack.

[0053] A method according to the invention can be used to form so-called "forksheet" FET structures. A "forksheet" FET structure comprises both an nFET structure and a pFET structure, with a thin dielectric wall separating the two structures.

[0054] As shown in [Fig.3A], the method according to the invention is applied to a substrate 1 to define a plurality of pFET and nFET sub-regions which are adjacent to each other and which pave the front face of the substrate. The steps illustrated in FIGS. 2A to 2L can be applied accordingly to the substrate 1.

[0055] The pFET and nFET sub-regions are separated from each other by boundary grooves 1t. A portion of the upper silicon layer 1e forms the bottom of the boundary grooves. According to one embodiment, this portion can be removed by etching and the trench filled with a dielectric, such as silicon nitride, to form a plurality of boundary trenches, completely electrically isolating the pFET and nFET sub-regions ([Fig.3B]).

[0056] The method can then be applied to the resulting structure, to define two pFET 2' fins in a pFET sub-region and two nFET 2 fins in an nFET sub-region, as shown in [Fig.3C]. After finalizing the pFET and nFET structures, a plurality of forksheet semiconductor structures FS1-FS5 can be defined by grouping adjacent pFET and nFET structures, as shown in [Fig.3D].

[0057] Other variations of the disclosed embodiments may be understood and made by those skilled in the art of the claimed invention, from a study of the drawings, the disclosure and the appended claims.

[0058] In particular, the thickness of the channel nanosheets may be chosen based on the final application of the structure. Digital applications generally require or benefit from thinner channels, and the thickness of the channel nanosheets may then be between 4 nm and 10 nm. Analog applications may require or benefit from thicker channels, and the thickness of the channel nanosheets may then be selected for this application and be between 10 nm and 20 nm.

[0059] Multiple semiconductor structures according to the present invention may be stacked together, in a 3D structure, or fabricated separately and connected in a system using a 2.5D or 3D integration or packaging approach.

Claims

Claims

1. Semiconductor structure (SC) comprising a. a support (the); b. a dielectric layer (1b) directly placed on the support (1a); c. at least one pFET structure residing directly on the dielectric layer (1b), each pFET structure comprising: i. a first stack of silicon-germanium channel nanosheets subjected to compressive stress; ii. a pFET gate structure encapsulating each channel nanosheet of the first stack; and d. at least one nFET structure residing directly on the dielectric layer (1b), each nFET structure comprising: i. a second vertical stack of silicon channel nanosheets; ii. an nFET gate structure encapsulating each channel nanosheet of the second stack.

2. The semiconductor structure of claim 1, wherein the silicon of the channel nanosheets of the second vertical stack is subjected to tensile stress.

3. The semiconductor structure according to claim 1 further comprises: a. source and drain pFET regions formed on the support and respectively associated with the channel nanosheets of the first stack and; b. source and drain nFET regions formed on the support and respectively associated with the channel nanosheets of the second stack.

4. The semiconductor structure according to one of the preceding claims further comprises a boundary trench (10) separating the pFET structures and the nFET structures.

5. The semiconductor structure according to one of the preceding claims, in which the channel nanosheets of the first stack and the second stack have a thickness between 4 nm and 20 nm.

6. A method of preparing a semiconductor structure (SC), comprising the following steps: a. providing a substrate (1) comprising a support (1a), a dielectric layer (1b) directly arranged on the support (1a), and an upper silicon film (1e) directly arranged on the dielectric layer (1b); b. transforming, in a pFET region of the substrate (1), a portion of the upper silicon film (le) into a silicon-germanium film (le1) stressed in compression, the remaining portion of the upper silicon film (le) forming an nFET region of the substrate (1); c. selectively growing, on the pFET region, a first pseudomorphic superlattice (SL1) composed of silicon layers (SL11) and compressively strained silicon-germanium layers (SL21); d. defining at least one pFET structure residing directly on the dielectric layer (1b) by: i. selectively removing the silicon layers of the first pseudomorphic superlattice (SL1) to define a first stack of channel nanosheets (8') consisting of compressively strained silicon-germanium layers; ii. forming by deposition a pFET gate structure (9') encapsulating each channel nanosheet of the first stack; e. selectively growing on the nFET region a second pseudomorphic superlattice (SL) composed of silicon layers (SL1) and silicon-germanium layers (SL2); f. defining at least one nFET structure residing directly on the dielectric layer (1b) by: i. selectively removing the silicon-germanium layers (SL2) from the second pseudomorphic superlattice (SL) to define a second stack of channel nanosheets (8) made of silicon layers (SL1); ii. forming by deposition an nFET gate structure (9) by encapsulating each channel nanosheet (8) of the second stack.

7. A method according to claim 6 wherein the upper silicon film (Ie) of the substrate (1) is subjected to a tensile stress.

8. The method of claim 7 further comprising, before the step of transforming a portion of the upper silicon film (Ie), a step of relaxing, at least in part, the tensile stress of the upper silicon film (Ie) in the pFET region.

9. The method of claim 8, wherein the tensile stress relaxation comprises amorphizing, in the pFET region, a portion of the upper silicon film (Ie) by ion implantation and heat treating the substrate (1) to recrystallize the amorphous portion.

10. A method according to one of claims 6 to 9, wherein transforming a portion of the upper silicon film (Ie) comprises: a. selectively forming a germanium (If)-rich layer on the upper silicon film (Ie) of the pFET region; and b. oxidizing at least a portion of the germanium (If)-rich layer to diffuse germanium species into the upper silicon film (Ie) in the pFET region, thereby forming the compressively strained silicon germanium layer.

11. The method of claim 10, wherein the germanium (If)-rich layer is a silicon-germanium layer having a germanium concentration of between 10% and 20%, and a thickness of between 5 and 10 nm.

12. Method according to one of claims 6 to 11, in which the silicon layers (SL11) of the first pseudomorphic superlattice (SL1) each have a thickness of between 4 nm and 20 nm, and the silicon-germanium layers (SL21) of the first pseudomorphic superlattice (SL) each have a thickness of between 4 nm and 20 nm.

13. Method according to one of claims 6 to 12, in which the silicon-germanium (SL2) layers of the second pseudomorphic superlattice (SL) each have a thickness between 4 nm and 20 nm, and the silicon layers (SL1) of the second pseudomorphic superlattice (SL) each have a thickness between 4 nm and 20 nm.

Images