Microelectronic device comprising an enclosing grid and method for making such a device

Abstract

Title: Microelectronic device comprising a surrounding gate and method of making such a device The invention relates to a microelectronic device comprising a transistor (T1, T2) comprising at least two channels (41a, 41b, 41c) stacked along a principal direction (z), a first gate (G1) partially surrounding one of the channels (41a, 41b, 41c), a second gate (G2) partially surrounding said channel (41), a source (42) and a drain (43) on either side of the channels (41a, 41b, 41c), and source and drain contacts (60S, 60, 60D) connected respectively to the source (42) and the drain (43), a dielectric layer (70, 71, 72) of gate separating each channel (41) from the surrounding gates (G1, G2). The first and second grids (G1, G2) are insulated from each other so that they can be independently polarized. The invention also relates to a method for implementing such a device. Figure for the abstract: Fig. 22A

Description

Title of the invention: Microelectronic device comprising a wrapping grid and method for producing such a device Technical field

[0001] The invention relates to the field of microelectronics technologies. It finds a particularly advantageous application in the manufacture of advanced FET (Field-Effect Transistor) type devices with a surrounding gate and channel based on semiconductor materials, in particular based on two-dimensional (2D) materials or semiconductor oxides. STATE OF THE ART

[0002] The constant increase in transistor performance was first made possible by the reduction in transistor dimensions, for a classic MOSFET (“Metal-Oxide-Semiconductor Field-Effect Transistor”) architecture based on silicon.

[0003] This classic architecture then gave way to other types of architectures better suited to the performances specified in technological nodes below 12 nm. The so-called "finFET" architecture, for example, makes it possible to meet the performances set by the 7 nm and 5 nm technological nodes. Such an architecture makes it possible, in particular, to easily adjust the threshold voltage of the transistors to favor high performances or low energy consumption, depending on the targeted applications.

[0004] For the next technological nodes, particularly from 3 nm and below, other architectures offering better electrostatic control are necessary. One architecture envisaged to address the issues of these next technological nodes includes gate-enveloping transistors known as GAA transistors (acronym for Gate Ail Around). These GAA transistors typically include very thin channels, in the form of nanowires or nanosheets, stacked on top of each other. This type of architecture is, however, less versatile than the "finFET" architecture. The threshold voltage cannot be easily adjusted.

[0005] The document “Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications, R. Bao et al., 2019 IEEE International Electron Devices Meeting (IEDM)” discloses a solution for integrating nanosheet GAA transistors with a multitude of threshold voltages. The device and method disclosed by this document are based on the introduction of variable nanosheet dimensions within a single stack, with good gate dimensional control. The different portions of the surrounding gate have thus different thicknesses of metal. This makes it possible to obtain different threshold voltages for the same stack. Four different threshold voltages are thus accessible via this architecture. To increase the number of accessible threshold voltages, different zones, made with different technological parameters, remain necessary.

[0006] A major challenge for the development of these GAA transistor architectures is the possibility of finely adjusting their threshold voltage.

[0007] A first objective of the invention is to propose a GAA transistor architecture allowing extended control of the threshold voltage. A second objective of the invention is to propose a method for producing such a GAA transistor architecture. Another objective of the invention is to at least partially overcome the drawbacks of known devices and methods. SUMMARY

[0008] To achieve these objectives, according to one embodiment, a microelectronic device is provided comprising at least one transistor comprising: - at least two channels stacked along a main direction z, each channel being based on a semiconductor material, - a grid surrounding at least one of the channels, - a source and a drain on either side of the channels, and source contacts and drain connected respectively to the source and drain, - a dielectric gate layer separating each channel from the gate,

[0009] The gate corresponds to a first gate partially surrounding at least one of the channels.

[0010] Advantageously, the at least one transistor comprises a second gate partially surrounding the same channel as that surrounded by the first gate, the first and second gates being electrically insulated from each other, so that they can be biased independently of each other.

[0011] Thus, the device comprises two gates surrounding the transistor channels, which can be biased independently. This makes it possible to adjust the threshold voltage of the device continuously, unlike known solutions which allow access to only a few threshold voltages previously fixed by the design of the architecture. The device according to the invention advantageously has a wide range of threshold voltages for a GAA architecture. It can be described as a double gate device, or "dual gate". The gate dielectric layer can have ferroelectric properties, for example for the production of memory transistors of the FeFET type (acronym for "ferroelectric field effect transistor").

[0012] Another aspect of the invention relates to a method of manufacturing this microelectronic device. The method comprises the following steps: Providing on a substrate a stack in the main direction z comprising a plurality of first layers in a first material alternating with a plurality of second layers in a second material alternating with a plurality of third layers in a third material, the first, second and third materials being different, Forming a first etching mask on this stack, Forming in this stack first openings defining first patterns perpendicular to the first etching mask, Forming a sacrificial grid on either side of the first patterns, in the first openings, Forming a second etching mask on the first etching mask and on the sacrificial grid, the second etching mask being transverse to the first etching mask, Form in the first patterns second openings defining second patterns directly above the second engraving mask, Partially removing, from the second openings, the third material of the third layers selectively to the first and second materials of the first and second layers, so as to form third spaces in the third layers, Filling the third spaces with a third dielectric material to form third internal spacers, Partially removing, from the second openings, the first material of the first layers selectively to the second material of the second layers and to the third internal spacers, so as to form first spaces in the first layers, preferably in line with the third internal spacers, Filling the first spaces with a first dielectric material to form first internal spacers, Partially removing the sacrificial grid so as to form third openings opening onto remaining parts of the third layers, Completely removing, from the third openings, the third material from the remaining parts of the third layers, so as to form third cavities, Forming a first insulation layer in the third cavities, Filling the third cavities with a first metallic material, so as to form the first grid partially surrounding the second layers, Completely removing a remaining part of the sacrificial grid so as to form fourth openings opening onto remaining parts of the first layers, - Completely remove, from the fourth openings, the first material from the remaining parts of the first layers, so as to form the first cavities, - Form a second layer of insulation in the first cavities, - Fill the first cavities with a second metallic material, so as to to form the second grid partially surrounding the second layers, - Filling the second openings with an electrically conductive material so as to form source and drain contacts in contact with the second layers.

[0013] A principle of the method according to the invention consists in selectively replacing certain layers of the initial stack, here the first and third layers, to form two typically inter-digitated gate parts, surrounding layers based on a semiconductor material forming the channels of the transistor, here the second layers. The advantages mentioned above for the device apply mutatis mutandis to the method according to the invention.

[0014] According to one possibility, the second layers are subsequently replaced by a semiconductor material in order to form the channels of the transistor. In this case, the initial stack does not include the semiconductor material forming the channels of the transistor. The subsequent deposition of the semiconductor material aims to better preserve the semiconductor material. According to a preferred possibility, the semiconductor material is a two-dimensional (2D) material chosen from transition metal dichalcogenides MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S) or selenium (Se). The method makes it possible in particular to introduce layers of 2D material at the end of the process, after structuring the stack and in particular after the formation of the internal spacers. This advantageously makes it possible to limit the risk of degradation of the 2D material during the process. The 2D material is not exposed to all the steps of the manufacturing process.The 2D material is thus preserved.

[0015] Such late introduction of the 2D material during the manufacturing process also makes it possible to use standard microelectronics technologies for forming and structuring the stack. There is no need to modify or adapt the standard technological structuring steps to the constraints of using the 2D material. The costs of the process are thus advantageously limited. The process can be more easily implemented in existing production lines.

[0016] Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other benefits can be incorporated. BRIEF DESCRIPTION OF THE FIGURES

[0017] [Fig. 1 A] [Fig.2A] [Fig.3A] [Fig.4A] [Fig.5A] [Fig.ôA] [Fig.7A] [Fig.8A] [Fig.9A] [Fig. 10 A] [Fig. 11 A] [Fig. 12A] [Fig. 13 A] [Fig. 14A] [Fig. 15 A] [Fig. 16A] [Fig. 17 A] [Fig. 18 A] [Fig. 19A][Fig.20A][Fig.21A][Fig.22A] Figures nA (n=1...22) schematically illustrate, along xz cross sections, steps for manufacturing a device with superimposed channels, according to a first embodiment of the present invention.

[0018] [Fig.lB][Fig.2B][Fig.3B][Fig.4B][Fig.5B][Fig.6B][Fig.7B][Fig.8B][Fig.9B][Fig.l0 B][Fig.llB][Fig.l2B][Fig.l3B][Fig.l4B][Fig.l5B][Fig.l6B][Fig.l7B][Fig.l8B][Fig.l 9B][Fig.20B][Fig.21B][Fig.22B] Figures nB (n=1...22) schematically illustrate, according to transverse sections yz indicated in the corresponding figures nA, the same steps of manufacturing the device, according to a first embodiment of the present invention.

[0019] [Fig.23 A] [Fig.24A] [Fig.25 A] [Fig.26A] [Fig.27 A] [Fig.28 A] [Fig.29A] [Fig.30A] [Fig.3 lA][Fig.32A][Fig.33A][Fig.34A] Figures nA (n=23...34) schematically illustrate, along xz cross sections, steps in manufacturing a device with superimposed channels, according to a second embodiment of the present invention.

[0020] [Fig.23B] [Fig.24B] [Fig.25B] [Fig.26B] [Fig.27B] [Fig.28B] [Fig.29B] [Fig.30B] [Fig.31 B][Fig.31B][Fig.32B][Fig.33B][Fig.34B] Figures nB (n=23...34) schematically illustrate, according to transverse sections yz indicated in the corresponding figures nA, the same steps of manufacturing the device, according to a second embodiment of the present invention.

[0021] In the cross-sectional figures, section planes are indicated (A-A', B-B', ..., P-P'..., Z-Z', a- a', ..., e-e', ..., 0-0') with cross-references to the section planes of the corresponding figures. The drawings are given as examples and do not limit the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to the scale of practical applications. In particular, in the principle diagrams, the thicknesses and / or dimensions of the different layers, patterns and reliefs are not representative of reality. For reasons of clarity, all of the alphanumeric references are not systematically repeated from one figure to another.It is understood that the elements already described and referenced, when reproduced in another figure, typically bear the same alphanumeric references, even if these are not explicitly mentioned. A person skilled in the art will easily identify the same element reproduced in different figures. DETAILED DESCRIPTION

[0022] Before commencing a detailed review of embodiments of the invention, are listed below are optional features that may be used in combination or alternatively:

[0023] According to one example, each channel is partially surrounded by the first grid and is partially surrounded by the second grid.

[0024] According to one example, the first grid and the second grid are interdigitated.

[0025] According to one example, each channel is interposed between a finger of the first grid and a finger of the second grid.

[0026] According to one example, the first grid covers two adjacent sides of one of the channels, and the second grid covers two other adjacent sides of this channel.

[0027] According to one example, the first and second grids have complementary shapes completely surrounding at least one of the channels, in particular surrounding all sides of this channel.

[0028] According to one example, the semiconductor material is a transition metal dichalcogenide MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S), selenium (Se) or tellurium (Te).

[0029] According to another example, the semiconductor material is based on a semiconductor oxide, for example based on IGZO (Indium Gallium Zinc Oxide), In2O3, IWO (Tungsten-Doped Indium Oxide), ITO (Indium Tin Oxide), IAZO (Indium Aluminum Zinc Oxide), InGaZnO, InGaO, InZnO or an amorphous semiconductor oxide.

[0030] According to another example, the semiconductor material is based on graphene, hexagonal boron nitride “h-BN”, phosphorene.

[0031] According to one example, the stack comprises an alternation of a first layer with a second layer with a third layer. Preferably, the initial stack does not comprise the semiconductor material of the transistor channels, nor the materials of the different gates or parts of the surrounding gate. According to one example, the first layers of the provided stack are only in contact with the second layers and the third layers of the provided stack are only in contact with the second layers.

[0032] According to an example, the first and third internal spacers are based on silicon nitride. The first internal spacers are preferably in contact with the remaining portions of the first layers. The third internal spacers are preferably in contact with the remaining portions of the third layers. Before forming the first internal spacers, the partial removal of the first material of the first layers is configured to keep portions of the first layers between the first spaces. These portions are called remaining portions. The remaining portions of the first layers are thus located between the first spaces, in a direction of the xy plane. Before forming the third internal spacers, the partial removal of the third material of the third layers is configured to keep parts of the third layers between the third spaces. These parts are called remaining parts. The remaining parts of the third layers are thus located between the third spaces, along a direction of the xy plane.

[0033] According to one example, the method further comprises a sequence of steps configured to replace the second layers, said sequence comprising the following steps: - Completely removing, from the second openings, the second material of the second layers, for example selectively from the first material of the first layers, so as to form second spaces, - Preferably form a dielectric layer in the second spaces, - Deposit a layer based on a semiconductor material in the second spaces, so as to form: • channels based on the semiconductor material directly above the first and second gates, under the first and second etching masks, and • sources and drains based on the semiconductor material directly above the first and third internal spacers.

[0034] Typically, for CMOS applications (MOSFET transistors) the dielectric layer does not have ferroelectric properties. For memory applications (FeFET transistors) this dielectric layer has ferroelectric properties.

[0035] According to one example, the sequence of steps configured to replace the second layers is performed after formation of the first and third internal spacers and the formation of the source and drain contacts is performed after said sequence of steps and before the partial removal of the sacrificial gate. This type of process, typically called "gate last", or here "dual gate last", provides for the formation of the functional gate at the end of the process, replacing the sacrificial gate. This makes it possible to preserve the dimensional characteristics of the first and second gates. This makes it possible to obtain better control of the threshold voltage of the MOSFET transistors. The thermal budget linked to the deposition of the layer based on the semiconductor material does not impact the equivalent thickness of gate oxide at the interface with the first and second gates. The structural and electrical characteristics of the two functional gates are better controlled.

[0036] According to one example, the sequence of steps configured to replace the second layers is performed after formation of the first and second gates and before formation of the source and drain contacts. This type of method, typically called "gate first", or here "dual gate first", or even "channel last", provides for the formation of the functional gate replacing the sacrificial gate at the beginning of the process. The channels are formed at the end of the process. This allows the properties of the channels to be preserved, particularly when the transistor channels are based on a temperature-sensitive material.

[0037] According to one example, the method further comprises forming spacers on flanks of the first and second etching masks, said spacers bearing on an upper face of the first patterns.

[0038] According to one example, the deposition of the layer based on the semiconductor material is also carried out on sides of the second pattern substantially parallel to the main direction z, in particular on sides of the first internal spacers and on sides of the third internal spacers. This makes it easier to reconnect the source and drain contacts in the device.

[0039] According to one example, the deposition of the layer based on the semiconductor material is configured to form lateral portions of the layer based on the semiconductor material on sides of the second pattern substantially parallel to the main direction z, and horizontal portions of the layer based on the semiconductor material in the second spaces, such that the lateral portions are thicker than the horizontal portions. Thicker lateral portions make it possible to reduce the contact resistance of the source and drain contacts. The channels of the transistor are formed in the horizontal portions.

[0040] According to one example, the deposition of the layer based on the semiconductor material is configured to form lateral portions of the layer based on the semiconductor material on the spacers, on the first internal spacers and on the third internal spacers.

[0041] According to one example, the method comprises forming source and drain contacts in the second openings.

[0042] According to one example, the deposition of the layer based on the semiconductor material is carried out by chemical vapor deposition or by atomic layer deposition. Chemical vapor depositions are easy to implement. Atomic layer depositions make it possible to precisely control the thickness of the layer based on the semiconductor material. These deposits make it possible to obtain very good conformity for the layer based on the semiconductor material.

[0043] According to one example, the semiconductor material is chosen from transition metal dichalcogenides MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S), selenium (Se) or tellurium (Te).

[0044] According to another example, the semiconductor material is chosen based on a semiconductor oxide, for example based on IGZO (Zinc-indium-gallium oxide), In2O3, IWO (Tungsten-doped indium oxide), ITO (Indium-tin oxide), IAZO (Indium-aluminum zinc oxide), InGaZnO, InGaO, InZnO or an amorphous semiconductor oxide.

[0045] According to one example, the first material is chosen from SiGe with a germanium concentration of between 20%at and 25%at, the second material is chosen from Si, and the third material is chosen from SiGe with a germanium concentration of around 50%at. These materials can be easily epitaxially grown using conventional microelectronics technological processes. This makes it possible to benefit from existing technological pathways. The cost of the process is reduced. The assignment of the different materials to the different layers can be permuted.

[0046] According to one example, the formation of the sacrificial gate is carried out such that the sacrificial gate extends over an entire height of the first openings. According to one example, the first openings extend over the entire height of the stack of the first, second and third layers. The sacrificial gate extends over the entire height of the stack. The sacrificial gate typically rests on the substrate. This makes it possible to provide access to all the layers of the stack via the third and fourth openings.

[0047] According to one example, the deposition of the layer based on the semiconductor material is configured so that the layer based on the semiconductor material completely fills the second spaces.

[0048] According to another example, the deposition of the layer based on the semiconductor material is configured so that the layer based on the semiconductor material partially fills the second spaces. According to one example, the method further comprises, after deposition of the layer based on the semiconductor material, a deposition of an additional dielectric layer configured to fill the second spaces. This makes it possible to form a layer based on the semiconductor material of low thickness, without constraint on the thickness of the second layers of the stack. The layer based on the semiconductor material may have a thickness less than that of the second layers of the initial stack.

[0049] According to one example, the substrate is a solid silicon-based substrate.

[0050] According to one example, the first openings are formed in a longitudinal direction longitudinal direction x and the second openings are formed in a transverse direction y perpendicular to the longitudinal direction x, said first and second openings extending to the substrate.

[0051] According to one example, the removal of the first material of the first layers is done selectively to the second material of the second layers with a SiO:2o selectivity of at least 5:1, preferably at least 10:1. According to one example, the removal of the third material of the third layers is done selectively to the second material of the second layers with a SiO:2o selectivity of at least 5:1, preferably at least 10:1.

[0052] According to one example, the removal of the second material of the second layers is done selectively to the first material of the first layers with a selectivity S2o:io of at least 5:1, preferably at least 10:1. According to one example, the removal of the second material of the second layers is done selectively to the third material of the third layers with a selectivity S2o:3o of at least 5:1, preferably at least 10:1.

[0053] According to one example, the deposition of the layer based on the semiconductor material is configured to form lateral portions of the layer based on the semiconductor material on flanks of the second pattern in the second openings. According to one example, the method further comprises forming source and drain contacts in said second openings and on the lateral portions of the layer based on the semiconductor material, before the start of the removal of the sacrificial gate, or after forming the first and second gates.

[0054] Unless incompatibility exists, it is understood that all of the above optional features may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention. The features and advantages of one aspect of the invention, for example the device or the method, may be adapted mutatis mutandis to the other aspect of the invention.

[0055] The invention relates generally to a microelectronic device with GAA transistors and a manufacturing method. Such a microelectronic device may have a "GAA stacked nanosheet" type architecture, i.e. with stacked nanosheets and a partially or fully encapsulating gate. An architecture with stacked nanowires and a partially or fully encapsulating gate is also possible.

[0056] The nanowires or nanosheets typically each comprise a conduction channel of a transistor. These channels are stacked in a z direction. This means that they each occupy a level of given altitude in the z direction. A level can be defined between two planes perpendicular to the z direction.

[0057] In the present invention, each transistor comprises two gates. These two gates each comprise portions surrounding the channels of the transistor. These portions may typically be complementary so as to completely or almost completely surround at least one of the channels of the transistor. These two gates may be designated as "enveloping" even if each gate does not completely envelop the channel(s) of the transistor. The combination of the two gates may be similar to a gate completely surrounding the channel(s) of the transistor. This architecture therefore falls under both the nomenclatures "Gâte Ail Around" (totally enveloping gate) and "Dual Gâte" (double gate).

[0058] Advantageously, the method according to the invention can be implemented for the production of GAA MOS transistors for the 5 nm and sub-5 nm technological nodes.

[0059] A microelectronic device comprising GAA transistors with stacked channels can be advantageously integrated into logic systems having 3D architectures. These transistors can in particular be associated with other structural or functional elements so as to design complex systems.

[0060] A particular aspect of the invention relates to the implementation of 2D materials to produce the nanowires or nanosheets of the device. These 2D materials have semiconductor properties, in particular through the presence of an electronic gap.

[0061] 2D materials typically correspond to compounds with a lamellar structure consisting of two-dimensional sheets, stacked along the crystallographic axis c. The atomic bonds within each sheet are strong, covalent in nature. The bonds between sheets are much weaker, of the Van der Waals type. These two-dimensional sheets are also called monolayers.

[0062] In the context of the present invention, the monolayers are preferably semiconductor monolayers of the MX2 type where M is molybdenum (Mo) or tungsten (W) and X is sulfur (S) or selenium (Se). Each "monolayer" is here composed of a plane of metal cations M inserted between two planes of anions X. A monolayer therefore typically comprises three atomic planes: the atoms of the transition metal (Mo or W) form a plane sandwiched between two planes of chalcogens (S, Se or Te, for example). Each transition metal atom is connected to six chalcogen atoms. These anions are in trigonal prismatic coordination with respect to the metal atoms. The monolayers of MX2 transition metal dichalcogenides have a hexagonal atomic lattice.

[0063] The monolayers of transition metal dichalcogenides MX2 are preferably based on molybdenum disulfide MoS2, MoSe2, MoTe2, WS2, WSe2.

[0064] An alternative possibility concerns the implementation of semiconductor oxides to produce the nanowires or nanosheets of the device, for example IWO, IGZO, ITO, InGaZnO, InGaO, InZnO, In2O3, IAZO. Another possibility concerns the implementation of graphene, hexagonal boron nitride "h-BN", phosphorene (also known as "Black Phosphorous" BP), in particular in the form of a monolayer.

[0065] It is specified that, in the context of the present invention, the terms “on”, “overcomes”, “covers”, “underlying”, “facing” and their equivalents do not necessarily mean “in contact with”. Thus, for example, the deposition or application of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either di directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0066] A substrate, a film, a layer, “based” on a material A, is understood to mean a substrate, a film, a layer comprising this material A only or this material A and possibly other materials, for example doping elements or alloying elements. Thus, a spacer based on silicon nitride SiN may for example comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Si3N4), or even a silicon oxynitride (SiON).

[0067] The word "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 20. In the present invention, the dielectric layer may have ferroelectric properties.

[0068] Several embodiments of the invention implementing successive steps of the manufacturing method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them.

[0069] Furthermore, the term “step” means the carrying out of a part of the method, and can designate a set of sub-steps.

[0070] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term step does not necessarily mean unitary and inseparable actions in time and in the sequence of the phases of the process.

[0071] The term “selective etching with respect to” or “etching having selectivity with respect to” means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching rate of the material A greater than the etching rate of the material B. The selectivity is the ratio between the etching rate of the material A and the etching rate of the material B. It is noted SA:B. A selectivity SA:b of 10:1 means that the etching rate of the material A is 10 times greater than the etching rate of the material B.

[0072] The different patterns formed during the manufacturing steps typically have a structure intended to evolve during the process steps. Thus, the patterns may include the sacrificial layers of the initial stack, the layers based on 2D material or semiconductor oxide, the dielectric layers, continuous or discontinuous. The different patterns aim to form, at the end of the process, “patterns of transistors” each comprising at least one conduction channel and two gates surrounding said channel, a dielectric barrier separating the two gates from each other and the channel, a source and a drain on either side of the channel. The assignment of the first and second layers in the initial stack can be reversed.

[0073] A preferably orthonormal reference frame, comprising the axes x, y, z is shown in the attached figures.

[0074] In the present patent application, we will preferably speak of thickness for a layer or a film, and of height for a device or a structure. The thickness is taken along a direction normal to the main extension plane of the layer or film. Thus, a surface layer of silicon (topSi) typically has a thickness along z. A gate pattern formed on such a surface layer has a height along z. The relative terms “on”, “overcomes”, “under”, “underlying” refer to positions taken along the z direction. A “lateral” dimension corresponds to a dimension along a direction of the xy plane. A “lateral” or “laterally” extension is understood to mean an extension along one or more directions of the xy plane.

[0075] An element located "perpendicular to" or "in line with" another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the cross-sectional figures.

[0076] The terms "substantially", "approximately", "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and..." and equivalents mean that the limits are included, unless otherwise stated.

[0077] The following description presents examples of implementation of the method according to the invention in a context of developing a complex 3D device. The scope of this description is obviously not limiting of the invention.

[0078] Figures 1A, 1B to 22A, 22B schematically illustrate steps in manufacturing a device comprising GAA transistors according to a first embodiment. Figures nA (n= 1...22) correspond to first transverse sections each illustrating a different step of the manufacturing process. Figures nB (n=1.. .22) correspond to second transverse sections each illustrating the same step as the corresponding figure nA. This first embodiment can in particular be described as “gate last” or “dual gate last”. The first and second gates are formed here at the end of the process, after formation of the transistor channels.

[0079] As illustrated in Figures 1A, 1B, a first step consists of providing or producing a stack E of semiconductor layers 10, 20, 30 on a substrate S. The substrate S can be a substrate of the SOI (Silicon On Insulator) or GeOI (Germanium On Insulator) or SGOI (Silicon-Germanium On Insulator). These known substrates comprise, according to the terminology common to those skilled in the art, a thick silicon SI layer called “Si bulk”, a silicon oxide S2 layer called “BOX” (Burried Oxide) and a thin surface layer, respectively based on silicon, germanium or silicon-germanium. This thin surface layer can advantageously correspond to the first layer 10 of the stack E.

[0080] Alternatively, the substrate S can be a bulk Si substrate.

[0081] According to one example, the stack E comprises an alternation of first layers 10 of silicon-germanium (SiGe) having a first composition of Ge, second layers 20 of silicon (Si), and third layers 30 of SiGe having a second composition of Ge.

[0082] The concentrations of Ge in the SiGe alloy of the first and third layers 10, 30 are chosen so as to allow good etching selectivity during the selective etching steps between the different layers. According to one example, the first layers 10 have a first Ge composition of between 20% at and 25% at. According to one example, the third layers 30 have a second Ge composition of the order of 50% at. This stack E is advantageously formed by epitaxy of the SiGe layers 10, 30 and Si 20. This step of forming the stack E is inexpensive and well known to those skilled in the art. The thicknesses of the Si and SiGe layers may typically be of the order of 10 nm, and more generally between 5 nm and 20 nm for example. In a known manner, in order to avoid the formation of structural defects, the maximum thicknesses permitted for the SiGe layers 10, 30 depend in particular on the Ge concentration chosen.

[0083] In the example illustrated in figures 1A, 1B two layers 10 of SiGe are alternated with three layers 20 of epitaxially grown Si and two layers 30 of SiGe. A Si / SiGe superlattice is thus obtained. The number of layers of Si and SiGe can naturally be increased. This ultimately makes it possible to increase the number of stacked channels in the final device. The sequence of the first, second and third layers 30 is preferably chosen so that each second layer 20 is intercalated between a first layer 10 and a third layer 30. In the final device, the first layers are intended to be replaced by fingers of a first gate and the third layers are intended to be replaced by fingers of a second gate, the first and second gates being interdigitated. The second layers are intended to form transistor channels partly surrounded by the first gate and partly surrounded by the second gate.The sequence of the different layers 10, 20, 30 is therefore chosen according to the desired design for the final device. According to one example, the first layers 10 are only in contact with the second layers 20 and the third layers 30 are also. only in contact with the second layers 20.

[0084] Generally speaking, the first material of the first layers 10, the second material of the second layers 20 and the third material of the third layers 30 are chosen so that some can be etched selectively with respect to the others. Thus, other pairs of first, second and third materials are possible. By respecting this condition of selectivity during etching, the first, second and third materials can be chosen from dielectric materials (oxides and nitrides for example), semiconductor materials, metallic materials. Care will be taken in particular to ensure that the third material can be etched selectively with respect to the first and second materials, and that the first material can be etched selectively with respect to the second material.

[0085] As illustrated in Figures 2A, 2B, a conventional lithography / etching step is carried out in order to define first patterns 101M, and first openings 100. The etching is anisotropic and directed along z. It is configured to etch the stack E, here the Si / SiGe superlattice, over its entire height, stopping on the substrate S, here the BOX S2. It can be carried out by plasma using an HBr / 02 etching chemistry. The first patterns 10IM can have a length Li along x of between 10 nm and 500 nm. They preferably have a width h along y of between 10 nm and 120 nm, for example of the order of 40 nm. This first structuring of the E stack in the form of fins or "fins" according to current Anglo-Saxon terminology, makes it possible to define a plurality of superimposed nanowires or nanosheets.The “end” patterns 101M are typically topped by an etching mask or hard mask 130 implemented during this first structuring of the stack E.

[0086] As illustrated in Figures 3A, 3B, sacrificial gates 150 are then formed between the “end” patterns 101M. The formation of these sacrificial gates 150 is typically done by deposition then chemical mechanical polishing CMP with stopping on the hard mask 130. The sacrificial gates 150 typically comprise several independent portions located between the “end” patterns 10IM. This facilitates a localized opening of the different portions of the sacrificial gates thereafter. The sacrificial gates 150 typically bear on the substrate S. An etching mask or hard mask 140 is formed transversely to the “end” patterns 101M. This hard mask 140 then participates in a second structuring of the stack E, as well as in a structuring of the sacrificial gates 150, as illustrated in the following figures. The sacrificial grids 150 are for example based on polycrystalline silicon.A thin layer of SiO2 oxide, 7 nm thick for example, is preferably deposited prior to the formation of the sacrificial gates 150. This thin layer of SiO2 oxide (not illustrated in the figures) is thus intercalated between the . sacrificial gates 150 and the “end” patterns 101M. This thin layer of SiO2 oxide can form a stop layer for the subsequent etching of the sacrificial gates 150.

[0087] As illustrated in Figures 4A, 4B, the hard mask 130 is first etched so as to expose the upper face 321 of the stack E. The portions of the hard mask 130 located under the hard mask 140 are retained, as well as the hard mask 140. Spacers 170 are then formed on the yz-oriented flanks of the hard masks 130, 140. In general, in projection along z, these spacers form a continuous ring around the hard masks 130, 140, with a closed contour. In transverse section, however, along the xz plane illustrated in [Fig.4A], the spacer 170 has two facing portions on each of the flanks of the hard masks 130, 140. These two portions are generally designated as being the spacers 170, even if these can be considered as belonging to a single spacer. The spacers 170 typically extend to the upper face 321 of the stack E.The spacers 170 are typically based on silicon nitride SiN or a low dielectric constant dielectric material, for example based on SiCO.

[0088] As illustrated in Figures 5A, 5B, after formation of the spacers 170 by deposition / etching, the anisotropic etching along z is extended in order to define second patterns 102M, and second openings 200. The etching is configured to etch the stack E over its entire height, stopping on the substrate S. It can be carried out by plasma using an HBr / O2 etching chemistry. A second structuring of the stack E is thus carried out.

[0089] As illustrated in Figures 6A, 6B, after formation of the second openings 200, the third layers 30 are partially etched selectively to the second layers 20, to the first layers 10, to the substrate S and to the spacers 170. The etching of the third material of the third layers 30 typically has a selectivity S30:20 with respect to the second material of the second layers 20, of at least 5:1, preferably at least 10:1. The etching of the third material of the third layers 30 typically has a selectivity S30:10 with respect to the first material of the first layers 10, of at least 5:1, preferably at least 10:1. This partial etching aims to form third spaces 31 directly above the spacers 170. This partial etching is typically stopped in time. It has an isotropic character and can be carried out wet or dry, from the second openings 200.At the end of this partial etching, central parts of the third layers 30 are preserved under the hard masks 130, 140.

[0090] As illustrated in Figures 7A, 7B, the third spaces 31 are then filled with a dielectric material, for example with silicon nitride or with a low permittivity dielectric, to form third internal spacers 131. These “internal” spacers 131 are integrated into the stack E, preferably plumb spacers 170. They are in contact with the central parts of the third layers 30. The formation of the third internal spacers 131 is typically done from the second openings 200.

[0091] As illustrated in Figures 8A, 8B, the first layers 10 are partially etched selectively to the second layers 20, to the substrate S, to the spacers 170 and to the third internal spacers 131. The etching of the first material of the first layers 10 typically has a SiO:2o selectivity relative to the second material of the second layers 20, of at least 5:1, preferably at least 10:1. This partial etching aims to form first spaces 11 directly above the spacers 170 and the third internal spacers 131. This partial etching is typically stopped in time. It has an isotropic character and can be carried out by a wet or dry method, from the second openings 200. At the end of this partial etching, central parts of the first layers 10 are preserved under the hard masks 130, 140.

[0092] As illustrated in Figures 9A, 9B, the first spaces 11 are then filled with a dielectric material, for example with silicon nitride or with a low permittivity dielectric, to form first internal spacers 111. These “internal” spacers 111 are integrated into the stack E, preferably directly above the spacers 170 and the third internal spacers 131. They are in contact with the central parts of the first layers 10. The formation of the first internal spacers 111 is typically done from the second openings 200.

[0093] As illustrated in Figures 10A, 10B, the second layers 20 are then selectively etched at the central portions of the first layers 10 and the third layers 30, and at the internal spacers 111, 131. The etching of the second material of the second layers 20 typically has a S2o:io selectivity relative to the first material of the first layers 10, of at least 5:1, preferably at least 10:1. The etching of the second material of the second layers 20 typically has a S2o:3o selectivity relative to the third material of the third layers 30, of at least 5:1, preferably at least 10:1. This total etching can be stopped at the time, possibly after an over-etching time aimed at guaranteeing the total removal of the second material from the second layers 20. This total etching has an isotropic character and can be carried out by wet or dry means, from the second openings 200.At the end of this etching, the second layers 20 are completely removed to form second spaces 21. The central parts of the first layers 10 and the central parts of the third layers 30 are held by the sacrificial grids 150, as illustrated in [Fig. 10B].

[0094] As illustrated in Figures 1 1A, 1 1B, a dielectric layer 70 is then deposited in the second spaces 21. This dielectric layer 70 is typically based of a high permittivity material, for example based on HfO2. The dielectric layer 70 is intended to form the gate dielectric layer between the channels of the GA A transistors and their surrounding gates. It can be formed by chemical vapor deposition CVD (acronym for “Chemical Vapor Deposition”), by chemical vapor deposition with organometallic precursors MOCVD (acronym for “Metal Organic Chemical Vapor Deposition”) or by atomic layer deposition ALD (acronym for “Atomic Layer Deposition”). It thus covers at least the central parts of the first layers 10 and the central parts of the third layers 30, and preferably the internal spacers 111, 131, and the spacers 170. The dielectric layer 70 typically has a thickness of between 1 nm and 5 nm. According to an alternative example, this layer 70 may be based on a ferroelectric material such as HfZrO2, HZO, Si-doped HfO2 for example.Such a ferroelectric layer 70 can be advantageously used for the production of memory transistors of the FeFET type (acronym for “ferroelectric field effect transistor”). This dielectric layer 70 typically forms a Venetian mesh pattern in each 102M pattern.

[0095] As illustrated in Figures 12A, 12B, a layer 40 based on a semiconductor material is then deposited on the gate dielectric layer 70 in the second spaces 21. The deposition of the semiconductor material is here configured so that the layer 40 completely fills the second spaces 21. The portions of the layer 40 located in the second spaces 21 thus have a perfectly controlled thickness, close to the thickness of the initial second layers. This layer 40 is intended to form the channels 41 of the GAA transistors directly above the central parts of the first layers 10 and the central parts of the third layers 30. This layer 40 is also intended to form the sources 42 and the drains 43 of the GAA transistors directly above the spacers 170 and the internal spacers 111, 131.

[0096] The layer 40 is also typically deposited outside the second spaces 21, on the sides of the spacers 170 and the internal spacers 111, 131. This makes it possible to improve the contact recovery with the sources 42 and the drains 43 of the GAA transistors. The layer 40 thus has horizontal portions in the second spaces 21, in particular between the remaining parts of the first layers and the third layers, and vertical portions on the sides of the spacers 170 and the internal spacers 111, 131. According to one possibility, the thickness of the vertical portions of the layer 40 is greater than the thickness of the horizontal portions of the layer 40. This makes it possible to reduce the contact resistance for the sources 42 and the drains 43 of the GAA transistors.The sources 42 and the drains 43 of the GAA transistors may comprise the horizontal portions directly above the spacers 170 and the internal spacers 111, 131, and at least in part the vertical portions on the sides. spacers 170 and internal spacers 111, 131.

[0097] The semiconductor material of the layer 40 is advantageously a two-dimensional material taken from the transition metal dichalcogenides MX2 with M molybdenum (Mo) or tungsten (W), and X sulfur (S), selenium (Se) or tellurium (Te). Such a 2D material can advantageously be deposited in the form of a thin layer comprising 1 to 10 atomic layers, preferably 1 to 5 atomic layers. The deposition of this 2D material can be done by CVD, MOCVD or ALD. According to another possibility, the semiconductor material of the layer 40 is a semiconductor oxide such as 1TTO (acronym for “Indium Tin Oxide”), 1TGZO (acronym for “Indium Gallium Zinc Oxide”), IWO (meaning “tungsten doped indium oxide”), indium oxide In2O3.Alternatively, the semiconductor material of layer 40 is graphene, hexagonal boron nitride "h-BN", phosphorene (also known as "Black Phosphorous" BP), in the form of a monolayer or a thin layer comprising 1 to 10 atomic layers, preferably 1 to 5 atomic layers.

[0098] As illustrated in Figures 13A, 13B, the second openings can then be filled with one or more metal layers 60, for example based on Ti, TiN, W, or by other metals making it possible to ensure low contact resistance such as Bi, Ni, Au, Sb, etc., in order to form the source and drain contacts. Chemical mechanical polishing CMP is typically carried out in order to remove the excess metal deposited on the patterns 102M. The hard masks 140 are thus exposed.

[0099] As illustrated in Figures 14A, 14B, protective caps 61, for example based on SiO2, are preferably formed at the upper ends of the contacts 60. This makes it possible to protect the underlying metal layers during the following steps of replacing the different portions of sacrificial gate.

[0100] As illustrated in Figures 15A, 15B, the hard mask 140 is partially open to access certain portions of the sacrificial gate 150 via the openings 300a. The different portions of the sacrificial gate 150 are separated by the “end” patterns. In particular, the openings 300a are configured to access every other portion of the sacrificial gate 150, in an alternating manner.

[0101] As illustrated in Figures 16A, 16B, the exposed portions of the sacrificial gate 150 are then removed to form the third openings 300b. This removal can be carried out by wet etching with stopping on the thin SiO2-based stop layer of the sacrificial gate 150. This wet etching typically has a high selectivity with respect to the stop layer. This wet etching can be based on a solution of ammonia salts TM AH (Tetramethylammonium Hydroxide) or TEAH (Tetraethylammonium Hydroxide). The SiO2-based stop layer is then typically wet etched to expose a first flank of the patterns. of “end”. The third openings 300b open onto the central parts of the third layers 30 ([Fig.16B]).

[0102] As illustrated in Figures 17A, 17B, the central portions of the third layers 30 are then completely removed by selective etching with respect to the dielectric layer 70 and the central portions of the first layers 10, from the third openings 300b. This etching aims to form third cavities 32 in place of the central portions of the third layers 30. This etching has an isotropic character and can be carried out by a wet or dry method, from the third openings 300b.

[0103] As illustrated in Figures 18A, 18B, the third openings 300b and the third cavities 32 are then filled with one or more metal layers, for example based on TiN, W, in order to form a first gate G1 of the GAA transistors. Before deposition of the metal layers, a dielectric layer 71 based on a high permittivity material, for example based on HfO2, is previously deposited so as to line the third openings 300b and the third cavities 32. This makes it possible to increase the thickness of the gate dielectric layer between the channels 41a, 41b, 41c of the GAA transistors and the first gate G1. This also makes it possible to isolate the first gate G1 from the central parts of the first layers 10, intended to form a second gate part. Chemical mechanical polishing (CMP) is typically performed to remove excess metal deposited on the 102M patterns.

[0104] As illustrated in Figures 19A, 19B, the hard mask 140 is again partially opened to access the remaining portions of the sacrificial gate 150, via openings 400a.

[0105] As illustrated in Figures 20A, 20B, the remaining portions of the sacrificial gate 150 are then removed to form the fourth openings 400b. This removal can be carried out as previously, by wet etching based on TMAH or TEAH, with a stop on the thin SiO2-based stop layer of the sacrificial gate 150. The SiO2-based stop layer is then typically wet etched to expose a second flank of the “end” patterns. The fourth openings 400b open onto the central portions of the first layers 10 ([Fig.20B]).

[0106] As illustrated in Figures 21A, 21B, the central parts of the first layers 10 are then completely removed by selective etching with respect to the dielectric layers 70, 71, from the fourth openings 400b. This etching aims to form first cavities 12 in place of the central parts of the first layers 10. This etching has an isotropic character and can be carried out by a wet or dry method, from the fourth openings 400b.

[0107] As illustrated in Figures 22A, 22B, the fourth openings 400b and the first cavities 12 are then filled with one or more metal layers, for example based on TiN, W, in order to form a second gate G2 of the GAA transistors. Before deposition of the metal layers, a dielectric layer 72 based on a high permittivity material, for example based on HfO2, is previously deposited so as to line the fourth openings 400b and the first cavities 12. This makes it possible to increase the thickness of the gate dielectric layer between the channels 41a, 41b, 41c of the GAA transistors and the second gate G2. This also makes it possible to isolate the second gate G2 from the first gate G1. Chemical-mechanical polishing CMP is typically carried out in order to remove the excess metal deposited on the patterns 102M.

[0108] A microelectronic device comprising two transistors T1, T2 each comprising three channels 41a, 41b, 41c stacked along z, and two interdigitated covering gates G1, G2, is thus advantageously obtained. The channels 41a, 41b, 41c, the sources 42 and the drains 43 are preferably based on a two-dimensional material. Source and drain contacts 60S, 60, 60D electrically connect these GAA transistors T1, T2.

[0109] Figures 23A, 23B to 34A, 34B schematically illustrate steps of manufacturing a device comprising GAA transistors according to a second embodiment. Figures nA (n=23...34) correspond to first cross-sections each illustrating a different step of the manufacturing method. Figures nB (n=23...34) correspond to second cross-sections each illustrating the same step as the corresponding figure nA.

[0110] Only the different characteristics of this second embodiment compared to the first embodiment are described below. The other characteristics are deemed identical to those of the first embodiment, with reference to the above. This second embodiment can in particular be described as “channel last”. The channels of the transistors are formed here after replacing the sacrificial gate portions with the first and second gates.

[0111] As illustrated in Figures 23A, 23B, after formation of the internal spacers 111, 131, the second openings are filled with a dielectric material 27, for example based on SiO2. The hard mask 140 is partially open to access certain portions of the sacrificial gate 150 via the openings 300a, as previously.

[0112] As illustrated in Figures 24A, 24B, the exposed portions of the sacrificial gate 150 are removed to form the third openings 300b, as before. The third openings 300b open onto the central portions of the third layers 30.

[0113] As illustrated in Figures 25A, 25B, the central portions of the third layers 30 are then completely removed by selective etching with respect to the second layers 20 and central parts of the first layers 10, from the third openings 300b. This etching aims to form third cavities 32 in place of the central parts of the third layers 30. This etching has an isotropic character and can be carried out by wet or dry means, from the third openings 300b.

[0114] As illustrated in Figures 26A, 26B, the third openings 300b and the third cavities 32 are then filled with one or more metal layers, for example based on TiN, W, in order to form the first gate G1 of the GAA transistors. Before deposition of the metal layers, a dielectric layer 71 based on a high permittivity material, for example based on HfO2, is previously deposited so as to line the third openings 300b and the third cavities 32. This makes it possible to form the gate dielectric layer between the second layers 20, which subsequently form the channels of the GAA transistors, and the first gate G1. This also makes it possible to isolate the first gate G1 from the first layers 10, which subsequently form fingers of the second gate G2, as previously.

[0115] As illustrated in Figures 27A, 27B, the hard mask 140 is again partially opened to access the remaining portions of the sacrificial gate 150, and the remaining portions of the sacrificial gate 150 are removed to form the fourth openings 400b, as before. The fourth openings 400b open onto the central portions of the first layers 10.

[0116] As illustrated in Figures 28A, 28B, the central parts of the first layers 10 are then completely removed by selective etching with respect to the dielectric layer 71 and the second layers 20, from the fourth openings 400b. This etching aims to form the first cavities 12 in place of the central parts of the first layers 10.

[0117] As illustrated in Figures 29A, 29B, the fourth openings 400b and the first cavities 12 are then filled with one or more metal layers, for example based on TiN, W, in order to form a second gate G2 of the GAA transistors. Before deposition of the metal layers, a dielectric layer 72 based on a high permittivity material, for example based on HfO2, is previously deposited so as to line the fourth openings 400b and the first cavities 12. This makes it possible to form the gate dielectric layer between the second layers 20, which subsequently form the channels of the GAA transistors, and the second gate G2. This also makes it possible to isolate the second gate G2 from the first gate G1, as previously.

[0118] As illustrated in Figures 30A, 30B, the dielectric material 27 is removed so as to reform the second openings 200b. The second openings 200b open on the second layers 20.

[0119] As illustrated in Figures 31 A, 31B, the second layers 20 are then selectively etched with respect to the dielectric layers 71, 72, from the second openings 200b. This total etching can be stopped in time, possibly after an over-etching time intended to guarantee the total removal of the second material from the second layers 20. This total etching has an isotropic character and can be carried out by a wet or dry method, from the second openings 200b. At the end of this etching, the second layers 20 are completely removed to form second spaces 21, as previously.

[0120] As illustrated in Figures 32A, 32B, according to an optional possibility, a dielectric layer 73 is then deposited in the second spaces 21. This dielectric layer 73 is typically based on a high permittivity material, for example based on HfO2. The dielectric layer 73 can be formed by chemical vapor deposition CVD or MOCVD, or by atomic layer deposition ALD. The dielectric layer 73 typically has a thickness of between 1 nm and 5 nm. The dielectric layer 73 typically makes it possible to increase the thickness of the gate dielectric layers formed by the dielectric layers 71, 72.

[0121] As illustrated in Figures 33A, 33B, the layer 40 based on a semiconductor material is then deposited on the dielectric layer 73 in the second spaces 21. The deposition of the semiconductor material is here configured so that the layer 40 completely fills the second spaces 21, as previously. This layer 40 is intended to form the channels 41 of the GAA transistors directly above the central parts of the first layers 10 and the fingers of the gates G1, G2. This layer 40 is also intended to form the sources 42 and the drains 43 of the GAA transistors directly above the spacers 170 and the internal spacers 111, 131, as previously.

[0122] The semiconductor material of layer 40 is advantageously a 2D material or a semiconductor oxide, as previously.

[0123] As illustrated in Figures 34A, 34B, the second openings can then be filled with one or more metal layers 60, in order to form the source and drain contacts, as before. Chemical mechanical polishing CMP is typically performed in order to remove excess metal deposited on the 102M patterns.

[0124] A microelectronic device comprising two transistors T1, T2 each comprising three channels 41a, 41b, 41c stacked along z, and two interdigitated wrapping gates G1, G2, is thus advantageously obtained, as previously. This second embodiment of the “channel last” type makes it possible to limit the number of technological steps to which the transistor channels are exposed during the formation of the device. The properties of the material forming the transistor channels are thus preserved.

[0125] In view of the foregoing description, it is clear that the proposed device and method offer a particularly effective solution for forming GAA transistors with adjustable threshold voltage. This solution is furthermore advantageously compatible with standard microelectronics methods. The invention is however not limited to the embodiments previously described.

[0126] According to a possibility not illustrated, the layer 40 based on the semiconductor material does not completely fill the second spaces 21. In this case, the portions of the layer 40 located in the second spaces 21 may be significantly thinner than the initial second layers. These horizontal portions may have a thickness corresponding to only a few atomic layers, for example between 1 and 5 atomic layers of semiconductor material. This makes it possible to reduce the dimensions of the channels 41 of the GAA transistors. The performance of the GAA transistors can be improved. A dielectric plug is typically formed between the horizontal portions of the layer 40, in order to fill the second spaces 21. This makes it possible in particular to work with a single monolayer of 2D material. Excellent electrostatic control of the device is thus obtained. The gate length can thus be advantageously reduced.This also improves the mechanical strength of the device and / or prevents deformation of the GAA transistor channels, for example due to heating during operation. This dielectric cap can be formed by CVD deposition and etching, in a conventional manner.

Claims

Claims

1. Microelectronic device comprising at least one transistor (Tl, T2) comprising: • at least two channels (41a, 41b, 41c) stacked in a main direction (z), each channel being based on a semiconductor material, • a gate (Gl, G2) surrounding at least one of the channels (41a, 41b, 41c), • a source (42) and a drain (43) on either side of the channels (41a, 41b, 41c), and source and drain contacts (60S, 60, 60D) connected respectively to the source (42) and to the drain (43), • a gate dielectric layer (70, 71, 72) separating each channel (41) from the gate (Gl), the device being characterized in that the gate (Gl) corresponds to a first gate (Gl) partially surrounding at least one of the channels (41a, 41b, 41c), and in that the at least one transistor (Tl, T2) comprises a second gate (G2) partially surrounding the same channel as that surrounded by the first gate (Gl), the first and second gates (Gl,G2) being electrically insulated from each other, so that they can be polarized independently of each other.,

2. Device according to the preceding claim in which each channel (41a, 41b, 41c) is partially surrounded by the first grid (G1) and is partially surrounded by the second grid (G2).

3. Device according to any one of the preceding claims in which the first grid (G1) and the second grid (G2) are interdigitated, and in which each channel (41a, 41b, 41c) is interposed between a finger of the first grid (G1) and a finger of the second grid (G2).

4. Device according to any one of the preceding claims in which the first grid (G1) covers two adjacent sides of one of the channels (41a, 41b, 41c), and the second grid (G2) covers two other adjacent sides of said channel (41a, 41b, 41c).

5. A method of manufacturing a microelectronic device according to any one of the preceding claims, said method comprising the following steps: • Providing on a substrate (S) a stack (E) in the main direction (z) comprising a plurality of first layers (10) in a first material, alternating with a plurality of second layers (20) in a second material, alternating with a plurality of third layers (30) in a third material, the first, second and third materials being different, • Form a first etching mask (130) on this stack (E), • Form in this stack (E) first openings (100) defining first patterns (101M) directly above the first etching mask (130), • Form a sacrificial grid (150) on either side of the first patterns (101M), in the first openings (100), • Forming a second etching mask (140) on the first etching mask (130) and on the sacrificial gate (150), the second etching mask (140) being transverse to the first etching mask (130), • Forming in the first patterns (101M) second openings (200) defining second patterns (102M) directly above the second etching mask (140), • Partially removing, from the second openings (200), the third material of the third layers (30) selectively to the first and second materials of the first and second layers (10, 20), so as to form third spaces (31) in the third layers (30), • Filling the third spaces (31) with a third dielectric material to form third internal spacers (131), • Partially remove, from the second openings (200), the first material of the first layers (30) selectively to the second material of the second layers (20) and to the third internal spacers (131), so as to form first spaces (11) in the first layers (10), preferably directly above the third internal spacers (131), • Fill the first spaces (11) with a first di- material

6. electrical to form first internal spacers (111), • Partially remove the sacrificial grid (150) so as to form third openings (300b) opening onto remaining parts of the third layers (30), • Completely removing, from the third openings (300b), the third material from the remaining parts of the third layers (30), so as to form third cavities (32), • Form a first insulation layer (71) in the third cavities (32), • Fill the third cavities (32) with a first metallic material, so as to form the first grid (Gl) partially surrounding the second layers (20), • Completely remove a remaining portion of the sacrificial grid (150) so as to form fourth openings (400b) opening onto remaining portions of the first layers (10), • Completely remove, from the fourth openings (400b), the first material from the remaining parts of the first layers (10), so as to form first cavities (12), • Form a second layer of insulation (72) in the first cavities (12), • Fill the first cavities (12) with a second metallic material, so as to form the second grid (G2) partially surrounding the second layers (20), • Filling the second openings (200, 200b) with an electrically conductive material so as to form source and drain contacts in contact with the second layers (20). Method according to the preceding claim further comprising a sequence of steps configured to replace the second layers (20), said sequence comprising the following steps: • Completely remove, from the second openings (200, 200b), the second material of the second layers (20), so as to form second spaces (21), • Preferably form a dielectric layer (70, 73) in the second spaces (21), • Deposit a layer (40) based on a semiconductor material in the second spaces (21), so as to form: • channels (41a, 41b, 41c) based on the semiconductor material directly above the first and second gates (G1, G2), under the first and second etching masks (130, 140), and • sources (42) and drains (43) based on the semiconductor material directly above the first and third internal spacers (111, 131).

7. Method according to the preceding claim in which the sequence of steps configured to replace the second layers (20) is carried out after formation of the first and third internal spacers (111, 131) and in which the formation of the source and drain contacts (60, 60S, 60D) is carried out after said sequence of steps and before the partial removal of the sacrificial gate (150).

8. The method of claim 6 wherein the sequence of steps configured to replace the second layers (20) is performed after formation of the first and second gates (G1, G2) and before formation of the source and drain contacts (60, 60S, 60D).

9. Method according to any one of claims 5 to 8 further comprising a formation of spacers (170) on flanks of the first and second etching masks (130, 140), said spacers (170) bearing on an upper face (321) of the first patterns (101M).

10. Method according to any one of claims 6 to 9 in which the deposition of the layer (40) based on the semiconductor material is carried out by chemical vapor deposition or by atomic layer deposition.

11. A method according to any one of claims 6 to 10 wherein the semiconductor material is a two-dimensional (2D) material selected from transition metal dichalcogenides MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S), selenium (Se) or tellurium (Te).

12. Method according to any one of claims 5 to 11 in which the first layers (10) of the stack (E) are only in contact with the second layers (20) and in which the third layers (30) of the stack (E) are only in contact with the second layers (20).

13. Method according to any one of claims 6 to 12 in which the deposition of the layer (40) based on the semiconductor material is configured so that the layer (40) based on the semiconductor material completely fills the second spaces (21).

14. Method according to any one of claims 6 to 12 in which the deposition of the layer (40) based on the semiconductor material is configured so that the layer (40) based on the semiconductor material partially fills the second spaces (21), said method further comprising, after deposition of the layer (40) based on the semiconductor material, a deposition of an additional dielectric layer configured to fill the second spaces (21).

15. A method according to any one of claims 5 to 14 wherein the first openings (100) are formed along a longitudinal direction (x) and the second openings (200) are formed along a transverse direction (y) perpendicular to the longitudinal direction (x), said first and second openings (100, 200) extending to the substrate (S).

Images