Device for monitoring one or more power supplies

Abstract

Device for monitoring one or more power supplies The present description relates to a circuit (2000) comprising first, second and third nodes (2002, 2004, 2006) respectively receiving a reference potential (GND), a first voltage (V1) and a second voltage (V2). A first NMOS transistor (MN1) has its gate connected to the second node. A second NMOS transistor (MN2) has its drain and its source connected respectively to the source of the first transistor (MN1) and to the second node. A third NMOS transistor (MN3) has its gate and its source connected respectively to the second and first nodes. A fourth PMOS transistor (MP3) has its drain connected to the drain of the third transistor (MN3) and to the gate of the second transistor (MN2), and its gate connected to the source of the first transistor (MN1).A resistive element (2008) connects the first transistor (MN1) to the third node, another resistive element (2010) connects the fourth transistor (MP3) to the third node. Figure for abstract: Fig. 2.

Description

Title of the invention: Device for monitoring one or more power supplies Technical field

[0001] The present description relates generally to the monitoring of one or more supply voltages, and, more particularly, to power-on reset (POR) strategies. Prior art

[0002] Known chips increasingly often comprise several supply voltage domains and / or portions of the chip with circuits using several supply voltages.

[0003] When a supply voltage is off, it is in a high impedance state. When it is on, or powered up, this supply voltage initially has a zero value before reaching its nominal or target value following a power-up phase. When powering up and ramping up one or more supply voltages of a portion of the chip, many problems arise in the circuits that receive this or these supply voltages to be powered.

[0004] Known circuits generate, when one or more supply voltages increase in power, a reset signal which makes it possible to put the circuits to be supplied with this or these supply voltages in a known initial state.

[0005] However, these known power-up reset circuits have many drawbacks. Summary of the invention

[0006] There is a need for a power-up reset circuit that overcomes some or all of the disadvantages of known power-up reset circuits.

[0007] For example, there is a need for a power-on reset circuit that consumes less power than known power-on reset circuits.

[0008] For example, there is a need for a power-up reset device that is independent of the ramp-up sequence of the supply voltages it monitors.

[0009] For example, there is a need for a power-up reset device that provides a reset signal having a defined state as soon as one of the supply voltages monitored by the device is turned on and is no longer in a high impedance state.

[0010] For example, there is a need for a power-up reset device that allows implementation with MOS (Metal Oxide Semiconductor) transistors having a voltage withstand limit Vmax while one of the supply voltages monitored by this device has a nominal value higher than this voltage withstand Vmax and / or the difference in values between two of the voltages monitored by the device may be greater than this voltage withstand Vmax.

[0011] One embodiment overcomes all or part of the drawbacks of known power-up reset circuits and devices.

[0012] One embodiment provides a circuit comprising: a first node configured to receive a reference potential; a second node configured to receive a first DC voltage, the first DC voltage being a supply voltage; a third node configured to receive a second direct voltage; a first NMOS transistor having its gate connected to the second node; a second NMOS transistor having its drain connected to the source of the first transistor and its source connected to the second node; a third NMOS transistor having its gate connected to the second node and its source connected to the first node; a fourth PMOS transistor having its drain connected to the drain of the third transistor and to the gate of the second transistor, and its gate connected to the source of the first transistor; a first resistive element connected between the drain of the first transistor and the third node; a second resistive element connected between the source of the fourth transistor and the third node; and a first CMOS inverter configured to be powered by the second voltage, an input of the first inverter being connected to the drain of the third transistor and an output of the first inverter being configured to provide a reset signal.

[0013] According to one embodiment, each of the first and second resistive elements is implemented by a PMOS transistor having its gate connected to the first node and its source connected to the third node.

[0014] According to one embodiment, the circuit further comprises a capacitive element connected between the gate and the source of the first transistor.

[0015] According to one embodiment, the circuit further comprises a second CMOS inverter configured to be powered by the second voltage, an input of the second inverter being connected to the output of the first inverter, and an output of the second inverter being configured to provide a signal complementary to the reset signal.

[0016] According to one embodiment, the first and second resistive elements, and the first and fourth transistors are sized so that the fourth transistor is blocked when the first transistor is on.

[0017] According to one embodiment, the second voltage is also a supply voltage.

[0018] Another embodiment provides a device comprising: at least two circuits as described above; and a CMOS logic gate configured to implement a Boolean AND logic function between the reset signals provided by said at least two circuits, in which: the first nodes of said at least two circuits are configured to receive the same reference potential; the third nodes of said at least two circuits are configured to receive the same second voltage, said second voltage being a reference voltage; and the second nodes of said at least two circuits are each configured to receive a first direct current supply voltage different from the first voltages received by the second nodes of the other circuits.

[0019] According to one embodiment, the CMOS logic gate is configured to be powered by the second voltage.

[0020] According to one embodiment, the device further comprises a voltage generation circuit configured to provide the second reference DC voltage.

[0021] According to one embodiment, the voltage generation circuit is configured to provide the second reference DC voltage at its nominal value before a power-up and a power-up of each of the first voltages.

[0022] According to one embodiment, the circuit for generating the second reference voltage comprises: a first voltage divider bridge connected between a first supply node configured to receive one of the first DC supply voltages and a second supply node configured to receive the reference potential; a first MOS transistor and a second resistive voltage divider bridge connected in series between the first and second supply nodes, the first transistor having its gate connected to an intermediate node of the first bridge and its source connected to the second supply node; a first buffer circuit configured to be powered by said first voltage continuous supply and comprising an input connected to a first intermediate node of the second bridge and an output configured to provide the second reference voltage; and a second MOS transistor having its drain connected to the output of the first buffer circuit and its source connected to the first power supply node, wherein the first bridge is configured so that the first transistor is blocked when said one of the first direct supply voltages is at a value lower than a first threshold itself lower than a voltage withstand limit of the transistors, and wherein the second transistor is configured to be in the on state if the first transistor is in the off state and vice versa.

[0023] According to one embodiment, the circuit for generating the second reference voltage comprises: a first voltage divider bridge connected between a first supply node configured to receive one of the first DC supply voltages and a second supply node configured to receive the reference potential; a first MOS transistor and a second resistive voltage divider bridge connected in series between the first and second supply nodes, the first transistor having its gate connected to an intermediate node of the first bridge and its source connected to the first supply node; a second MOS transistor and a third resistive voltage divider bridge connected in series between the first and second supply nodes, the source of the second MOS transistor being connected to the second supply node; a buffer circuit configured to be powered by said one of the first DC supply voltages and comprising an input connected to a first intermediate node of the third bridge and an output configured to provide the second reference voltage; and a third MOS transistor having its drain connected to the output of the buffer circuit and its source connected to the first power supply node; wherein the second transistor is configured to be in the off state, respectively on state, when the first transistor is in the off state, respectively on state, wherein the third transistor is configured to be in the on state if the second transistor is in the off state and vice versa, and wherein the first bridge is configured so that the first transistor is blocked when said one of the first direct supply voltages is at a value lower than a first threshold itself lower than a voltage withstand limit of the transistors. Brief description of the drawings

[0024] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0025] [Fig.l] shows an example of a power-up reset circuit;

[0026] [Fig.2] shows an embodiment of a power-up reset circuit;

[0027] [Fig.3] shows an embodiment of a power-up reset device;

[0028] [Fig.4] represents, schematically and in the form of blocks, an example of an electronic system comprising a reference voltage generation circuit according to one embodiment;

[0029] [Fig.5] illustrates, in circuit form, an embodiment of the reference voltage generation circuit of [Fig.4];

[0030] [Fig.6] illustrates, in the form of a circuit, an exemplary embodiment of the reference voltage generation circuit of [Fig.4];

[0031] [Fig.7] represents, in the form of a circuit, an alternative embodiment of the circuit of [Fig.5];

[0032] [Fig.8] represents, in the form of a circuit, an alternative embodiment of the circuit of [Fig.6];

[0033] [Fig.9] represents, in circuit form, an exemplary embodiment of an analog buffer circuit; and

[0034] [Fig. 10] shows, in circuit form, an example of another embodiment of an analog buffer circuit Description of the embodiments

[0035] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0036] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0037] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0038] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0039] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0040] [Fig.l] shows an example of a power-up reset circuit 1000.

[0041] In this example, the circuit 1000 is configured to provide a reset signal POR to a low binary state corresponding, for example, to a zero voltage when a circuit to be supplied with two supply voltages VDDE and VDD must be reset, and to a high binary state corresponding, for example, to a voltage of value equal to the nominal value of the voltage VDEE when the rise in power of the two voltages VDDE and VDD is complete, i.e. when these two voltages VDDE and VDD have reached their respective nominal values. Thus, the low state of the signal POR causes the reset of the circuit to be supplied with the voltages VDD and VDDE and this reset phase ends when all the voltages have completed their rise in power and the signal POR switches to the high state.

[0042] The circuit 1000 is powered by the voltage VDDE or VDD which has the highest nominal value, namely VDDE in this example. Thus, the circuit 1000 comprises a node (or rail) 1004 configured to receive the voltage VDDE, and a node (or rail) 1006 configured to receive a reference potential GND, for example ground.

[0043] The circuit 1000 comprises a logic gate 1002 implemented in CMOS (Complementary MOS) technology, i.e. a CMOS logic gate 1002. The gate 1002 is powered by the voltage 1002.

[0044] Gate 1002 is configured to implement a Boolean logic function NAND between voltages VDDE and VDD, these voltages VDDE and VDD being provided to respective inputs of gate 1002. Logic gate 1002 provides the result of this Boolean logic operation on an output node 1008 of gate 1002.

[0045] Gate 1002 comprises as many PI PMOS transistors as it has inputs, i.e. two PI transistors in this example. The PI transistors are connected in parallel between nodes 1004 and 1008. Each PI transistor has its gate connected to a different input of gate 1002. For example, a first PI transistor has its gate connected to voltage VDD, or, in other words, has its gate configured to receive voltage VDD, and a second PI transistor has its gate connected to voltage VDDE or, in other words, has its gate configured to receive voltage VDDE.

[0046] Furthermore, gate 1002 includes as many NMOS NI transistors as it has inputs, i.e., two NI transistors in this example. The NI transistors are connected in series between nodes 1008 and 1006. Each NI transistor has its gate connected to a different input of gate 1002. For example, a first NI transistor has its gate connected to voltage VDD, and a second NI transistor has its gate connected to voltage VDDE.

[0047] The circuit 1000 further comprises an inverter INV1. The inverter INV1 is powered by the voltage VDDE. The inverter has an input connected to the output node 1008 of the gate 1002 and an output 1010 configured to provide the signal POR.

[0048] The inverter INV1 is implemented in CMOS technology. More particularly, the inverter INV1 comprises a PMOS transistor P2 connected between the node 1004 and the output 1010 and having its gate connected to the node 1008, and an NMOS transistor N2 connected between the output 1010 and the node 1006 and having its gate connected to the node 1008.

[0049] In this example, the circuit 1000 further comprises an inverter INV2. The inverter INV2 is powered by the voltage VDDE. The inverter INV2 is implemented in CMOS technology. The inverter INV2 has an input connected to the output 1010 of the inverter INV1, and an output 1012 configured to provide an nPOR signal complementary to the POR signal. More particularly, the inverter INV2 comprises a PMOS transistor P3 connected between the node 1004 and the output 1012 and having its gate connected to the node 1010, and an NMOS transistor N3 connected between the output 1012 and the node 1006 having its gate connected to the node 1010.

[0050] Although an example of a circuit 1000 monitoring the rise in power of two supply voltages VDDE and VDD has been described here, the person skilled in the art is able to adapt this example to the case where the circuit 1000 monitors the rise in power of more than two supply voltages, by increasing the number of inputs of the gate 1002.

[0051] The circuit 1000 only detects the rise in power of the supply voltage VDDE or VDD that it monitors which occurs last.

[0052] If all the supply voltages monitored by the circuit 1000 have finished their power increases, then all the NI transistors are on, the output 1008 of the gate 1002 is pulled to the GND potential, or, in other words, a zero voltage is present on the node 1008, and the POR signal is in a high state corresponding to the supply voltage VDDE of the circuit 1000.

[0053] If all the supply voltages monitored by the circuit 1000 have finished their power increases with the exception of at least one of the monitored supply voltages which is still at a zero value and which is not the supply voltage of the circuit 1000, then the output 1008 is pulled to the supply voltage VDDE, and the signal POR is in a low state corresponding to zero voltage.

[0054] On the other hand, as long as the voltage VDDE is absent, that is to say in a high impedance state, then the output 1008 is in a high impedance state, just like the signal POR.

[0055] Having a POR signal in an undefined state while certain power supplies monitored by the circuit 100 have already finished their power ramp-ups is not desirable. Indeed, this can lead to having floating nodes in the circuit to be powered with the monitored power supply voltages and receiving the POR signal. However, when the circuit to be powered has floating nodes and has already received power supply voltages that have finished their power ramp-ups, this can lead to malfunctions or destruction of the circuit to be powered.

[0056] To prevent the POR signal from being in an undefined state while one of the voltages monitored by the circuit 1000 has finished its power rise, for example when the voltage VDD has reached its nominal value while the voltage VDDE is absent, it has been proposed to impose a switching-on sequence for the monitored supply voltages, for example to impose that the voltage VDDE be supplied before the voltage VDD. However, imposing a switching-on sequence for the supply voltages is not always possible and, more generally, it is desirable not to impose such a switching-on sequence.

[0057] Furthermore, when the difference between the value of the voltage VDDE and the value of at least one other of the monitored voltages can take, during the power-up and increase in power of these two supply voltages, values greater than the voltage withstand Vmax of the MOS transistors in a given technology, then the circuit 1000 cannot be implemented in this technology.

[0058] Furthermore, in the circuit 1000, at the end of the ramp-up of all the supply voltages that it monitors, if one of the monitored voltages, for example the voltage VDD, has a different and lower nominal value than that of the voltage VDDE, then the circuit consumes energy which is proportional to the difference between these nominal values, which is not desirable.

[0059] By way of example, the circuit 1000 is therefore not suitable for use as a power-up reset circuit for an RRAM (Resistive Random Access Memory) type memory powered by the voltages VDD and VDDE having, for example, nominal values respectively substantially equal to 1.8 V and 3.3 V.

[0060] Although an exemplary power-up reset strategy and an exemplary circuit 1000 implementing that strategy have been described herein, other known power-up reset strategies and known circuits implementing them suffer from similar drawbacks.

[0061] For example, known power-up reset strategies and known circuits implementing them require an imposed sequence of switching on the supply voltages that they monitor so that the POR signal that they provide to a circuit to be supplied with these monitored supply voltages is not in an undefined state while at least one of the monitored voltages has already finished its power rise.

[0062] For example, known power-up reset strategies and known circuits implementing them cannot be implemented in given technologies for which the voltage withstand of the transistors is lower than values taken by the difference between two of the voltages monitored during power-up and the increase in power of the latter, for example the two voltages VDD and VDDE in the circuit 1000 previously described.

[0063] For example, known circuits implementing known power-up reset strategies exhibit significant non-zero static power consumption when the monitored voltages have finished ramping up and at least two of the monitored voltages have different nominal values.

[0064] Another example of a power-up reset circuit (not illustrated by a figure) is implemented from a dual-supply NAND gate. In other words, this other reset circuit comprises a NAND gate similar to gate 1002 of [Fig.l], except that the source of the PI transistor receiving the voltage VDDE on its gate is connected to a node receiving the voltage VDD, and not to node 1004 as in [Fig.l]. This other circuit preferably comprises the inverter INV1 connected to the output of the NAND gate, and preferably the inverter INV2 connected to the output of the inverter INV1.

[0065] In this other circuit not shown, if the voltage VDDE has finished its rise in power while the voltage VDD is zero, the output of the NAND gate is pulled to the voltage VDDE by the PI transistor controlled by the voltage VDD, and, conversely, if the voltage VDD has finished its rise in power while the voltage VDDE is zero, the output of the NAND gate is pulled to the voltage VDD by the PI transistor controlled by the voltage VDDE. Thus, the output signal POR of the inverter INV 1 is in the low state.

[0066] Still in this other circuit not illustrated, if the voltage VDDE, respectively VDD, is absent, or, in other words, in a high impedance state, while the voltage VDD, respectively VDDE, has finished its rise in power, then the output of the dual-supply NAND gate is in a high impedance state, from which it follows, for example, that the output signal POR of the inverter INV 1 is also in a high impedance state.

[0067] Although this alternative circuit has advantages over circuit 1000, it is difficult to adapt this alternative power-on reset circuit to examples where more than two supply voltages are monitored. Furthermore, this alternative power-on reset circuit initialization at power-up has at least some of the disadvantages of circuit 1000, such as for example a static consumption at the end of the power rise of the voltages VDDE and VDD which is proportional to the difference between these two voltages.

[0068] [Fig.2] shows an embodiment of a power-up reset circuit 2000.

[0069] The circuit 2000 comprises a node 2002 configured to receive the reference potential GND, a node 2004 configured to receive a first direct voltage VI, the first direct voltage being a supply voltage monitored by the circuit 2000, and a node 2006 to receive another direct voltage V2.

[0070] Circuit 2000 comprises an NMOS transistor MN1. Transistor MN1 has its gate connected to node 2004. Circuit 2000 comprises an NMOS transistor MN2. The drain of transistor MN2 is connected to the source of transistor MN1 and the source of transistor MN2 is connected to node 2004. Circuit 2000 comprises an NMOS transistor MN3. The gate of transistor MN3 is connected to node 2004 and the source of transistor MN3 is connected to node 2002. Circuit 2000 comprises a PMOS transistor MP3. The drain of transistor MP3 is connected to the drain of transistor MN3, the drain of transistor MN3 being connected to the gate of transistor MN2. The gate of transistor MP3 is connected to the source of transistor MN1.

[0071] Further, circuit 2000 includes a resistive element 2008 connected between the drain of transistor MN1 and node 2006. For example, resistive element 2008 has one terminal connected to the drain of transistor MN1 and one terminal connected to node 2006. Circuit 2000 also includes a resistive element 2010 connected between the source of transistor MP3 and node 2006. For example, resistive element 2010 has one terminal connected to the source of transistor MP3 and one terminal connected to node 2006.

[0072] The circuit 2000 comprises an inverter INV3 implemented in CMOS technology. The inverter INV3 is powered by the voltage V2, and, more generally, the circuit 2000 is powered by the voltage 2000. An input of the inverter INV3 is connected to the drain of the transistor MP3, therefore to the drain of the transistor MN3 and to the gate of the transistor MN2. The output 2012 of the inverter INV3 is configured to provide a reset signal POR2000 upon power-up.

[0073] As an example, the inverter INV3 comprises a PMOS transistor P4 connected between the node 2006 and the output 2012 and having its gate connected to the drains of the transistors MP3 and MN3, and an NMOS transistor N4 connected between the output 1012 and the node 2002 and having its gate connected to the drains of the transistors MP3 and MN3.

[0074] According to one embodiment, the circuit 2000 comprises an optional capacitive element Ce connected between the gate and the source of the transistor MN1.

[0075] According to one embodiment, when the circuit 2000 is configured to supply, in addition to the circuit POR2000 on the output 2012 of the inverter INV3 which is also a output of circuit 2000, a signal nPOR2000 complementary to the signal POR2000, circuit 2000 includes an inverter INV4 implemented in CMOS technology. The inverter INV4 is powered by the voltage V2. An input of the inverter INV4 is connected to the output 2012 of the inverter INV3, and an output 2014 of the inverter INV4 is configured to provide the signal nPOR2000.

[0076] As an example, the inverter INV4 comprises a PMOS transistor P5 connected between the node 2006 and the output 2014 and having its gate at the output 2012, and an NMOS transistor N5 connected between the output 1014 and the node 2002 and having its gate connected to the output 2012.

[0077] According to one embodiment, each of the resistive elements 2008 and 2010 is implemented by a respective PMOS transistor having its gate connected to the node 2002 so as to receive the potential GND and its source connected to the node 2006. For example, the resistive element 2008 is implemented by a PMOS transistor MPI having its gate controlled by the potential GND, its source connected to the node 2006 and its drain connected to the drain of the transistor MN1, and the resistive element 2010 is implemented by a PMOS transistor MP2 having its gate controlled by the potential GND, its source connected to the node 2006 and its drain connected to the source of the transistor MP3.

[0078] An advantage of implementing the resistive elements 2008 and 2010 with the PMOS transistors MPI and MP2 rather than with resistors is that, for a similar footprint, the resistive elements will have larger resistance values, which makes it possible to reduce the static consumption of the circuit 2000 compared to the case where these resistive elements would have been implemented with resistors.

[0079] However, in alternative embodiments, the resistive elements 2008 and 2010 are implemented with resistors.

[0080] To illustrate the operation of the circuit 2000, the case where the ignition and the increase in power of the voltage V1 are subsequent to the increase in power of the voltage V2 is considered, as an example.

[0081] This is for example the case when the two voltages are DC supply voltages, for example the respective voltages VDD and VDDE, of a circuit to be supplied whose initialization is controlled by the low state of the signal POR2000, and that an ignition sequence is imposed on these voltages VI and V2 so that the voltage V2 has finished its rise in power before the ignition and the rise in power of the voltage VI.

[0082] This may also be the case, for example, when the voltage V2 is a reference voltage VrefH provided by a reference voltage generation circuit configured so that the voltage VrefH is stable and at its nominal value before and during the switching on and the ramping up of the voltage VI. This latter case occurs, for example, when the voltage V1 monitored by the circuit 2000 is a voltage supply of a circuit to be supplied receiving a reset signal on power-up determined by the signal POR2000 and that the voltage V2 (or VrefH) is not a supply voltage of this circuit and does not depend on the voltage V2. For example, the voltage V2 (or VrefH) can then be supplied by a bandgap circuit which is for example supplied by a supply voltage which is not switched off when the supply V1 is switched off and / or which finishes its power rise before the voltage VI is switched on.

[0083] Thus, as soon as the voltage V1 is switched on and is then at a zero value, the transistor MN1 is in the off state, just like the transistor MN3. By capacitive coupling between the source and the gate of the transistor MN1, either via the parasitic source-gate capacitance of the transistor MN1, or via the capacitive element Ce, the gate of the transistor MP3 receives a zero or almost zero voltage, and the transistor MP3 therefore switches to the on state. As a result, the inverter INV3 receives on its input a voltage substantially equal to the voltage V2 and the signal POR2000 is then in the low state corresponding to a zero or almost zero voltage.

[0084] Advantageously, as soon as voltage VI is switched on, signal POR2000 is therefore in a defined state, namely the low state.

[0085] Furthermore, because the voltage on the drain of the transistor MP3 is equal to the voltage V2 minus the voltage drops across the resistive element 2010 and the transistor MP3, the transistor MN2 is on and the gate of the transistor MP3 receives the zero voltage V1, which makes it possible to keep the transistor MP3 on.

[0086] Then, when the voltage VI increases, as long as the voltage V1 is too low to switch the transistor MN2 to the off state, the voltage on the gate of the transistor MP3 follows the increase in the voltage VI. At the same time, as soon as the voltage VI becomes sufficient for the transistor MN1 to switch to the on state and for the transistor MN3 to switch to the on state, on the one hand the voltage on the gate of the transistor MP3 then becomes equal to the voltage V2 minus the voltage drops across the resistive element 2008 and across the transistor MN1, and, on the other hand, the voltage on the gate of the transistor MN2 is pulled towards the potential GND. This results on the one hand in the transistor MP3 switching to the off state, and, on the other hand in the transistor MN2 switching to the off state.Furthermore, because the inverter INV3 receives a zero or almost zero voltage at its input, the signal POR2000 is then in its high state corresponding to a voltage substantially equal to the voltage V2 at its nominal value.

[0087] According to an embodiment corresponding to the operation described above, the transistor MP3 is configured to turn off when the transistor MN1 turns on, so as to reduce the static consumption of the circuit 2000. The resistive elements 2008 and 2010, and the transistors MN1 and MP3 are then sized so that the transistor MP3 turns off when the transistor MN1 turns on. For example, when the elements 2008 and 2010, for example the two transistors MPI and MP2, are identical, the transistor MP3 is sized so as to have, in absolute value, a threshold voltage value higher than that of the transistor MN1. For this, it is for example provided that the channel of the transistor MP3 is longer than that of the transistors MN1, MN2 and MN3 when the resistive elements MPI and MP2 are identical.

[0088] According to a more energy-consuming embodiment variant, during the rise in power of voltage VI, or even at the end of this rise in power, transistor MP3 can remain on while transistors MN1 and MN3 are on. However, even if both transistors MN3 and MP3 are on simultaneously, due to the voltage drop across resistive element 2010, the input of inverter INV3 will receive a voltage closer to a zero value than to the nominal value of voltage V2, and signal POR2000 will then be in its high state.

[0089] A case is considered as an example where: the voltage V1 corresponds to one of the supply voltages of a circuit to be supplied to which a reset signal must be supplied in a defined state as soon as one of its supply voltages is switched on, and the voltage V2 is a reference voltage VrefH having a non-zero value, preferably its nominal value, before switching on and ramping up each of the supply voltages of the circuit to be powered. In such a case, the circuit 2000 can only monitor one of the supply voltages of the circuit to be powered. To monitor all the supply voltages of the circuit to be powered, and to provide it with a reset signal PORres to a binary state, for example low, defined as soon as one of these supply voltages is switched on, and to another binary state, for example high, as soon as all these supply voltages have finished ramping up, a switch-on reset device is proposed comprising several circuits 2000, an exemplary embodiment of which will now be described in relation to [Fig.3].

[0090] [Fig.3] shows an embodiment of a power-up reset device 3000.

[0091] In this example, the device 3000 is configured to monitor the two supply voltages VDD and VDDE of a circuit to be supplied with these two supply voltages, and to provide, to this circuit to be supplied, an initialization signal PORres upon power-up which: either in the low state as soon as any of the monitored voltages VDDE and VDD is switched on and takes a zero value, and either in the high state as soon as all the monitored voltages VDDE and VDD have completed their power increases.

[0092] The device 3000 comprises as many circuits 2000 as it monitors voltage. supply voltages. Thus, in this example where the device 3000 monitors both voltages VDD and VDDE, the circuit 3000 comprises two circuits 2000. However, the person skilled in the art is able to adapt the description given for the case where the device 3000 monitors only the two voltages VDD and VDDE to the case where the device 3000 monitors more than three supply voltages.

[0093] The nodes, or inputs, 2006 of the circuits 2000 all receive the same reference DC voltage VrefH.

[0094] The nodes 2002 of the circuits 2000 all receive the same reference potential GND.

[0095] On the other hand, the nodes, or inputs, 2004 of the circuits 2000 each receive a supply voltage to be monitored which is part of the supply voltages monitored by the device 3000 and which is different from the supply voltages to be monitored received by the nodes 2004 of the other circuits 2000. Thus, in this example where the device 3000 monitors the two voltages VDD and VDDE, one of the two circuits 2000 (at the top in [Fig.3]) receives the voltage VDD on its node 2004, and the other of the two circuits 2000 (at the bottom in [Fig.3]) receives the voltage VDDE on its node 2004.

[0096] Furthermore, the device 3000 comprises a logic gate 3002 implemented in CMOS technology and powered by the reference voltage VrefH. More particularly, the logic gate 3002 implements a Boolean AND logic function between the POR2000 signals supplied by the circuits 2000. In the example of [Fig.3], the gate 3002 therefore comprises two inputs receiving the POR2000 signals from the two circuits 2000. The gate output 3002 provides the PORres initialization signal upon power-up which will be supplied to the circuit to be powered with the voltages VDD and VDDE that the device 3000 monitors.

[0097] As an example not illustrated, the logic gate 3002 comprises, to implement the AND function: - PMOS transistors assembled in parallel between a node at voltage VrefH and an intermediate node of gate 3002, and each having a gate connected to a corresponding input of the gate; - NMOS transistors assembled in series between the intermediate node and a node at GND potential, and each having a gate connected to a corresponding input of the gate; and - an inverter powered by the voltage VrefH, having an input connected to the intermediate node and an output corresponding to the output of the gate.

[0098] Although not shown, according to one embodiment, the device 3000 comprises a reference voltage generation circuit configured to provide the reference voltage VrefH.

[0099] According to one embodiment, the reference voltage generation circuit is configured to provide the reference DC voltage VrefH at its nominal value before a power-up and a ramp-up of each of the voltages VDD and VDDE monitored by the device 3000. For example, the reference voltage generation circuit is a band-hopping type circuit.

[0100] Thus, as soon as one of the voltages VDDE and VDD is powered up (or switched on), even if this voltage has a zero value and the other of the voltages VDDE and VDD is in a high impedance state, because the voltage VrefH is supplied to the circuits 2000, the circuit 2000 receiving on its node 2004 the voltage which has just been switched on will supply a POR2000 signal in the low state. The low state of at least one POR2000 signal causes the PORres signal to be in the low state. Then, as long as all the voltages VDDE and VDD have not finished their power increases, the PORres signal remains in its low state. Finally, once all the monitored voltages VDD and VDDE have finished their power increases, the POR2000 signals are all in their high state, from which it follows that the PORres signal is in the high state.

[0101] The device 3000 therefore makes it possible to monitor the voltages VDDE and VDD and to provide an initialization signal PORres upon power-up which is in a defined low state as soon as one of the voltages VDDE and VDD is switched on, and which then switches to its high state only when all the monitored voltages VDD and VDDE have finished their power increases, which was not the case with the circuit 1000 of [Fig.l]. The signal PORres is then independent of the sequence in which the monitored voltages are switched on and increase in power.

[0102] In another embodiment, the circuit to be supplied with the voltages VDDE and VDD comprises cascode structures each being supplied by the voltage VDDE, and each comprising a transistor having its gate biased by the voltage VrefH and a transistor having its gate controlled by a binary signal. In this case, the circuit for generating the voltage VrefH is configured so that the voltage VrefH allows an implementation of the cascode structures with transistors whose voltage withstand Vmax is lower than values that the difference between the voltages VDDE and VDD can take while the ignition sequence of the voltages VDDE and VDD is not imposed. In this other embodiment, the voltage VrefH for biasing the cascode structures can advantageously serve as voltage VrefH for the circuits 2000 previously.

[0103] Embodiments and variants of such a circuit for generating a reference voltage have been described in French patent application FR2304777 filed on May 15, 2023, and will be described below in relation to figures 4 to 10 corresponding to the respective figures 1 to 7 of the aforementioned application.

[0104] [Fig.4] represents, schematically and in the form of blocks, an example of an electronic system 1 comprising a REFGEN device for generating a reference voltage according to one embodiment.

[0105] More particularly, the system 1, corresponding for example to a portion of an integrated circuit chip, comprises an IP device, for example a resistive memory, and the REFGEN device.

[0106] The IP device is powered by the supply voltage VDDE, for example available on a connection pad of the chip. For example, the voltage VDDE has a nominal value substantially equal to 3.3 V. The IP device comprises a terminal configured to receive the voltage VDDE, and another terminal configured to receive the reference potential GND, for example the ground, to which the voltage VDDE is referenced.

[0107] The IP device comprises MOS transistor cascode structures. For example, the IP device comprises N-channel MOS transistor cascode structures 100 and / or P-channel MOS transistor cascode structures 102.

[0108] By way of example, each structure 100 comprises two N-channel MOS transistors T1 and T2 connected in series between a node 104 receiving the voltage VDDE and a node 106 receiving the potential GND. The transistor T1 has its source connected to the node 106 and its drain connected to the source of the transistor T2, the source of the transistor T2 being coupled to the node 104 by a load L. The gate of the transistor T2 is configured to receive the reference or bias voltage VrefH. The transistor T2 is, for example, called a cascode transistor. The gate of the transistor T1 is configured to receive a control voltage between 0 V and the bias voltage VrefH.

[0109] Symmetrically, for example, each structure 102 comprises two P-channel MOS transistors T3 and T4 connected in series between nodes 104 and 106. Transistor T2 has its source connected to node 104 and its drain connected to the source of transistor T2, the source of transistor T2 being coupled to node 106 by a load L. The gate of transistor T4 is configured to receive a reference voltage VrefL. Transistor T4 is, for example, called a cascode transistor. The gate of transistor T3 is configured to receive a control voltage between the reference voltage VrefL and the supply voltage VDDE.

[0110] In the remainder of the description, Vmax is the maximum voltage that can be applied between the gate and the source or between the source and the drain of each of the transistors of the IP device without damaging the transistor. In other words, Vmax is the voltage withstand limit of the MOS transistors of the IP device.

[0111] Preferably, the voltages VrefL and VrefH have different values. For example, To optimize the operation of the N-channel and P-channel transistors of the IP device, the voltage VrefL is chosen to be equal to the voltage VDEE minus the voltage VrefH. However, in other examples, the voltages VrefL and VrefH have the same value.

[0112] The voltages VrefH and VrefL are received by the IP device.

[0113] The REFGEN device is configured to provide the voltages VrefL and VrefH. The REFGEN device is powered by the voltage VDDE. The REFGEN device has, for example, a terminal receiving the voltage VDDE, and another terminal receiving the reference potential GND.

[0114] According to one embodiment, the REFGEN device is further configured to receive a supply voltage VDD and a binary signal EN-S.

[0115] The voltage VDD has a lower nominal value than that of the voltage VDDE. In particular, the voltage VDD is lower than the voltage withstand limit Vmax. For example, the result of subtracting the nominal value of the voltage VDD from that of the voltage VDDE is lower than the voltage withstand limit of the transistors T1, T2, T3 and T4 of the device IP. For example, the voltage VDD is a voltage generated by a circuit (not shown) of the integrated circuit chip comprising the system 1.

[0116] The EN-S signal is a binary signal whose low level corresponds to a zero voltage, and whose high level corresponds to the voltage VDD. The EN-S signal is configured to be at its low level by default. The EN-S signal is further configured to be at its low level when the current value of the voltage VDDE is greater than the voltage Vmax. When the current value of the voltage VDDE is less than the voltage Vmax, the level of the EN-S signal is determined by a control signal cmd. For example, setting the EN-S signal with the cmd signal when the voltage VDDE is less than the voltage Vmax corresponds to a low-power operating mode where the voltage VDDE is at a current value lower than its nominal value, for example a current value equal to the nominal value of the voltage VDD.

[0117] By way of example, the system 1 comprises a circuit 108 configured to receive the voltages VDDE and VDD, the potential GND and the signal cmd, and to provide the signal EN-S. The implementation of such a circuit 108, and, more generally, the generation of the signal EN-S, are within the reach of the person skilled in the art.

[0118] In an alternative embodiment, the REFGEN circuit does not receive the EN-S signal and the VDD voltage.

[0119] In the example of [Fig.4], the IP device comprises structures 100 and 102, and the REFGEN device therefore provides the two voltages VrefH and VrefL. In other examples, the IP device does not comprise structure 100 and the REFGEN device then only provides the voltage VrefL, or, conversely, the IP device does not comprise structure 102 and the REFGEN device then only provides the voltage VrefH.

[0120] [Fig.5] illustrates, in circuit form, an embodiment of the REFGEN circuit of [Fig.4]. In this embodiment, the REFGEN device is configured to provide only the voltage VrefH.

[0121] According to one embodiment, this REFGEN device provides the voltage VrefH to each circuit 2000 previously described and is part of the device 3000. Furthermore, the REFGEN device can be used to provide the voltage VrefH to the circuits 2000 described previously whether or not it is used to provide the voltage VrefH to the circuit IP.

[0122] The REFGEN device comprises a voltage divider bridge 200. The bridge 200 is connected between a node 202 configured to receive the VDDE voltage, and a node 204 configured to receive the GND potential. For example, the bridge 200 has one end connected to the node 202 and one end connected to the node 204.

[0123] According to one embodiment, the bridge 200 comprises one or more P-channel MOS transistors connected in series between the node 202 and an intermediate node 206 of the bridge 200. Each of these P-channel transistors is connected as a diode, or, in other words, has its drain connected to its gate. Each of these P-channel transistors has its source on the side of the node 202. In [Fig. 5], these P-channel transistors are represented in the form of a single P-channel MOS transistor, DI. Symmetrically, the bridge 200 comprises one or more N-channel MOS transistors connected in series between the node 206 and the node 204. Each of these N-channel transistors is connected as a diode, or, in other words, has its drain connected to its gate. Each of these N-channel transistors has its source on the node 204 side. In [Fig.5], these N-channel transistors are represented as a single N-channel MOS transistor, D2.

[0124] According to an alternative embodiment, the P-channel MOS transistors of the bridge 200 are replaced by diodes, for example diodes having their anodes on the side of the node 202, and the N-channel MOS transistors of the bridge 200 are also replaced by diodes, for example diodes having their anodes on the side of the node 206.

[0125] According to another alternative embodiment, the P-channel transistors of the bridge 200 are replaced by a resistive element comprising one or more resistors in series between the nodes 202 and 206, and the N-channel transistors of the bridge 200 are replaced by another resistive element comprising one or more resistors in series between the nodes 206 and 204.

[0126] The REFGEN device comprises a MOS transistor Ten and a resistive voltage divider bridge 208, the transistor Ten and the bridge 208 being connected in series between the nodes 202 and 204.

[0127] Transistor Ten has its gate connected to node 206 on which a voltage EN is available. The source of transistor Ten is connected to node 204 in the embodiment of [Fig.5]. In the embodiment of [Fig.5], transistor Ten is N-channel.

[0128] The divider bridge 208 has one end 210 connected to the drain of the transistor Ten. The divider bridge 208 has another end 212 connected to the node 202 in the mode of realization of [Fig.5].

[0129] The bridge 208 comprises, for example, at least three resistive elements RI, R2 and R3. Each resistive element RI, R2, R3 of the bridge 208 may correspond to a single resistor or to a series and / or parallel association of several resistors. For example, the element RI is connected between the end 212 and an intermediate node 214 of the bridge 208, the element R2 is connected between the node 214 and another intermediate node 216 of the bridge 208, and the element R3 is connected between the node 216 and the end 210 of the bridge.

[0130] The REFGEN device comprises a buffer circuit BUFFal. The BUFFal circuit is powered by the voltage VDDE. For example, the BUFFal circuit has a terminal connected to node 202 and a terminal connected to node 204.

[0131] The BUFFal circuit is an analog buffer circuit. In other words, the BUFFal circuit is configured to provide on its output 218 a voltage having a value identical to that of a voltage that it receives on its input 220, while ensuring isolation between its input and its output. In other words, the BUFFal circuit is a unity gain follower circuit.

[0132] Input 218 of the BUFFal circuit is connected to an intermediate node of the bridge 208, for example to node 214. Output 220 of the BUFFal circuit provides the voltage VrefH.

[0133] The REFGEN device further comprises a MOS transistor Toi. The drain of the transistor Toi is connected to the output of the BUFFal circuit. The source of the transistor Toi is connected to the node 202 in the embodiment of [Fig.5] where the REFGEN device is configured to provide the voltage VrefH. In the embodiment of [Fig.5], the transistor Toi is P-channel.

[0134] Transistor Toi is configured to be in the on state when transistor Ten is in the off state, and to be in the off state when transistor Ten is in the on state. More particularly, transistor Toi is configured so that its on or off state is determined by a voltage value on an intermediate node of the divider bridge 208, for example on node 216 of the bridge 208.

[0135] In the example of [Fig.5], the REFGEN device comprises a P-channel MOS transistor T5 and a resistive element R4 in series between nodes 202 and 204. Transistor T5 has its gate connected to node 216 of bridge 208, its source connected to the same node 202 as the source of transistor Toi, and its drain coupled to node 204 by element R4. The gate of transistor Toi is connected to the drain of transistor T5.

[0136] In the REFGEN circuit, the divider bridge 200 is configured so that the transistor Ten is in the off state if the voltage VDDE is lower than a threshold VT1, for example substantially equal to 0.9 V. Preferably, the threshold VT1 is lower than the voltage Vmax. Conversely, the divider bridge 200 is configured so that the transistor Ten is on if the voltage VDDE is higher than the threshold VT1. More particularly, the divider bridge 200 is configured to have the above operation when taken alone, that is to say when no circuit comes to directly modify the potential of node 206, for example by pulling this node 206 to GND or VDDE.

[0137] Thus, when the bridge 200 is taken alone and the voltage VDDE is lower than the threshold VT1, the voltage EN is lower than the threshold of the transistor Ten which is then in the off state. This results in the node 216 being at the voltage VDDE, and therefore the transistor T5 being in the off state. The off state of the transistor T5 causes the gate of the transistor Toi to receive the potential GND and therefore the transistor Toi is in the on state. The output 218, therefore the voltage VrefH, is then pulled to the voltage VDDE. In other words, as long as the voltage VDDE is lower than the threshold VT1, the voltage VrefH follows the voltage VDDE. Conversely, when bridge 200 is taken alone and voltage VDDE is greater than or equal to threshold VT1, voltage EN is sufficient for transistor Ten to be on, resulting in transistor T5 becoming on, this on state of transistor T5 forcing transistor Toi to the off state.The voltage VrefH is then equal to the voltage on the input 220 of the BUFFal circuit. For example, the divider bridge 208 is configured so that, when the transistor Ten is on, the voltage on the input 220 of the BUFFal circuit is equal to 0.55 times the voltage VDDE when the output 218 of the BUFFal circuit provides the voltage VrefH.

[0138] In one embodiment (not shown), the REFGEN circuit does not receive the EN-S signal and the VDD voltage.

[0139] In another embodiment, as illustrated by [Fig. 5], the REFGEN device receives the EN-S signal and the VDD voltage. The REFGEN device then comprises a circuit 222 configured to receive the EN-S signal and to pull, only when the EN-S signal is at its high level, the node 206 to that of the GND potential and the VDDE voltage which puts the transistor Ten in the off state when it is applied to the gate of the transistor. In the embodiment of [Fig. 5] where the transistor Ten is N-channel and has its source connected to the node 204, the circuit 222 is configured to pull the node 206 to the node 204 when the EN-S signal is at its high level.

[0140] When the voltage VDDE is lower than Vmax and the signal cmd controls the high level of the signal EN-S, the provision of the circuit 222 allows the voltage VrefH to be equal to the voltage of the node 202 to which the source of the transistor Toi is connected. For example, such operation allows that, in a low power supply mode where the voltage VDDE is at a low value compared to its nominal value and lower than the voltage Vmax, for example a low value equal to the nominal value of the voltage VDD, the voltage VrefH is at a value allowing the operation of the cascode structures 100 of the device IP ([Fig.4]).

[0141] In the embodiment of [Fig.5], the circuit 222 comprises a buffer circuit BUFFnl and an N-channel MOS transistor T6. The circuit BUFFnl is powered by the voltage VDD. For example, circuit BUFFnl has one terminal connected to node 204 and one terminal connected to a node 224 configured to receive voltage VDD.

[0142] The BUFFnl circuit is a digital buffer circuit. The BUFFnl circuit is therefore configured to provide on its output 226 a digital signal at the high level (VDD) when its input 228 receives the high level of the EN-S signal, and at the low level (GND) when its input receives the low level (GND) of the EN-S signal, while ensuring isolation between its input and its output. As an example, the BUFFnl circuit comprises two inverters in series between its input 228 and its output 226.

[0143] Transistor T6 has its source connected to node 204, its gate connected to output 226 of circuit BUFFnl and its drain connected to node 206 of bridge 200.

[0144] An embodiment has been described above in relation to [Fig.5] where the REFGEN device is configured to provide the voltage VrefH, which implies that the transistor Toi has its source connected to the node 202.

[0145] In an alternative embodiment (not shown) of the REFGEN device, the device described in relation to [Fig. 5] is configured to generate the voltage VrefL and is then not used to supply the voltage VrefH to the circuits 2000. In this alternative, the transistor Toi is N-channel, and has its source connected to the node 204. In such an alternative, the transistor Toi remains controlled from a voltage on an intermediate node of the bridge 208, for example on the node 216, so as to be on when the transistor Ten is off, and to be off when the transistor Ten is on. In such an alternative, the gate of the transistor Toi is, for example, connected to the node 216, the transistor T5 and the resistive element R4 possibly being omitted.In such a variant, the voltage VrefL is then supplied on the output of the circuit BUFFal instead of the voltage VrefH, the voltage VrefL being zero as long as the transistor Ten is blocked and equal to the voltage on the node 214 when the transistor Ten is on. For example, when the output 218 of the circuit BUFFal supplies the voltage VrefL, the bridge 208 is configured so that the voltage on the node 214 is equal to 0.45 times the voltage VDDE when the transistor Ten is on.

[0146] The REFGEN device described in relation to [Fig.5] has the advantage of being able to be implemented with MOS transistors similar to those of the IP device, i.e. MOS transistors having a voltage withstand Vmax. Furthermore, by using the voltage VrefH as the voltage applied to the node 2006 of the circuits 2000, the latter can also be implemented with MOS transistors having a voltage withstand Vmax.

[0147] [Fig.6] illustrates, in circuit form, another exemplary embodiment of the REFGEN circuit of [Fig.4]. In this exemplary embodiment, the REFGEN device is configured to provide only the voltage VrefL, and is therefore not used to provide the voltage VrefH to the circuits 2000.

[0148] The REFGEN device of [Fig.6] includes many elements in common with that of [Fig.5], and only the differences between these two devices are highlighted here. In particular, unless otherwise indicated, everything that has been indicated for the REFGEN device described in relation to [Fig.5] applies to the REFGEN device of [Fig.6].

[0149] The REFGEN device comprises the voltage divider bridge 200, the resistive voltage divider bridge 208, the buffer circuit BUFFal, the transistor Ten and the transistor Toi.

[0150] Transistor Ten and bridge 208 are connected in series between nodes 202 and 204. However, unlike what has been described in relation to [Fig.5], in [Fig.6], transistor Ten is P-channel and has its source connected to node 202, the end 212 of the divider bridge 208 therefore being connected to node 204.

[0151] Furthermore, in the embodiment of [Fig.6], the output 218 of the buffer circuit BUFFal provides the voltage VrefL and not the voltage VrefH as in [Fig.5]. The input 218 of the circuit BUFFal is connected to an intermediate node of the bridge 208, for example to the node 214.

[0152] In the embodiment of [Fig.6] where the REFGEN device is configured to provide the voltage VrefL, the source of the transistor Toi is connected to the node 204 and the transistor Toi is N-channel. As in [Fig.5], in the REFGEN device of [Fig.6], the transistor Toi is configured to be in the on state when the transistor Ten is in the off state, and to be in the off state when the transistor Ten is in the on state. More particularly, the transistor Toi is configured so that its on or off state is determined by a voltage value on an intermediate node of the divider bridge 208, for example on the node 216 of the bridge 208.

[0153] In the example of [Fig.6], the REFGEN device comprises the MOS transistor T5 and the resistive element R4 in series between the nodes 202 and 204. However, compared to what has been described in relation to [Fig.5], in [Fig.6] the transistor T5 is N-channel and has its source connected to the node 204.

[0154] As in [Fig.5], in [Fig.6] the divider bridge 200 is configured so that the transistor Ten is in the off state if the voltage VDDE is lower than a threshold VT1, for example substantially equal to 0.9 V, and so that the transistor Ten is on if the voltage VDDE is higher than the threshold VT1. More particularly, the divider bridge 200 is configured to have the above operation when taken alone.

[0155] Thus, when the bridge 200 is taken alone and the voltage VDDE is lower than the threshold VT1, the difference between the voltages EN and VDDE is not sufficient for the transistor Ten to be on. The blocked state of the transistor Ten implies that the node 216 is at the potential GND from which it follows that the transistor T5 is in the blocked state and that the gate of the transistor Toi receives the voltage VDDE. The transistor Toi is then in the on state and the voltage VrefL is zero. Conversely, when the bridge 200 is taken alone and the voltage VDDE is greater than or equal to the threshold VT1, the difference between the voltages EN and VDDE is sufficient for the transistor Ten to be on, from which it follows that the transistor T5 becomes on which puts the transistor Toi in the off state. The voltage VrefL is then equal to the voltage on the input 220 of the circuit BUFFal. For example, when the output 218 of the circuit BUFFal provides the voltage VrefL, the bridge 208 is configured so that the voltage on the node 214 is equal to 0.45 times the voltage VDDE when the transistor Ten is on.

[0156] In one embodiment (not shown), the REFGEN circuit does not receive the EN-S signal and the VDD voltage.

[0157] In another embodiment, as illustrated by [Fig.6], the REFGEN device receives the EN-S signal and the VDD voltage. The REFGEN device then comprises the circuit 222 configured to receive the EN-S signal and to pull, when the EN-S signal is at its high level, the node 206 to that of the GND potential and the VDDE voltage which controls the blocked state of the transistor Ten. Thus, in the embodiment of [Fig.6] where the transistor Ten is P-channel and has its source connected to the node 202, the circuit 222 is configured to pull the node 206 to the node 202 when the EN-S signal is at its high level.

[0158] When the current value of the voltage VDDE is lower than Vmax and the signal cmd controls the high level of the signal EN-S, the provision of the circuit 222 allows the voltage VrefL to be equal to the voltage of the node 204 to which the source of the transistor Toi is connected. For example, such operation allows that, in a low power supply mode where the voltage VDDE is at a low value compared to its nominal value and lower than the voltage Vmax, the voltage VrefL is at a value allowing the operation of the cascode structures 102 of the device IP ([Fig.4]).

[0159] In the embodiment of [Fig.6], the circuit 222 comprises the buffer circuit BUFFnl and the MOS transistor T6. However, in this example, the transistor T6 is P-channel and has its source connected to the node 202, and its gate is not connected to the output of the circuit BUFFnl. The circuit 222 then further comprises an N-channel MOS transistor T7 and a voltage divider bridge 300 connected in series between the nodes 202 and 204. The bridge 300, preferably a resistive divider bridge, is connected between the node 202 and the transistor T7. The transistor T7 has its source connected to the node 204, its gate connected to the output of the circuit BUFFnl and its drain connected to the bridge 300. The gate of the transistor T6 is connected to an intermediate node 302 of the bridge 300.

[0160] In the implementation described here of the circuit 222, when the voltage VDDE is greater than the voltage Vmax and the signal EN-S is therefore at its low level, the transistor T7 then has a zero gate-source voltage but a drain-source voltage equal to the VDDE and therefore greater than the voltage withstand Vmax of the transistors of the device IP. Thus, the transistor T7 is chosen to be able to hold the voltage VDDE on its drain. For example, transistor T7 is an extended drain transistor.

[0161] The REFGEN device described in relation to [Fig.6] has the advantage of being able to be implemented with MOS transistors similar to those of the IP device, i.e. MOS transistors having a voltage withstand Vmax, except with regard to the transistor T7 which is sized to be able to withstand the voltage VDDE on its drain.

[0162] An embodiment has been described above in relation to [Fig.6] where the REFGEN device is configured to provide the voltage VrefL, which implies that the transistor Toi has its source connected to the node 204.

[0163] In an alternative embodiment, the device described in relation to [Fig.6] is configured to generate the voltage VrefH and can be used to supply the voltage VrefH to the circuits 2000. In this case, the transistor Toi is P-channel, and has its source connected to the node 202. In such an alternative embodiment, the transistor Toi remains controlled from a voltage on an intermediate node of the bridge 208, for example the node 216, so as to be on when the transistor Ten is off, and to be off when the transistor Ten is on. In such an alternative embodiment, the gate of the transistor Toi is, for example, connected to the node 216, the transistor T5 and the resistive element R4 possibly being omitted. In such a variant, the voltage VrefH is then supplied on the output of the circuit BUFFal instead of the voltage VrefL, the voltage VrefH following the voltage VDDE as long as the transistor Ten is blocked and being equal to the voltage on the node 214 when the transistor Ten is on.For example, when output 218 of circuit BUFFal provides voltage VrefH, bridge 208 is configured so that the voltage on node 214 is equal to 0.55 times voltage VDDE when transistor Ten is on.

[0164] According to one embodiment, this REFGEN device according to the variant described above in relation to [Fig.6] supplies the voltage VrefH to each circuit 2000 previously described and is part of the device 3000. Furthermore, the REFGEN device can be used to supply the voltage VrefH to the circuits 2000 described previously whether or not it is used to supply the voltage VrefH to the circuit IP.

[0165] [Fig.7] represents, in the form of a circuit, an alternative embodiment of the REFGEN circuit of [Fig.5]. Compared to the REFGEN circuit of [Fig.5] which is configured to provide the voltage VrefH, the REFGEN circuit of [Fig.7] is configured to generate the voltage VrefH and the voltage VrefL.

[0166] According to one embodiment, this REFGEN device provides the voltage VrefH to each circuit 2000 previously described and is part of the device 3000. Furthermore, the REFGEN device can be used to provide the voltage VrefH to the circuits 2000 described previously whether or not it is used to provide the voltage VrefH to the circuit IP.

[0167] The REFGEN device of [Fig.7] includes many elements in common with that of [Fig.5], and only the differences between these two devices are highlighted here. In particular, unless otherwise indicated, everything that has been indicated for the REFGEN device described in relation to [Fig.5] applies to the REFGEN device of [Fig.7],

[0168] Compared to the REFGEN device of [Fig.5], the REFGEN device of [Fig.7] further comprises a resistive voltage divider bridge 400 and a MOS transistor T8 in series between nodes 202 and 204.

[0169] The source of transistor T8 is connected to the one of nodes 202 and 204 to which the source of transistor Ten is not connected, i.e. to node 202 in the embodiment of [Fig.7]. In the embodiment of [Fig.7], transistor T8 is P-channel.

[0170] Transistor T8 is configured to be on, respectively off, when transistor Ten is on, respectively off. In the embodiment of [Fig.7], transistor T8 has its gate connected to an intermediate node of bridge 208, for example to node 216.

[0171] The divider bridge 400 has one end 402 connected to the drain of the transistor T8. The divider bridge 400 has another end 404 connected to the node 204 in the embodiment of [Fig.7].

[0172] The bridge 400 comprises, for example, at least three resistive elements R5, R6 and R7. Each resistive element R5, R6, R7 of the bridge 400 may correspond to a single resistor or to a series and / or parallel association of several resistors. For example, the element R5 is connected between the end 404 and an intermediate node 406 of the bridge 400, the element R6 is connected between the node 406 and another intermediate node 408 of the bridge 400, and the element R7 is connected between the node 408 and the end 402 of the bridge 400.

[0173] Compared to the REFGEN device of [Fig.5], the REFGEN device of [Fig.7] comprises a buffer circuit BUFFa2. The BUFFa2 circuit is powered by the voltage VDDE. For example, the BUFFa2 circuit has a terminal connected to node 202 and a terminal connected to node 204.

[0174] The BUFFa2 circuit is an analog buffer circuit. In other words, the BUFFa2 circuit is configured to provide on its output 410 a voltage having a value identical to that of a voltage that it receives on its input 412, while ensuring isolation between its input and its output. In other words, the BUFFa2 circuit is a unity gain follower circuit.

[0175] Input 412 of circuit BUFFa2 is connected to an intermediate node of bridge 400, for example to node 406. In the embodiment of [Fig.7], output 410 of circuit BUFFa2 provides voltage VrefL.

[0176] The REFGEN device further comprises a MOS transistor To2. The drain of the Transistor To2 is connected to the output of circuit BUFFa2. The source of transistor To2 is connected to node 204 in the embodiment of [Fig.7] where circuit BUFFa2 is configured to provide voltage VrefL. In other words, the source of transistor To2 and the source of transistor Toi are connected to respective different nodes among nodes 202 and 204. In the embodiment of [Fig.7], transistor To2 is N-channel.

[0177] Transistor To2 is configured to be in the on state when transistor T8 is in the off state, and to be in the off state when transistor T8 is in the on state.

[0178] More particularly, in the embodiment of [Fig.7], the transistor To2 is configured so that its on or off state is determined by a voltage value V2 on a node of the divider bridge 208, for example on the node 210 of the divider bridge 300, and the transistor Toi is configured so that its on or off state is by a voltage value V1 on a node of the divider bridge 400, for example on the node 402 of the bridge 400. The transistor Toi has its gate coupled, preferably connected, to the node 402, the transistor To2 having its gate connected, preferably connected, to the node 210.

[0179] In an alternative embodiment (not shown) the REFGEN device comprises a MOS transistor and a resistive element in series between nodes 202 and 204, identical to transistor T5 and element R4 of [Fig.5], and connected together, to bridge 208 and to transistor Toi in the same way as transistor T5 and element R4 in [Fig.5]. Transistor Toi is then not controlled by voltage VI of bridge 400. Compared to the embodiment illustrated in [Fig.7], this alternative is more bulky.

[0180] In another alternative embodiment, which can be combined with the above alternative embodiment, the REFGEN device comprises a MOS transistor and a resistive element in series between the nodes 202 and 204, identical to the transistor T5 and the element R4 of [Fig.6], and connected together, to the bridge 208 and to the transistor Toi in the same way as the transistor T5 and the element R4 in [Fig.6]. The transistor To2 is then not controlled by the voltage V2 of the bridge 208. Compared to the embodiment illustrated in [Fig.7], this alternative is more bulky.

[0181] In the embodiment of [Fig.7], the REFGEN device comprises the circuit 222 of [Fig.4],

[0182] In an alternative embodiment, circuit 222 is omitted.

[0183] The operation of the REFGEN device of [Fig.7] is within the reach of the person skilled in the art from the functional description given previously of the REFGEN devices of figures 5 and 6.

[0184] The REFGEN device described in relation to [Fig.7] has the advantage of being able to be implemented with MOS transistors similar to those of the IP device, i.e. MOS transistors having a voltage withstand Vmax. In addition, the circuits 2000 can then also be implemented with MOS transistors having a Vmax voltage rating.

[0185] [Fig.8] represents, in the form of a circuit, an alternative embodiment of the REFGEN circuit of [Fig.6]. Compared to the REFGEN circuit of [Fig.6] which is configured to provide the voltage VrefL, the REFGEN circuit of [Fig.8] is configured to generate the voltage VrefL and the voltage VrefH.

[0186] According to one embodiment, this REFGEN device provides the voltage VrefH to each circuit 2000 previously described and is part of the device 3000. Furthermore, the REFGEN device can be used to provide the voltage VrefH to the circuits 2000 described previously whether or not it is used to provide the voltage VrefH to the circuit IP.

[0187] The REFGEN device of [Fig.8] includes many elements in common with that of [Fig.6], and only the differences between these two devices are highlighted here. In particular, unless otherwise indicated, everything indicated for the REFGEN device described in relation to [Fig.6] applies to the REFGEN device of [Fig.8]. Furthermore, since the REFGEN device of [Fig.8] includes elements described in relation to the REFGEN device of [Fig.7], for these elements, only the differences between [Fig.7] and [Fig.8] are highlighted.

[0188] Compared to the REFGEN device of [Fig.6], the REFGEN device of [Fig.8] further comprises, like the REFGEN device of [Fig.7], the resistive voltage divider bridge 400 and a MOS transistor T8 in series between the nodes 202 and 204.

[0189] The source of transistor T8 is connected to the one of nodes 202 and 204 to which the source of transistor Ten is not connected, i.e. to node 204 in the embodiment of [Fig.8]. In the embodiment of [Fig.8], transistor T8 is N-channel.

[0190] Transistor T8 is configured to be on, respectively off, when transistor Ten is on, respectively off. In the embodiment of [Fig.8], transistor T8 has its gate connected to an intermediate node of bridge 208, for example to node 216.

[0191] The divider bridge 400 has its end 404 connected to the node 202 in the embodiment of [Fig.8].

[0192] Compared to the REFGEN device of [Fig.6], the REFGEN device of [Fig.8] comprises, like the REFGEN circuit of [Fig.7], the buffer circuit BUFFa2. The input 412 of the BUFFa2 circuit is connected to an intermediate node of the bridge 400, for example to the node 406. In the embodiment of [Fig.8], the output 410 of the BUFFa2 circuit provides the voltage VrefH.

[0193] The REFGEN device of [Fig.8] further comprises, like the REFGEN device of [Fig.7], a MOS transistor To2. The source of the transistor To2 is connected to the node 202 in the embodiment of [Fig.8] where the circuit BUFFa2 is configured to provide the voltage VrefH. In other words, the source of the transistor To2 and the source of the transistor Toi are connected to different respective nodes among the nodes 202 and 204. In the embodiment of [Fig.8], the transistor To2 is P-channel.

[0194] More particularly, in the embodiment of [Fig.8], the transistor To2 is configured so that its on or off state is determined by a voltage value V4 on a node of the divider bridge 208, for example on the node 210 of the divider bridge 300, and the transistor Toi is configured so that its on or off state is by a voltage value V3 on a node of the divider bridge 400, for example on the node 402 of the bridge 400. The transistor Toi has its gate coupled, preferably connected, to the node 402, the transistor To2 having its gate connected, preferably connected, to the node 210.

[0195] In an alternative embodiment (not shown) the REFGEN device comprises a MOS transistor and a resistive element in series between the nodes 202 and 204, identical to the transistor T5 and the element R4 of [Fig.3], and connected together, to the bridge 208 and to the transistor Toi in the same way as the transistor T5 and the element R4 in [Fig.6]. The transistor Toi is then not controlled by the voltage V3 of the bridge 400. Compared to the embodiment illustrated in [Fig.8], this alternative is more bulky.

[0196] In another alternative embodiment, which can be combined with the above alternative embodiment, the REFGEN device comprises a MOS transistor and a resistive element in series between the nodes 202 and 204, identical to the transistor T5 and the element R4 of [Fig. 5], and connected together, to the bridge 208 and to the transistor Toi in the same way as the transistor T5 and the element R4 in [Fig. 5]. The transistor To2 is then not controlled by the voltage V4 of the bridge 208. Compared to the embodiment illustrated in [Fig. 8], this alternative is more bulky.

[0197] In the embodiment of [Fig.8], the REFGEN device comprises the circuit 222 of [Fig.6].

[0198] In an alternative embodiment, circuit 222 is omitted.

[0199] The operation of the REFGEN device of [Fig.8] is within the reach of the person skilled in the art from the functional description given previously of the REFGEN devices of figures 5 and 6.

[0200] The REFGEN device described in relation to [Fig.8] has the advantage of being able to be implemented with MOS transistors similar to those of the IP device, i.e. MOS transistors having a voltage withstand Vmax, except with regard to the transistor T7 which is sized to be able to withstand the voltage VDDE on its drain. The circuits 2000 can then also be implemented with MOS transistors having a voltage withstand Vmax.

[0201] [Fig.9] represents, in the form of a circuit, an exemplary embodiment of an analog buffer circuit configured to provide the voltage VrefH. In this example, the buffer circuit described is the BUFFal circuit implemented in the REFGEN circuit of [Fig.7],

[0202] The BUFFal circuit comprises a differential pair comprising two MOS transistors T10 and Tl 1. Since the BUFFal circuit provides the voltage VrefH, the transistors T10 and Tl 1 are preferably N-channel.

[0203] Transistor T10 has its gate connected to input 220 of circuit BUFFal, and therefore receives, in this example, the voltage present on node 214 of bridge 208 ([Fig.7]). Transistor T11 has its gate connected to output 218 of circuit BUFFal, and therefore receives voltage VrefH.

[0204] The BUFFal circuit further comprises two MOS transistors T12 and T13 mounted in current mirror of each other, and configured to bias the respective transistors T10 and T11 of the differential pair. Since the BUFFal circuit provides the voltage VrefH, the transistors T12 and T13 are preferably P-channel. For example, the transistors T12 and T13 have their sources connected to the node 202 and their gates connected to each other, the gate of the transistor T12 being further connected to the drain of this transistor T12. For example, the drain of the transistor T12, respectively T13, is connected to the drain of the transistor T10, respectively T11.

[0205] The BUFFal circuit further comprises a MOS transistor T14 having its gate connected to a node 600 for connecting the transistor T13 to the transistor T11, and its source connected to the output 218 of the circuit. As the BUFFal circuit provides the voltage VrefH, the transistor T14 is preferably N-channel and has its drain connected to the node 202.

[0206] Preferably, a capacitive element C is connected between the gate and the source of the transistor T14 to improve the stability of the BUFFal circuit.

[0207] The BUFFal circuit further comprises a MOS transistor T15 coupling the differential pair (transistors T10 and T11) to the one of the nodes 202 and 204 to which the transistors T12 and T13 are not connected, and a MOS transistor T16 coupling the output 218 to the one of the nodes 202 and 204 to which the transistor T14 is not connected. In the example of [Fig.9], since transistors T12 and T13 are connected to node 202, transistor T15 couples the differential pair to node 204, and, furthermore, since transistor T14 is connected to node 202, transistor T16 couples output 218 to node 204. In this example, transistors T15 and T16 are therefore N-channel. For example, transistors T15 and T16 have their sources connected to node 204, transistor T15 has its drain coupled, preferably connected, to the sources of transistors T10 and T11 of the differential pair, and transistor T16 has its drain coupled, preferably connected, to output 218.

[0208] The BUFFal circuit further comprises a MOS transistor T17 with a channel of the same type as that of the channels of the transistors T15 and T16, namely N-channel in this example. This transistor T17 has its source connected to the same node, 204 in this example, as the node to which the sources of transistors T15 and T16 are connected. Transistors T15 and T16 are connected in current mirror with transistor T17. For example, the gates of transistors T15 and T16 are each connected to the gate of transistor T17, with the gate of transistor T17 further connected to the drain of transistor T17.

[0209] According to one embodiment, the transistor T17 is advantageously biased from an intermediate node of the resistive divider bridge to which the circuit BUFFal is connected, namely from an intermediate node of the bridge 208 in this example, for example from the node 216 of the bridge 208 ([Fig.7]).

[0210] For example, the circuit BUFFal comprises a MOS transistor T18 with a channel of the opposite type to that of the channel of the transistor T17, and having its source connected to that of the nodes 202 and 204 to which the transistor T17 is not connected. Thus, in this example, the transistor T18 is P-channel and has its source connected to the node 202. In addition, the gate of the transistor T18 is connected to the intermediate node 216 of the bridge 208 from which the transistor T17 is biased. A resistor R couples the drains of the transistors T17 and T18 together.

[0211] In an alternative embodiment, the transistor T17 can be biased other than from a node of the resistive divider bridge to which the input 220 of the BUFFal circuit is connected.

[0212] According to one embodiment, to limit the consumption of the BUFFal circuit when the transistor Ten is in the off state ([Fig.7]), the BUFFal circuit comprises a MOS transistor T19 with a channel of the same type as that of the transistor T17, namely with an N channel in this example. The transistor T19 is configured to short-circuit the transistor T17 when the transistor Ten ([Fig.7]) is off. For example, the transistor T19 has its source, respectively its drain, connected to the source, respectively to the drain, of the transistor T17. By way of example, so that the transistor T19 is on when the transistor Ten is off, the gate of the transistor T19 is coupled, preferably connected, to the drain of the transistor which is in series with the resistive divider bridge to which the input 220 of the BUFFal circuit is connected, i.e. to the drain of the transistor Ten in this example.

[0213] Although an exemplary embodiment of the BUFFal circuit of the REFGEN device of [Fig. 7] has been described above, the BUFFa2 circuit of [Fig. 8] may be implemented by the circuit described in relation to [Fig. 9]. For example, in this case, the gate of transistor T10 is connected to node 406 of bridge 400, the gate of transistor T18 is connected to a node of bridge 400, for example to node 408, and the gate of transistor T19 is connected to the drain of transistor T8.

[0214] [Fig. 10] shows, in circuit form, an example of an embodiment of an analog buffer circuit configured to provide the voltage VrefL. In In this example, the buffer circuit described is the BUFFa2 circuit implemented in the REFGEN circuit of [Fig.7],

[0215] The BUFFa2 circuit of [Fig. 10] is similar to the BUFFal circuit of [Fig.9] and includes many elements in common with the latter, only the differences between these two devices being highlighted here.

[0216] In particular, since the circuit BUFFa2 provides the voltage VrefL, the transistors T10 and T11 of the circuit BUFFa2 are preferably P-channel.

[0217] The transistor T10 here has its gate connected to the input 220 of the circuit BUFFa2, and therefore receives, in this example, the voltage present on the node 406 of the bridge 400 ([Fig.7]). In addition, the transistor T11 here has its gate connected to the output 218 of the circuit BUFFa2, and therefore receives the voltage VrefL.

[0218] Since the circuit BUFFa2 provides the voltage VrefL, the transistors T12 and T13 connected in current mirror of each other to bias the respective transistors T10 and Tl 1 of the differential pair are preferably N-channel. For example, the transistors T12 and T13 here have their sources connected to the node 204 and their gates connected to each other, the gate of the transistor T12 being further connected to the drain of this transistor T12. For example, the drain of the transistor T12, respectively T13, is connected to the drain of the transistor T10, respectively Tl 1.

[0219] Since the circuit BUFFa2 provides the voltage VrefL, the transistor T14 having its gate connected to the node 600 and its source connected to the output 218 of the circuit BUFFa2 is, preferably, P-channel and has its drain connected to the node 202.

[0220] Preferably, the circuit BUFFa2 comprises the capacitive element C connected between the gate and the source of the transistor T14 to improve its stability.

[0221] In this embodiment, with transistors T12 and T13 connected to node 204, transistors T15 and T16 are connected to node 202. Transistor T15 therefore couples the differential pair to node 202, and, in addition, transistor T16 therefore couples output 218 to node 202. In this example, transistors T15 and T16 are therefore P-channel. For example, transistors T15 and T16 have their sources connected to node 202, transistor T15 has its drain coupled, preferably connected, to the sources of transistors T10 and T11, and transistor T16 has its drain coupled, preferably connected, to output 218.

[0222] Transistor T17 with a channel of the same type as that of the channels of transistors T15 and T16 is therefore P-channel in the BUFFa2 circuit, and has its source connected to the same node, 202 in this example, as the node to which the sources of transistors T15 and T16 are connected. Transistors T15 and T16 are connected in current mirror with transistor T17.

[0223] According to one embodiment, the transistor T17 is advantageously biased from an intermediate node of the resistive divider bridge to which the circuit is connected. BUFFa2, namely from an intermediate node of bridge 400 in this example, for example from node 406 of bridge 400 ([Fig.7]).

[0224] For example, the circuit BUFFa2 comprises the MOS transistor T18 with a channel of the opposite type to that of the channel of the transistor T17, and having its source connected to that of the nodes 202 and 204 to which the transistor T17 is not connected. Thus, in this example, the transistor T18 is N-channel and has its source connected to the node 204. In addition, the gate of the transistor T18 is connected to the intermediate node 406 of the bridge 400 from which the transistor T17 is biased. The resistor R couples the drains of the transistors T17 and T18 together.

[0225] In an alternative embodiment, the transistor T17 can be biased other than from a node of the resistive divider bridge to which the input 220 of the circuit BUFFa2 is connected.

[0226] According to one embodiment, to limit the consumption of the circuit BUFFa2 when the transistor Ten is in the off state ([Fig.7]), the circuit BUFFa2 comprises a MOS transistor T19 with a channel of the same type as that of the transistor T17, namely P channel in this example. The transistor T19 is configured to short-circuit the transistor T17 when the transistor Ten ([Fig.7]) is off. For example, the transistor T19 has its source, respectively its drain, connected to the source, respectively to the drain, of the transistor T17. By way of example, so that the transistor T19 is conducting when the transistor Ten is off, the gate of the transistor T19 is coupled, preferably connected, to the drain of the transistor which is in series with the resistive divider bridge to which the input 220 of the circuit BUFFa2 is connected, i.e. to the drain of the transistor T8 in this example.

[0227] Although an exemplary embodiment of the circuit BUFFa2 of the REFGEN device of [Fig. 7] has been described above, the circuit BUFFal of [Fig. 8] may be implemented by the circuit described in relation to [Fig. 10]. For example, in this case, the gate of transistor T10 of the circuit of [Fig. 10] is connected to node 214 of bridge 208, the gate of transistor T18 is connected to a node of bridge 208, for example to node 216, and the gate of transistor T19 is connected to the drain of transistor Ten.

[0228] In the embodiments and variants described previously in relation to FIGS. 4 to 10, each of the voltages VrefH and VrefL is generated from the voltage VDDE. Thus, each of the voltages VrefH and VrefL follows the variations in the voltage VDDE, and, in particular, the overvoltages or undervoltages of the voltage VDDE. This makes it possible to keep the voltages across the cascode transistors T2 and T3 of the structures 100 and 102 at values lower than the voltage withstand limit Vmax of these transistors. Furthermore, since each of the voltages VrefH and VrefL follows the variations in the voltage VDDE and is not generated from the voltage VDD, there is no no more constraints on the order in which the VDDE and VDD supply voltages must be supplied.

[0229] In the embodiments and variants described previously in relation to Figures 4 to 10, when the transistor Ten is on, each of the voltages VrefH and VrefL is generated from the voltage VDDE by a corresponding resistive voltage divider bridge 208 or 400. Thus, the dependence of the current value of each of the voltages VrefL and VrefH on the temperature is reduced or eliminated. Furthermore, the ratio between the current value of the voltage VrefH, respectively VrefL, and that of the voltage VDDE can be easily chosen by adapting the values of one or more of the resistive elements of the corresponding bridge 208 or 400.

[0230] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0231] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A circuit (2000) comprising: a first node (2002) configured to receive a reference potential (GND); a second node (2004) configured to receive a first DC voltage (VI), the first DC voltage being a supply voltage (VDDE, VDD); a third node (2006) configured to receive a second DC voltage (V2); a first NMOS transistor (MN1) having its gate connected to the second node; a second NMOS transistor (MN2) having its drain connected to the source of the first transistor (MN1) and its source connected to the second node; a third NMOS transistor (MN3) having its gate connected to the second node and its source connected to the first node; a fourth PMOS transistor (MP3) having its drain connected to the drain of the third transistor (MN3) and to the gate of the second transistor (MN2) and its gate connected to the source of the first transistor (MN1);a first resistive element (2008) connected between the drain of the first transistor (MN1) and the third node; a second resistive element (2010) connected between the source of the fourth transistor (MP3) and the third node; and a first CMOS inverter (INV3) configured to be powered by the second voltage (V2), an input of the first inverter being connected to the drain of the third transistor (MP3) and an output of the first inverter being configured to provide a reset signal (POR2000).;

2. The circuit of claim 1, wherein each of the first and second resistive elements (2008, 2010) is implemented by a PMOS transistor (MPI, MP2) having its gate connected to the first node and its source connected to the third node.

3. A circuit according to claim 1 or 2, further comprising a capacitive element (Ce) connected between the gate and the source of the first transistor (MN1).

4. A circuit according to any one of claims 1 to 3, further comprising a second CMOS inverter (INV4) configured to be powered by the second voltage (V2), an input of the second inverter being connected to the output of the first inverter (INV3), and an output of the second inverter being configured to provide a signal (nPOR2000) complementary to the reset signal (POR2000).

5. A circuit according to any one of claims 1 to 4, wherein the first and second resistive elements (2008, 2010), and the first and fourth transistors (MN1, MP3) are sized so that the fourth transistor (MP3) is off when the first transistor is on (MN1).

6. Circuit according to any one of claims 1 to 5, in which the second voltage (V2) is also a supply voltage (VDDE, VDD).

7. Device comprising: at least two circuits (2000) according to any one of claims 1 to 6; and a CMOS logic gate (3002) configured to implement a Boolean AND logic function between the reset signals (POR2000) provided by said at least two circuits, wherein: the first nodes (2002) of said at least two circuits are configured to receive the same reference potential (GND); the third nodes (2006) of said at least two circuits are configured to receive a same second voltage, said second voltage being a reference voltage (VrefH); and the second nodes (2004) of said at least two circuits are each configured to receive a first DC supply voltage (VDDE, VDD) different from the first voltages received by the second nodes of the other circuits.

8. Device according to claim 7, wherein the CMOS logic gate (3002) is configured to be powered by the second voltage (VrefH).

9. Device according to claim 7 or 8 comprising a voltage generation circuit (REFGEN) configured to provide the second reference DC voltage (VrefH).

10. Device according to claim 9, in which the voltage generation circuit is configured to provide the second reference DC voltage at its nominal value before a power-up and a power-up of each of the first voltages (VDDE, VDD).

11. Device according to claim 9, in which the circuit (REFGEN) of generating the second reference voltage (VrefH) comprises: a first voltage divider bridge (200) connected between a first supply node (202) configured to receive one of the first direct supply voltages (VDDE) and a second supply node (204) configured to receive the reference potential (GND); a first MOS transistor (Ten) and a second resistive voltage divider bridge (208) connected in series between the first and second supply nodes (202, 204), the first transistor having its gate connected to an intermediate node (206) of the first bridge and its source connected to the second supply node (204); a first buffer circuit (BUFFal) configured to be powered by said one of the first direct supply voltages (VDDE) and comprising an input (220) connected to a first intermediate node (214) of the second bridge and an output (218) configured to provide the second reference voltage (VrefH); and a second MOS transistor (Toi) having its drain connected to the output of the first buffer circuit and its source connected to the first power supply node (202), in which the first bridge (200) is configured so that the first transistor (Ten) is blocked when said one of the first direct supply voltages (VDDE) is at a value lower than a first threshold itself lower than a voltage withstand limit of the transistors, and wherein the second transistor (Toi) is configured to be in the on state if the first transistor (Ten) is in the off state and vice versa.

12. Device according to claim 9 wherein the circuit (REFGEN) for generating the second reference voltage (VrefH) comprises: a first voltage divider bridge (200) connected between a first power supply node (202) configured to receive one of the first DC power supply voltages (VDDE) and a second power supply node (204) configured to receive the reference potential (GND); a first MOS transistor (Ten) and a second resistive voltage divider bridge (208) connected in series between the first and second supply nodes (202, 204), the first transistor having its gate connected to an intermediate node (206) of the first bridge and its source connected to the first power node (202); a second MOS transistor (T8) and a third resistive voltage divider bridge (400) connected in series between the first and second supply nodes (202, 204), the source of the second MOS transistor (T8) being connected to the second supply node (202, 204); a buffer circuit (BUFFa2) configured to be powered by said one of the first direct supply voltages (VDDE) and comprising an input (220) connected to a first intermediate node (406) of the third bridge (400) and an output (218) configured to provide the second reference voltage (VrefH); and a third MOS transistor (To2) having its drain connected to the output of the buffer circuit (BUFFa2) and its source connected to the first power supply node (202); wherein the second transistor (T8) is configured to be in the off state, respectively on, when the first transistor (Ten) is in the off state, respectively on, wherein the third transistor (To2) is configured to be in the on state if the second transistor (T8) is in the off state and vice versa, and in which the first bridge (200) is configured so that the first transistor (Ten) is blocked when said one of the first direct supply voltages (VDDE) is at a value lower than a first threshold itself lower than a voltage withstand limit of the transistors.

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