SEMICONDUCTOR DEVICE

Abstract

The invention relates to a semiconductor device comprising: an amplifier configured from a silicon carbide element, and including a differential amplifier circuit that amplifies an input signal; and a power supply circuit that provides a voltage to the amplifier. The voltage fluctuation reduction circuit is inserted between the power supply circuit and the amplifier. As a result, it is possible to appropriately eliminate the influence of drift when the amplifier is configured from a silicon carbide semiconductor.

Description

Title of the invention: SEMICONDUCTOR DEVICE CONTEXT OF THE INVENTION

[0001] 1. Field of the invention

[0002]

[0003] The present invention relates to a semiconductor device.

[0004] 2. Description of the state of the art

[0005]

[0006] In recent years, semiconductors configured from elements made of silicon carbide (SiC) have become widespread. A device made of silicon carbide has characteristics different from those of a conventional device made of silicon, and offers various advantages. For example, a semiconductor made of silicon carbide has excellent radiation resistance performance and is therefore suitable for a measurement system of a nuclear energy device and a device used in space, such as an artificial satellite.

[0007] As an example, it is envisaged to configure an amplifier called a differential amplifier circuit from an element made of silicon carbide.

[0008]

[0009] JP 2023-31429 A discloses that a circuit having excellent radiation resistance is configured using a semiconductor made of silicon carbide. It is disclosed that, in the case where a semiconductor device is made of silicon carbide, the technique described in JP 2023-31429 A has a problem that a voltage spike is generated during startup, and a circuit configuration having excellent spike resistance is proposed to overcome this problem. Summary of the invention

[0010]

[0011] Furthermore, when a measuring system having excellent radiation resistance is configured from a semiconductor made of silicon carbide, an amplifier (differential amplifier circuit) is configured from a semiconductor made of silicon carbide.

[0012] However, when the amplifier is made of a semiconductor made of silicon carbide, the problem arises that during startup, a voltage affects an input terminal of the amplifier and causes an offset voltage to drift. Since this drift exerts an influence for several hours, e.g. For example, in the case of a measuring system that measures the output signal of an amplifier, it is not possible to make an accurate measurement.

[0013]

[0014] Furthermore, the problem that the semiconductor made of silicon carbide causes the offset voltage to drift is considered to be due to the characteristics of the material constituting the semiconductor itself, as well as the fact that the manufacturing process becomes more unstable in the case of the semiconductor made of silicon carbide than in the case of a semiconductor made of silicon.

[0015]

[0016] In view of the above, an object of the present invention is to provide a semiconductor device capable of obtaining an output signal without the influence of drift, even when an amplifier is configured from a semiconductor made of silicon carbide.

[0017]

[0018] The present application provides a plurality of means for solving the above-mentioned problem, one example of which is a semiconductor device comprising: an amplifier configured from a member made of silicon carbide, and comprising a differential amplifier circuit which amplifies an input signal; and a power supply circuit which supplies a voltage to the amplifier, a voltage fluctuation level reduction circuit being inserted between the power supply circuit and the amplifier.

[0019]

[0020] According to the present invention, it is possible to prevent a drift of an offset voltage from occurring by means of a voltage fluctuation level reduction circuit, and to suppress a fluctuation of an output signal due to the drift of the offset voltage in the case where a differential amplifier circuit is configured from a member made of silicon carbide.

[0021] Problems, configurations, and effects other than those described above will become apparent from the following description of embodiments. Brief description of the drawings

[0022]

[0023] [Fig.l] [Fig.l] is a circuit diagram of a semiconductor device according to a first embodiment of the present invention;

[0024] [Fig.2] [Fig.2] is a general configuration diagram of the semiconductor device driver according to the first embodiment of the present invention;

[0025] [Fig.3] [Fig.3] is a circuit diagram of a dV / dt reduction circuit of the semiconductor device according to the first embodiment of the present invention;

[0026] [Fig.4] [Fig.4] is a characteristic diagram of a dV / reduction circuit dt of the semiconductor device according to the first embodiment of the present invention;

[0027] [Fig.5] [Fig.5] is a circuit diagram of a semiconductor device according to the second embodiment of the present invention;

[0028] [Fig.6] [Fig.6] is a characteristic diagram of a semiconductor device according to the second embodiment of the present invention;

[0029] [Fig.7] [Fig.7] is a circuit diagram showing an example of a device with conventional semiconductor;

[0030] [Fig.8] [Fig.8] is a characteristic diagram showing an example of operation of the conventional semiconductor device;

[0031] [Fig.9] [Fig.9] is a characteristic diagram comparing a characteristic according to the present invention at a conventional offset voltage; and

[0032] [Fig. 10] [Fig. 10] is a circuit diagram showing a modified example of the semiconductor device according to the embodiments of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033]

[0034] <Premier mode de réalisation>

[0035] A semiconductor device according to a first embodiment of the present invention will be described below with reference to Figures 1 to 4.

[0036] [Fig.l] shows a circuit of a semiconductor device according to this embodiment.

[0037] The semiconductor device of this embodiment is a semiconductor device used as a measurement system 100, and comprises an amplifier 1 having a differential amplifier circuit which amplifies an input signal.

[0038] Amplifier 1 is configured from a semiconductor made of silicon carbide (SiC). Amplifier 1 is hereinafter referred to as a SiC amplifier.

[0039]

[0040] The SiC amplifier 1 has a positive input terminal (non-inverting input terminal) and a negative input terminal (inverting input terminal), and a signal obtained by a measurement signal input terminal 2 is supplied to the positive input terminal. At an output terminal 3, the SiC amplifier 1 then obtains a signal obtained by amplifying the difference between the signals obtained at the positive input terminal and the negative input terminal. The negative input terminal and the output 3 are connected, and one output of the amplifier to SiC 1 is fed back to the negative input terminal.

[0041]

[0042] The SiC amplifier 1 has a positive power supply terminal and a negative power supply terminal. A positive power supply Vdd is supplied to the positive power supply terminal of the SiC amplifier 1, and a negative power supply Vss is supplied to the negative power supply terminal of the SiC amplifier 1.

[0043] The positive power supply Vdd is provided by a power supply circuit 4. The negative power supply Vss is for example a ground potential of the power supply circuit 4.

[0044]

[0045] In this embodiment, a dV / dt reduction circuit 5 is connected between the power supply circuit 4 and the positive power supply Vdd. The dV / dt reduction circuit 5 acts as a voltage fluctuation level reduction circuit, and reduces a voltage fluctuation level dV in a unit time dt. In this case, a variation dV per unit time dt is a variation at least less than 15 V / ms.

[0046] In the case of the configuration of [Fig.l], the dV / dt reduction circuit 5 is connected between a positive side of the power supply circuit 4 and a line of the positive power supply Vdd.

[0047]

[0048] [Fig.2] represents an example configuration of the entire measurement system 100 comprising the SiC amplifier 1 having the circuit configuration illustrated in [Fig.l].

[0049] The measuring system 100 comprises a sensor 101, a semiconductor device 102 and an output unit 103.

[0050] The sensor 101 measures various states such as pressure and water level, and outputs a measurement signal. For example, the sensor 101 measures the water level in a pressure vessel of a nuclear power plant. A voltage value of the measurement signal output by the sensor 101 varies.

[0051]

[0052] The measurement signal output by the sensor 101 is delivered to the semiconductor device 102. The semiconductor device 102 has the same configuration as that illustrated for example in [Fig.l], and comprises the SiC amplifier 1 ([Fig.l]).

[0053] A power supply unit 102a of the semiconductor device 102 comprises the power supply circuit 4 and the dV / dt reduction circuit 5.

[0054] The measurement signal amplified by the semiconductor device 102 is then supplied to the output unit 103, outputting a voltage signal which is the signal measuring. The output processing of the measuring signal in the output unit 103 includes displaying and recording a voltage value, transmitting it to the outside, etc.

[0055]

[0056] [Fig.3] shows an example of configuration of the dV / dt reduction circuit 5.

[0057] The example illustrated in [Fig.3] is an example of the dV / dt reduction circuit 5 connected between power input Vin and power output Vout. Power circuit 4 is connected to power input Vin.

[0058] In the dV / dt reduction circuit 5, a resistor 51 is connected in series between the power input Vin and the power output Vout, and one end of a capacitor 52 is connected between the resistor 51 and the power output Vout. The other end of the capacitor 52 is connected to a part at ground potential.

[0059] The resistor 51 and the capacitor 52 of the configuration shown in [Fig.3] act as a low-pass filter, and the voltage fluctuation dV during the unit time dt is reduced by a passive circuit comprising the resistor 51 and the capacitor 52.

[0060]

[0061] [Fig.4] represents the characteristics of the dV / dt reduction circuit 5 illustrated in [Fig.3].

[0062] The characteristic diagram at the top of [Fig.4] represents a temporal variation (horizontal axis) of the voltage (vertical axis) of the power input Vin.

[0063] The characteristic diagram at the bottom of [Fig.4] represents a temporal variation (horizontal axis) of the voltage (vertical axis) of the power output Vout obtained via the dV / dt reduction circuit 5.

[0064] As illustrated in the characteristic diagram at the top of [Fig.4], the power supply circuit 4 is started at a certain instant to provide an output voltage E.

[0065]

[0066] At this instant, as illustrated in the characteristic diagram at the bottom of [Fig.4], the output power Vout increases up to the voltage E with a certain time constant due to the action of the low-pass filter comprising the resistor 51 and the capacitor 52.

[0067] When the characteristics of the resistor 51 and the capacitor 52 are respectively designated by R and C, the output power Vout has the characteristics expressed by the following [Expression 1].

[0068]

[0069] [Expression 1] = f(l - e“râ)

[0070] By means of the measurement system 100 configured as described above, it is possible to avoid the drift of the offset voltage, and it is possible to suppress the fluctuation of the output signal due to the drift of the offset voltage when the SiC amplifier 1 comprising the element made of silicon carbide is used.

[0071]

[0072] <Second mode de réalisation>

[0073] A semiconductor device according to a second embodiment of the present invention will next be described with reference to Figures 5 to 6. In Figures 5 and 6, parts which are identical to those of Figures 1 to 4 described in the first embodiment are designated by the same reference numerals, and any redundant description will be omitted.

[0074]

[0075] [Fig.5] shows a circuit of a semiconductor device according to this embodiment.

[0076] In the SiC amplifier 1 made of a semiconductor consisting of silicon carbide (SiC), a resistor 6a is connected between the output terminal 3 and the negative input terminal Viri.

[0077] In addition, a resistor 6c is connected to the positive input terminal Vin+ of the SiC amplifier 1, and an input signal for the SiC amplifier 1 is provided via the resistor 6c.

[0078] Furthermore, a resistor 6b is connected to the negative input terminal Vm of the SiC amplifier 1.

[0079]

[0080] The positive power supply Vdd is then supplied by a power supply circuit 4a to the positive power supply terminal of the SiC amplifier 1, and the negative power supply Vss is supplied by a power supply circuit 4b to the negative power supply terminal of the SiC amplifier 1.

[0081] In the present case, the dV / dt reduction circuit 5a is connected between the power supply circuit 4a and the positive power supply terminal of the SiC amplifier 1. Similarly, a dV / dt reduction circuit 5b is connected between the power supply circuit 4b and the negative power supply terminal of the SiC amplifier 1.

[0082] Each of the dV / dt reduction circuits 5a and 5b comprises a filter comprising passive components (a resistor and a capacitor), for example illustrated in [Fig.3].

[0083]

[0084] [Fig.6] represents a characteristic example of the circuit illustrated in [Fig.5].

[0085] In the example of [Fig.6], the vertical axis represents the negative input terminal Vm, the positive input terminal Vin+, the positive power supply Vdd, and the negative power supply Vss of the SiC amplifier 1, and the horizontal axis represents the time variation (ms).

[0086] As illustrated in [Fig.6], at the instant when the start-up period T1 ends, the positive supply Vdd and the negative supply Vss increase to the prescribed voltages. It is assumed here that the positive supply Vdd is 4 V and the negative supply Vss is -4 V.

[0087] A period T2 during which a virtual short circuit is in operation follows the completion of the start-up period T1.

[0088]

[0089] In the example of [Fig.6], an overvoltage of the input voltage of the negative input terminal Viri occurs immediately before the end of the start-up period Tl. This overvoltage is equal to or less than 0.5 V.

[0090] At this time, under the effect of the dV / dt reduction circuits 5a and 5b, the time when an overvoltage peak Vp occurs in the positive power supply Vdd shifts to the period T2 during which the virtual short circuit is in operation. In other words, the voltage output by the power supply circuits 4a and 4b during startup is lower than the value of the supply voltage which converges until a virtual short circuit occurs between the two input terminals Vm and Vin+.

[0091] As a result, it is possible to eliminate an adverse effect on the output signal when the SiC amplifier 1 comprising the element made of silicon carbide is used.

[0092] The positive supply Vdd and the negative supply Vss gradually converge towards 4 V or -4 V during the period T2 during which the virtual short circuit is in operation.

[0093]

[0094] A configuration in which the dV / dt reduction circuits 5a and 5b are not provided for the semiconductor device illustrated in [Fig.5] (conventional configuration: [Fig.7]) and the characteristics of the configuration of [Fig.7] will be described here ([Fig.8]) for reference.

[0095] In the case of the semiconductor device illustrated in [Fig.7], the positive supply Vdd is supplied by the supply circuit 4a to the positive supply terminal of the SiC amplifier 1, and the negative supply Vss is supplied by the supply circuit 4b to the negative supply terminal of the SiC amplifier 1. In the present case, the dV / dt reduction circuits 5a and 5b are not connected to the respective supply circuits 4a and 4b.

[0096]

[0097] Referring to [Fig.8], which shows the characteristics of the configuration illustrated in [Fig.7], an overvoltage of the input voltage of the negative input terminal Vm occurs immediately before the end of the start-up period Tl. This overvoltage is approximately 2.0 V.

[0098] At this instant, an overvoltage peak Vp' occurs in the positive power supply Vdd practically at the same instant as the overvoltage of the input voltage of the negative input terminal Viri.

[0099] In the case of the characteristics of the embodiment illustrated in [Fig.6], the instant when the overvoltage peak Vp occurs shifts towards the period T2 during which the virtual short circuit is in operation.

[0100]

[0101] Furthermore, in the characteristics illustrated in [Fig.8], the instant when the overvoltage peak Vp' occurs is the overvoltage peak Vp' appearing during the start-up period T1.

[0102] As can be seen by comparison with the characteristics of this embodiment illustrated in [Fig.6], in the case of the characteristics of the conventional configuration illustrated in [Fig.8], there occurs an adverse effect due to the overvoltage peak Vp' during the start-up period T1, whereas in the case of the characteristics of this embodiment, an adverse effect due to the overvoltage peak Vp can be eliminated.

[0103]

[0104] [Fig.9] shows a comparison of the offset voltage (vertical axis) of the SiC amplifier 1 between the Va characteristic of the configuration of [Fig.5] (configuration including the dV / dt reduction circuits 5a and 5b) and the Vb characteristic of the configuration of [Fig.7] (configuration without the dV / dt reduction circuits 5a and 5b). The horizontal axis of [Fig.9] represents the time (h). In the example of [Fig.9], the positive supply Vdd is 4 V, and the negative supply Vss is -4 V.

[0105] The offset voltage of the SiC amplifier 1 is here a value obtained by subtracting the voltage of the negative input terminal Vm from the voltage of the positive input terminal Vin+.

[0106]

[0107] The Va characteristic of the configuration comprising the dV / dt reduction circuits 5a and 5b is generally stable in any time zone with an offset voltage of about -3.4 V to -3.6 V.

[0108] Furthermore, in the case of the Vb characteristic of the configuration not including the dV / dt reduction circuits 5a and 5b, the offset voltage fluctuates greatly from about +0.5 V to about -2 V over an extended period.

[0109] Therefore, the use of the dV / dt reduction circuits 5a and 5b can satisfactorily suppress the fluctuation of the offset voltage during startup.

[0110] [YES]<Exemple modifié>

[0112] It should be noted that the embodiments described above have been presented in detail in order to describe the present invention in an easily understood manner, and that it is not necessarily intended to be limited to those which have all the configurations described.

[0113]

[0114] For example, while the power supply circuit having an independent configuration of the SiC amplifier 1 is connected in the embodiments described above, a similar dV / dt reduction circuit can be connected in a configuration in which the SiC amplifier and the power supply circuit are integrated.

[0115] [Fig. 10] represents an example of a configuration corresponding to this case.

[0116] In the example of [Fig.10], a series circuit consisting of a Zener diode 13 and a resistor 14 is connected between the power input Vin and a part at ground potential GND. A connection point between the Zener diode 13 and the resistor 14 is then connected to a negative input terminal of a SiC amplifier 11.

[0117]

[0118] An output terminal of the SiC amplifier 11 is connected to a base of an NPN bipolar junction transistor 12. An emitter of the transistor 12 is connected to the ground potential portion GND, and a collector of the transistor 12 is connected to the base of a PNP bipolar junction transistor 15.

[0119] An emitter of transistor 15 is connected to power input Vin, and a collector of transistor 15 is connected to power input Vout.

[0120] In addition, the power input Voutest connected to a positive input terminal of the SiC amplifier 11.

[0121]

[0122] A dV / dt reduction circuit 20 is then connected between the output terminal of the SiC amplifier 11 and the negative input terminal of the SiC amplifier 11. In the example of [Fig. 10], the dV / dt reduction circuit 20 is configured as the form of a low-pass filter in which a resistor 21 and a capacitor 22 are connected in parallel.

[0123] In a case where the power supply circuit including the Zener diode 13, etc. is integrated with the SiC amplifier 11 as described above, the same effects as those of the first embodiment and the second embodiment can be obtained when the dV / dt reduction circuit 20 is connected between the power supply circuit and the SiC amplifier 11.

[0124]

[0125] Furthermore, a configuration in which a dV / dt reduction circuit is configured from a filter using a passive component is only one example, and the dV / dt reduction circuit may be a circuit having another circuit configuration that acts as a voltage fluctuation level reduction circuit, which reduces the voltage fluctuation level dV during the unit time dt.

Claims

Claims

1. A semiconductor device comprising: an amplifier configured from a member made of silicon carbide, and comprising a differential amplifier circuit which amplifies an input signal; a power supply circuit which supplies a voltage to the amplifier; and a voltage fluctuation level reducing circuit inserted between the power supply circuit and the amplifier.

2. A semiconductor device according to claim 1, wherein one of two input terminals of the differential amplifier circuit contained in the amplifier is electrically connected to an output terminal of the amplifier, and the voltage fluctuation level reduction circuit shifts an overvoltage peak of a supply voltage of the power supply circuit during startup to a time when a virtual short circuit of the differential amplifier circuit is in operation.

3. A semiconductor device according to claim 2, wherein a voltage output from the power supply circuit during startup is lower than a supply voltage value which converges until a virtual short circuit occurs between the two input terminals.

4. The semiconductor device of claim 1, wherein the power supply circuit comprises a first power supply circuit that supplies current to the positive electrode side of the differential amplifier circuit and a second power supply circuit that supplies current to the negative electrode side of the differential amplifier circuit, and the voltage fluctuation level reducing circuit is inserted between the first power supply circuit and the amplifier, as well as between the second power supply circuit and the amplifier.

5. A semiconductor device according to claim 1, wherein the voltage fluctuation level reducing circuit is connected between one of the input terminals of the differential amplifier circuit and an output terminal.

6. A semiconductor device according to claim 1, wherein the voltage fluctuation level reduction circuit comprises a filter having a passive component.

7. A semiconductor device according to claim 1, wherein an input signal of the amplifier is a measurement signal, and a signal obtained at an output terminal of the amplifier is output as an amplified measurement signal.

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