Device for a particle counting detector

Abstract

Device for a particle counting detector This description relates to a device (EVAL-NUM2) for a particle counting detector (DET2), in which: the device comprises N digitizing channels, CHi, with N an integer strictly greater than 1 and i an index from 1 to N; each channel CHi comprises a comparator, COMPi, associated with a threshold, Thi, of the channel and providing a first digital pulse signal, outi, active if a pulse voltage (outFE) is greater than the threshold of the channel, and inactive otherwise; the thresholds Thi are increasing with the index i; for i from 2 to N, each comparator COMPi operates selectively in a low-power mode and a high-power mode; and the device comprises a circuit (BOOST) controlling, for i from 2 to N, each comparator COMPi in the low-power mode or in the high-power mode as a function of at least the first signal outi of at least one of the channels CHi.Figure for the summary: Fig. 3.

Description

Title of the invention: Device for a particle counting detector technical field

[0001] The present description relates generally to electronic circuits, and, more particularly, to devices (or circuits) for particle counting detectors. Previous technique

[0002] Known electronic systems include one or more particle counting detectors. Each detector includes a photodetector configured to receive incident particles and to provide a pulsed analog current determined by the received particles. Each detector further includes a current-to-voltage conversion circuit configured to receive the pulsed analog current and to provide a corresponding pulsed analog voltage. Each detector further includes a device configured to allow the evaluation of the number and energy of the particles received by the photodetector, based on the pulsed analog voltage.

[0003] Photon-counting spectral scanners are an example of such a known electronic system, used, for example, in medical imaging. In a photon-counting spectral scanner, the particles are, for example, photons of X-ray radiation, that is, radiation in the wavelength range from approximately 0.01 nm to approximately 10 nm. For example, each photodetector then comprises cadmium telluride.

[0004] Known particle counting detectors have drawbacks. Summary of the invention

[0005] There is a need to overcome all or part of the drawbacks of known particle counting detectors, for example known devices allowing the evaluation of the number and energy of the particles received by these known detectors.

[0006] For example, it would be desirable to have a particle counting detector that has reduced consumption compared to known particle counting detectors.

[0007] For example, it would be desirable to have a device for a particle counting detector that makes it possible to reduce the consumption of the particle counting detector compared to known particle counting detectors.

[0008] For example, it would be desirable to have a particle counting detector that allows for the correct evaluation of the number and energy of the particles it receives. when the probability of receiving two particles close together in time increases.

[0009] For example, it would be desirable to have a device for a particle counting detector that allows the particle counting detector to correctly evaluate the number and energy of the particles it receives when the probability of receiving two particles close together in time increases, preferably without intervening upstream of the analog-to-digital conversion circuit of the detector, that is to say without intervening on the purely analog part of the detector.

[0010] One embodiment overcomes all or part of the drawbacks of known particle counting detectors.

[0011] An embodiment overcomes all or part of the drawbacks of known devices for a particle counting detector allowing the evaluation of the number and energy of the particles received by the detector.

[0012] One embodiment provides a device for a particle counting detector, in which: the device comprises N digitization channels, CHi, with N an integer strictly greater than 1 and i an index from 1 to N, Each CHi channel includes a comparator, COMPi, associated with a threshold, Thi, of the channel and configured to provide a first pulsed digital signal, outi, in an active state if a pulsed analog voltage supplied to said channels is greater than the threshold of the channel, and in an inactive state otherwise; the thresholds Thi are increasing with the index i; For i ranging from 2 to N, each COMPi comparator is configured to selectively operate in a low-power mode and a high-power mode; and the device includes a COMPi comparator control circuit configured, for i ranging from 2 to N, to control each COMPi comparator in low power mode or in high power mode as a function of at least the first outi signal of at least one of the CHi channels.

[0013] According to one embodiment, the control circuit is configured, at a rising edge of each pulse of said voltage and for i ranging from 2 to N, to switch each comparator COMPi into the high consumption mode in response to a switching to the active state of the first outi signal of the CHI channel or of the first outi-1 signal of the CHi-1 channel.

[0014] According to one embodiment, the control circuit is further configured, following the rising edge of the pulse of said voltage and for i ranging from 2 to N, to switch each comparator COMPi into the low power mode at the earliest in response to a switching to the active state of the first signal outi of the CHi channel, and at the latest in response to a switching to the inactive state of the first signal outi of the CHI channel.

[0015] According to one embodiment, the control circuit is configured, for i ranging from 2 to N, to control each COMPi comparator in high power mode if the first outi-1 signal of channel CHi-1 is active, and in low power mode otherwise.

[0016] According to one embodiment, N is strictly greater than 2 and the control circuit is configured, for i ranging from 2 to N-1, for: - control each COMPi comparator in high-power mode if the first outi-1 signal of channel CHi-1 is active while the first outi+1 signal of channel CHi+1 is inactive, and in low-power mode otherwise; and - control the COMPN comparator in high power mode if the first outN-1 signal of the CHN-1 channel is active and in low power mode otherwise.

[0017] According to one embodiment, the control circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in high consumption mode if the first outl signal of channel CH1 is in the active state, and in low consumption mode otherwise.

[0018] According to one embodiment: - The COMPI comparator is configured to operate only in high-power mode; or - The COMPI comparator is configured to operate selectively in high power mode or low power mode, and the control circuit is configured to control the COMPI comparator in high power mode if the first signal out2 is inactive, and in low power mode otherwise.

[0019] According to one embodiment, the device further includes a digital counting circuit configured to count, for each channel CHi, a number of switchings to the active state of the first signal outi of said channel.

[0020] According to one embodiment: The device also includes a digital pulse reset circuit configured for: - for each CHi channel, receive the first outi signal of said channel, generate a second pulsed digital outci signal, and switch the second outci signal to an active state when the first outi signal is in the active state; and - generate a reset signal forcing, at each switch to the active state of the second outci signal of the CHI channel, a switch to the inactive state of the first outci signals and / or the second outci signals at the end of a first time period beginning with the switch to the active state of the second outci signal of the CHI channel.

[0021] According to one embodiment, the reset signal is configured to force, at each switching to the active state of the second outcl signal of channel CH1, at least the switching to the inactive state of the first outi signals at the end of the first time period beginning with the switching to the active state of the second outcl signal of channel CH1.

[0022] According to one embodiment: The device also includes a digital pulse reset circuit configured for: - for each CHi channel, receive the first outi signal of said channel, generate a second pulsed digital outci signal, and switch the second outci signal to an active state when the first outi signal is in the active state; and - generate a reset signal forcing, each time the second outcl signal of the CHI channel switches to the active state, a switch to the inactive state of the first outi signals at the end of a first time period beginning with the switching of the second outcl signal of the CHI channel to the active state, and The control circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in high power mode if the first outi signal of the CHi channel is in the inactive state while the first outi signal of the CHI channel is in the active state, and in low power mode otherwise.

[0023] According to one embodiment: The device also includes a digital pulse reset circuit configured for: - for each CHi channel, receive the first outi signal of said channel, generate a second pulsed digital outci signal, and switch the second outci signal to an active state when the first outi signal is in the active state; and - generate a reset signal forcing, each time the second outcl signal of the CHI channel switches to the active state, a switch to the inactive state of the first outi signals at the end of a first time period beginning with the switching of the second outcl signal of the CHI channel to the active state, and the control circuit is configured to, for i ranging from 2 to N, control each comparator COMPi in high power mode if the first outi signal of channel CHi is in the inactive state while the first outi-1 signal of channel CHi-1 is in the active state, and in low power mode otherwise.

[0024] According to one embodiment, the device further includes a digital counting circuit configured to count, for each channel CHi, a number of switchings to the active state of the second outci signal of said channel.

[0025] One embodiment provides a particle counting detector comprising: a photodetector adapted to receive particles, for example photons from X-rays, and to provide a pulsed analog current determined by the particles received; a current-to-voltage conversion circuit configured to receive the pulsed analog current and to provide a corresponding pulsed analog voltage; and a device such as above, configured to receive the pulsed analog voltage.

[0026] One embodiment provides a photon-counting scanner comprising a plurality of particle-counting detectors such as above, wherein the particles are photons of X-ray radiation, and each photodetector comprises, for example, cadmium telluride.

[0027] Another embodiment provides a device for a particle counting detector, the device comprising: digitization channels each configured to receive a pulsed analog voltage and to provide a first pulsed digital signal in an active state if said voltage is greater than a channel threshold, and in an inactive state otherwise; and a digital pulse reset circuit configured for: - for each channel, receive the first signal from said channel, generate a second pulsed digital signal, and switch the second signal to an active state when the first signal is active; and - generate a reset signal forcing, at each switch to the active state of the second signal of the lowest threshold channel, a switch to the inactive state of the first signals and / or the second signals at the end of a first time period beginning with the switch to the active state of the second signal of the lowest threshold channel.

[0028] According to one embodiment, the reset circuit is configured to: - for each lane and after each switching to the active state of the second signal of the lane, to maintain the second signal in the active state until the reset signal forces the second signal to the inactive state; or - for each lane and after each switching to the active state of the second signal of the lane, to maintain the second signal in the active state until the first signal of the lane switches to the inactive state or the reset signal forces the second signal to the inactive state.

[0029] According to one embodiment, the device further comprises a digital counting circuit configured to count, for each channel, a number of switchings to the active state of the second signal of said channel.

[0030] According to one embodiment, the duration of the first time period is fixed.

[0031] According to one embodiment, after each switching to the active state of the second the weakest threshold channel signal, the first time period ends if the The first or second signal of a given channel with a threshold higher than the lowest threshold switches to the inactive state before the end of a second time period of fixed duration beginning with the first time period, and at the end of the second time period otherwise.

[0032] According to one embodiment, the reset circuit is configured so that the reset signal maintains the inactive state of the first and / or second signals for a constant duration each time that said reset signal forces a switch to the inactive state of these signals.

[0033] According to one embodiment, each digitization channel includes a comparator configured to receive the pulsed analog voltage and compare it to the threshold of the channel, and to provide the first digital signal of the channel.

[0034] According to one embodiment, each comparator receives the reset signal.

[0035] According to one embodiment, the reset circuit comprises, for each lane, a first circuit configured to receive the reset signal and the first signal of the lane, and to provide the corresponding second signal.

[0036] According to one embodiment, each first circuit comprises an RS type flip-flop having an initialization input configured to receive the first signal received by said first circuit, a reset input configured to receive a signal at least partly determined by the reset signal, and an output configured to provide the second corresponding signal.

[0037] According to one embodiment, the reset circuit includes a second circuit configured to receive the second signal from the lowest threshold channel, and to generate the reset signal from this second signal.

[0038] According to one embodiment, the second circuit comprises: a first monostable circuit configured to receive the second signal from the lowest threshold channel, and to provide a first pulse at each switching of said second signal to the active state; and a second monostable circuit configured to receive the first pulses and to provide a second pulse at the end of each first pulse.

[0039] According to one embodiment, the reset signal is determined from the second pulses.

[0040] Another embodiment provides for a particle counting detector comprising: a photodetector adapted to receive particles, for example photons from X-rays, and to provide a pulsed analog current determined by the particles received; a current-to-voltage conversion circuit configured to receive pulsed analog current and to provide a corresponding pulsed analog voltage laying; and a device such as above, configured to receive the pulsed analog voltage.

[0041] Another embodiment provides a photon-counting scanner comprising a plurality of particle-counting detectors such as above, wherein the particles are photons of X-ray radiation, and each photodetector comprises, for example, cadmium telluride. Brief description of the drawings

[0042] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0043] Fig. 1 represents schematically and in block form an example of a known particle counting detector;

[0044] [Fig.2] illustrates by means of chronograms an example of the operation of the detector of [Fig.1];

[0045] [Fig.3] schematically represents, in block form, an embodiment of a particle counting detector;

[0046] [Fig.4] illustrates by means of timing diagrams an example of the operation of the detector of [Fig.3];

[0047] [Fig.5] schematically represents, in block form, another embodiment of a particle counting detector;

[0048] [Fig.6] illustrates by means of timing diagrams an example of the operation of the detector of [Fig.5];

[0049] [Fig.7] schematically represents, in block form, another embodiment of a particle counting detector;

[0050] [Fig.8] illustrates by means of timing diagrams an example of the operation of the detector of [Fig.5];

[0051] [Fig.9] illustrates by means of chronograms another example of the operation of the detector of [Fig.1];

[0052] [Fig. 10] schematically represents, in block form, another embodiment of a particle counting detector;

[0053] [Fig.1 1] illustrates by means of timing diagrams an example of operation of the detector of [Fig. 10] according to one embodiment;

[0054] [Fig. 12] illustrates by means of timing diagrams another example of the operation of the detector of [Fig. 10] according to one embodiment;

[0055] Figure 13 schematically represents, in block form, a detailed embodiment of a digital pulse reset circuit. detector of the [Fig. 10];

[0056] [Fig. 14] schematically represents, in block form, another embodiment of a particle counting detector;

[0057] [Fig. 15] illustrates by means of timing diagrams an example of the operation of the detector of [Fig. 14] according to one embodiment; and

[0058] [Fig. 16] illustrates by means of timing diagrams an example of operation of the detector of [Fig. 14] according to another embodiment. Description of the implementation methods

[0059] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0060] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0061] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0062] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0063] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0064] Fig. 1 represents schematically and in block form an example of a known particle counting detector.

[0065] The DET detector includes a PD photodetector, a FRONT-END current-voltage conversion circuit and an EVAL-NUM device.

[0066] The PD photodetector is configured to receive particles to which the DET detector is sensitive, for example photons of X-ray radiation also called X-ray photons.

[0067] The PD photodetector is further configured to provide a pulsed analog current Idet determined by the X-ray photons it receives. For example, for each X-ray photon that the PD photodetector receives, the current Idet has a current pulse with a specific shape (width, amplitude, rise and fall slope, etc.). by the energy of the received X-ray photon.

[0068] The FRONT-END circuit is configured to receive the current Idet and to provide a corresponding pulsed analog voltage outFE. For example, at each current pulse of the current Idet, the voltage outFE exhibits a voltage pulse having a shape (width, amplitude, rise and fall slope, etc.) determined by the shape of the current pulse of the current Idet. For example, the FRONT-END circuit is configured so that the voltage outFE has a direct current (DC) component ref and an alternating current (AC) component exhibiting pulses determined by the pulses of the current Idet.

[0069] The EVAL-NUM device or circuit is configured to receive the outFE voltage and to evaluate the number and energy of X photons received by the PD photodetector from the outFE voltage, or at least provide signals enabling the evaluation of the number and energy of the X photons received.

[0070] More specifically, the EVAL-NUM circuit includes a NUM circuit and an EVAL circuit.

[0071] The NUM circuit is an analog-to-digital converter circuit configured to evaluate the amplitude of each voltage pulse of the received outFE voltage. The NUM circuit receives the outFE voltage and provides several digital signals, for example, several one-bit signals or binary signals, representing, for each pulse of the outFE voltage, the amplitude of that pulse.

[0072] The EVAL circuit is configured to count, from the binary signals provided by the NUM circuit and for at least a given X-ray photon energy value, the number of detected X-ray photons having an energy greater than or equal to that given energy value. In other words, the EVAL circuit is configured to provide the spectrum of X-ray photons detected by the PD photodetector, or at least to provide signals allowing the spectrum of detected X-ray photons to be reconstructed.

[0073] More specifically, the NUM circuit comprises N digitizing channels CHi, with i an index from 1 to N and N a positive integer greater than or equal to 1, preferably 2. For example, in [Fig. 1], N is equal to 8, and the NUM circuit comprises 8 CHi channels (CH1, CH2, ..., CH1, ..., CH7, and CH8 in [Fig. 1]). Each CHi channel is configured to receive the analog voltage outFE and to provide a pulsed digital signal outi (out1, out2, ..., outi, ..., out7, and out8 in [Fig. 1]) in an active state when the outFE voltage is greater than a threshold Thi of the channel (Th1, Th2, ..., Thi, Th7, and Th8 in [Fig. 1]), and in an inactive state when the outFE voltage is less than this threshold Thi. Each active state of the outi signal corresponds to a pulse of the outi signal.

[0074] For example, each CHi channel includes a COMPi circuit or comparator (COMP1, COMP2, ..., COMPi, ..., COMP7 and COMP8 in [Fig. 1]) configured for receive the outFE voltage and compare it to the Thi threshold of the channel, and provide the outi signal of the channel. For example, each comparator COMPi receives the threshold Thi, that is, a threshold voltage Thi.

[0075] For each channel CHi, the EVAL circuit, in practice a digital counting circuit, is configured in the example of [Fig. 1] to count the number of pulses of the outi signal, that is to say, the number of switching cycles to the active state of this outi signal. For example, the EVAL circuit includes, for each channel CHi, a counter COUNTi (COUNT1, COUNT2, ..., COUNTi, ..., COUNT7 and COUNT8 in [Fig. 1]) configured to receive the outi signal and to provide a digital output signal ci (c1, c2, ..., ci, ..., c7 and c8 in [Fig. 1]) incremented by one unit at each pulse of the received outi signal.

[0076] Figure 2 illustrates, by means of timing diagrams, an example of the operation of the DET detector of Figure 1. More specifically, Figure 2 represents the evolution of the outFE voltage as a function of time t, the thresholds Thi, and the evolution of the outi signals as a function of time t in a case where the DET circuit comprises N=4 CHi channels. The thresholds Thi (Thi, Th2, Th3, Th4 in Figure 2) increase with the index i, with the threshold Thi being the lowest of the Thi thresholds. In this example, the inactive state of the outi signals is the low state, and the active state (pulse) of the outi signals is the high state. In the example of Figure 2, the outFE voltage exhibits two successive pulses P1 and P2.

[0077] In [Fig. 2], during the PI pulse, the outFE voltage increases from its resting value, i.e., from the ref value, up to a maximum value determined by the energy of the corresponding X-ray photon received by the PD photodetector ([Fig. 1]). During this increase, the outFE voltage successively crosses the thresholds Thi, Th2, Th3, and Th4, which causes the signals outi, out2, out3, and out4 to switch to the active state successively. Then, the outFE voltage decreases from the maximum value of the PL pulse. During this decrease, the outFE voltage successively crosses the thresholds Th4, Th3, Th2, and Thi, which causes the signals out4, out3, out2, and outi to switch to the inactive state successively.

[0078] Similarly, during pulse P2, the outFE voltage increases from its previously reached minimum value to a maximum value determined by the energy of the corresponding X-ray photon received by the PD photodetector. During this increase, the outFE voltage successively crosses the thresholds Thi, Th2, Th3, and Th4, causing the signals outi, out2, out3, and out4 to switch to the active state successively. Then, the outFE voltage decreases from the maximum value of pulse PL. During this decrease, the outFE voltage successively crosses the thresholds Th4, Th3, Th2, and Thi, causing the signals out4, out3, out2, and outi to switch to the inactive state successively.

[0079] In [Fig.2], the two X photons corresponding to the two pulses PI and P2 are received one after the other with a duration between the reception of the first X photon and that of the second X photon which is sufficiently large so that the two corresponding pulses of the current Idet do not overlap or overlap very little, from which it follows that the voltage outFE falls below the threshold Thl between the two pulses PI and P2.

[0080] The signals outl to out4 are then such that, in this example, each of the corresponding signals cl to c4 is incremented twice.

[0081] It is then possible, from the signals cl to c4, to determine that two X photons having an energy greater than a value E4 have been received by the photodetector PD of the detector DET, the energy value E4 determining, with the FRONT-END circuit, the value of the threshold Th4.

[0082] By way of example, to reconstruct a histogram of the spectrum of X-ray photons received by the PD photodetector of the DET detector: - for each CHi channel with index i strictly less than N, the value indicated by the signal ci+1 of the CHi+1 channel is subtracted from that indicated by the signal ci of the CHi channel, and the result of this subtraction indicates the number of X photons received with an energy between an energy value Ei and an energy value Ei+1, the value Ei determining, with the FRONT-END circuit, the value of the threshold Thi of the CHi channel, and the value Ei+1 determining, with the FRONT-END circuit, the value of the threshold Thi+1 of the CHi+1 channel; and - for the CHi channel with index N, the value indicated by the signal ci indicates the number of X photons received with an energy greater than the energy value Ei.

[0083] In the DET detector described above, it is desirable that the COMPi comparators switch their output signals as quickly as possible, or, in other words, that these COMPi comparators be as fast as possible. Thus, at least during detection and counting phases, these COMPi comparators operate continuously in a high-power mode, that is, in a mode with higher power consumption than in a low-power mode where the COMPi comparators would be slower. For example, a detection and counting phase corresponds to a time window during which the detector is used to detect and count the particles it receives.

[0084] It would be desirable to reduce the consumption in the DET detector, without the COMPi converters being, at least during the switching of their output signals outi in the active state, slower than if they were operating in high consumption mode.

[0085] According to a first aspect, it is proposed here to take advantage of the particularities of the outFE voltage, or, in other words, of the fact that during a pulse of the outFE voltage, the outi signals switch successively to their active states starting from the index i equal to to 1.

[0086] First aspect

[0087] To reduce the power consumption of a particle counting detector of the type described in relation to Figures 1 and 2, a device NUM2 is proposed here, similar to the device NUM, but in which: - for i ranging from 2 to N, with N strictly greater than 1, the COMPi comparators are configured to operate selectively in a low-power mode and a high-power mode, and - a BOOST control circuit configured to control, for i ranging from 2 to N, each comparator COMPi in low power mode or in high power mode as a function of at least the outi signal of at least one of the channels CH1 to CHN, the BOOST circuit being, preferably, a purely combinational circuit without a memory function.

[0088] More particularly, the BOOST circuit controls the high and low consumption modes of the COMPi comparators for i from 2 to N so that each of these COMPi comparators is in high consumption mode when the outFE voltage reaches and then exceeds the threshold Thi of the COMPi comparator and that the consumption of the NUM1 device is less than that of the NUM device in which the COMPi comparators are kept permanently, at least during detection and counting phases, in high consumption mode.

[0089] According to one embodiment, the BOOST circuit is configured, at each outFE pulse, to switch, for i ranging from 2 to N, each comparator COMPi from low-power mode to high-power mode in response to an active switching of the outi signal of a CHi channel with an index i lower than that of that comparator COMPi. Preferably, the BOOST circuit is configured, at each outFE pulse, to switch, for i ranging from 2 to N, each comparator COMPi into high-power mode in response to an active switching of the outi-1 signal of the CHi-1 channel, or, alternatively, in response to an active switching of the outi signal of the CHi channel.

[0090] Thus, for i ranging from 2 to N, each comparator COMPi is in high consumption mode when the voltage outFE reaches and then exceeds the threshold Thi of this comparator COMPi.

[0091] According to one embodiment, the BOOST circuit is further configured, for each pulse and for each comparator COMPi that the BOOST circuit has switched to high-power mode during the rising edge of the pulse, to switch this comparator COMPi to low-power mode at the latest in response to a switching to the inactive state of the output signal of the CHI channel, and, for example, at the earliest in response to a switching to the active state of the output signal outi of this comparator. COMPi.

[0092] Thus, at each pulse, after switching to high power mode during the rising edge of the pulse a comparator COMPi of index i in the range from 2 to N, the BOOST circuit switches this comparator COMPi to low power mode at the latest at the end of the pulse outFE.

[0093] With regard to the COMPI comparator of channel CH1, according to one embodiment, it only operates in high consumption mode and is therefore not controlled by the BOOST circuit.

[0094] According to an alternative embodiment concerning the COMPI comparator, the latter is also configured to operate selectively in a low power mode and a high power mode, and the BOOST circuit is then configured to control the COMPI comparator in low power mode if the out2 signal is in the active state, and in high power mode otherwise.

[0095] Examples of embodiments of such a NUM1 circuit will now be described in relation to Figures 3 to 8.

[0096] Fig. 3 schematically represents, in block form, an embodiment of a particle-counting DET2 detector.

[0097] The DET2 detector shares many features with the DET detector of [Fig. 1], and only the differences between these two detectors, DET and DET2, are highlighted here. In other words, unless otherwise indicated, everything described for the DET detector of [Fig. 1] applies to the DET2 detector of [Fig. 3].

[0098] Thus, the DET2 detector includes the PD photodetector supplying the current Idet, and the FRONT-END circuit receiving the current Idet and supplying the voltage outFE.

[0099] The DET2 detector includes an EVAL-NUM2 device or circuit similar to the EVAL-NUM circuit of the DET detector in [Fig. 1] in that it includes the EVAL circuit and a NUM2 circuit similar to the NUM circuit. However, the NUM2 circuit or device differs from the NUM circuit in that: For i ranging from 2 to N, each COMPi comparator is configured to operate selectively in a high-power mode and in a low-power mode; and The NUM2 circuit also includes a BOOST circuit for controlling the comparators.

[0100] In the example of [Fig.3], the NUM2 circuit comprises N=4 CHi digitization channels, and the thresholds Thi are increasing with the index i.

[0101] By way of example, each COMPi comparator that is configured to operate selectively in low-power mode and in high-power mode receives a binary signal bi (b2, ..., bi, ..., bN in [Fig. 3]) of which a first binary state controls the COMPi comparator in low-power mode, and a second The binary state controls the comparator in high-power mode. The bi signals are provided by the BOOST circuit from at least one of the outi signals.

[0102] In this embodiment, the BOOST circuit is more particularly configured to control, for i ranging from 2 to N, each comparator COMPi in high consumption mode, for example by providing the signal bi corresponding to its second binary state, if the signal outi-1 of the channel CHi-1 is in the active state, and in low consumption mode otherwise, for example by providing the signal bi corresponding to its first binary state.

[0103] Put another way, in this embodiment, the BOOST circuit controls the high or low power consumption mode of each of the COMPi comparators with i ranging from 2 to N, only from the state of the outi-1 signal of the CHi-1 channel.

[0104] Put another way, for each comparator COMPi with i ranging from 2 to N, the comparator COMPi is in low power mode (bi in its first binary state) if the signal outi-1 is inactive, and is in high power mode (bi in its second binary state) if the signal outi-1 is active.

[0105] Thus, in this embodiment, the BOOST circuit receives the signals outi for i ranging from 1 to N.

[0106] In this example, the COMPI comparator operates only in high power mode and therefore does not receive any bl signal from the BOOST circuit.

[0107] However, in another example not shown, the comparator COMPI is configured to operate selectively in high-power or low-power mode, and the BOOST circuit is configured to control the comparator COMPI in high-power mode if the out2 signal is inactive, and in low-power mode otherwise. For example, the BOOST circuit then provides a binary signal bl to the comparator COMPI, a first binary state of the signal bl controlling the comparator COMPI in low-power mode, and a second binary state of the signal bl controlling the comparator COMPI in high-power mode.

[0108] By way of example, as illustrated in [Fig. 3] for the COMP4 circuit of the NUM2 circuit, each comparator COMPi of the NUM2 circuit includes an open-loop amplifier OTA, the amplifier receiving the outFE voltage on a first input, and the corresponding Thi voltage on a second input, and providing the corresponding outi signal. By way of example, this outi signal can be directly supplied at the output of the comparator COMPi. By way of alternative example, as illustrated in [Fig. 3], the outi signal from the output of the amplifier OTA is shaped before being transmitted to the corresponding output of the comparator COMPi, for example by a buffer circuit BUFF consisting, for example, of two inverters INV in series. By way of another alternative example, the output of the amplifier OTA can be coupled to the corresponding output of the COMPi comparator by a single INV inverter.

[0109] Figure 4 illustrates, by means of timing diagrams, an example of the operation of the detector DET2 of [Fig. 3]. More specifically, [Fig. 4] represents the evolution of the outFE voltage as a function of time t, the thresholds Thi, the evolution of the outi signals as a function of time t, and the evolution of the bi signals as a function of time t in a case where the DET circuit comprises N=4 CHi channels. The thresholds Thi (Thl, Th2, Th3, Th4 in [Fig. 4]) increase with the index i, with the Thl threshold being the lowest of the Thi thresholds. In this example, the inactive state of the outi signals is the low state, and the active (pulse) state of the outi signals is the high state. In this example, each bi signal drives the comparator COMPi in low-power mode when it is low, and in high-power mode when it is high. In the example of [Fig. 4], the outFE voltage has a single PL pulse

[0110] At a time t0 before the start of the PI pulse, the outFE voltage is below the threshold Thl, so all the outi signals are in the inactive state (low state in [Fig. 4]). Furthermore, since all the outi signals are in the inactive state, all the bi signals for i from 2 to N are in their first binary states (the low state in [Fig. 4]). As a result, the COMPi comparators for i from 2 to N are all controlled in low-power mode.

[0111] The PI pulse begins after time t0, and, at a time t1 later than time t0, the outFE voltage becomes greater than the threshold Thl. As a result, the outi signal switches to the active state (high state in [Fig. 4]). In particular, in this example where the COMPI comparator is always operating in high-power mode, this switching of the outi signal is faster than if the COMPI comparator were operating in low-power mode.

[0112] Switching the outi signal to the active state causes the COMP2 comparator to switch, by the BOOST circuit ([Fig.3]), into high consumption mode, or, in other words, switching the b2 signal to its second binary state (high state in [Fig.4]).

[0113] At a time t2 after time t1, the voltage outFE becomes greater than the threshold Th2. As a result, the signal out2 switches to the active state (high state in [Fig. 4]). Since the comparator COMP2 was switched to high-power mode at time t1, this switching of the signal out2 is faster than if the comparator COMP2 were operating in low-power mode.

[0114] Switching the out2 signal to the active state causes the COMP3 comparator to switch, by the BOOST circuit ([Fig.3]), into high consumption mode, or, in other words, switching the b3 signal to its second binary state (high state in [Fig.4]).

[0115] At a time t3 later than time t2, the voltage outFE becomes greater than the threshold Th3 and the out3 signal switch to the active state (high state in [Fig.4]) while the comparator C0MP3 is controlled in high consumption mode from time t2. The switching of the out3 signal to the active state causes the comparator COMP4 to switch, by the BOOST circuit ([Fig.3]), to high consumption mode, or, in other words, the switching of the b4 signal to its second binary state (high state in [Fig.4]).

[0116] At a time t4 later than time t3, the voltage outFE becomes greater than the threshold Th4 and the signal out4 switches to the active state (high state in [Fig.4]) while the comparator COMP4 is controlled in high consumption mode since time t3.

[0117] At a time t5 after time t4, during the falling edge of the outFE pulse, the outFE voltage falls below the threshold Th4 and the out4 signal switches to the inactive state (low state in [Fig. 4]). During this switching of the out4 signal, the comparator COMP4 is always controlled in high-power mode, and this switching is therefore faster than if the comparator COMP4 had been controlled in low-power mode.

[0118] At a time t6 after time t5, during the falling edge of the outFE pulse, the outFE voltage falls below the threshold Th3 and the out3 signal switches to the inactive state (low state in [Fig. 4]) while the comparator COMP3 is still driven in high-power mode. The switching of the out3 signal to the inactive state causes the comparator COMP4 to switch to low-power mode via the BOOST circuit ([Fig. 3]), or, in other words, the switching of the b4 signal to its first binary state (low state in [Fig. 4]).

[0119] At a time t7 after time t6, during the falling edge of the outFE pulse, the outFE voltage falls below the threshold Th2 and the out2 signal switches to the inactive state (low state in [Fig. 4]) while the comparator COMP2 is still driven in high-power mode. The switching of the out2 signal to the inactive state causes the comparator COMP3 to switch to low-power mode via the BOOST circuit ([Fig. 3]), or, in other words, the switching of the b3 signal to its first binary state (low state in [Fig. 4]).

[0120] At a time t8 after time t7, during the falling edge of the outFE pulse, the outFE voltage falls below the threshold Thl and the outl signal switches to the inactive state (low state in [Fig. 4]) while the comparator COMP1 is still controlled in high-power mode. The switching of the outl signal to the inactive state causes the comparator COMP2 to switch to low-power mode via the BOOST circuit ([Fig. 3]), or, in other words, the switching of the b2 signal to its first binary state (low state in [Fig. 4]).

[0121] After time t8, the situation is the same as at time t0.

[0122] Although an example has been described here in the case where comparator COMP1 is Still in high-power mode, a person skilled in the art can adapt the description of this example to the case where comparator C0MP1 is controlled in high-power mode when signal out2 is inactive, and in low-power mode otherwise. Using the example in [Fig. 4], comparator C0MP1 would then be in high-power mode until time t2, in low-power mode from time t2 to time t7, and in high-power mode after time t7.

[0123] Figure 5 schematically represents, in block form, another embodiment of a particle-counting DET2 detector. In Figure 5, only the NUM2 circuit of the DET2 detector is shown; the rest of the DET2 detector in Figure 5 is identical to that in Figure 3. Furthermore, the NUM2 circuit in Figure 5 is similar to that in Figure 3, and only the differences between these two circuits are highlighted here.

[0124] In this embodiment, the BOOST circuit is more particularly configured to control, for i ranging from 2 to N, each comparator COMPi in high consumption mode, for example by providing the bi signal corresponding to its second binary state, if the outl signal of channel CH1 is in the active state, and in low consumption mode otherwise, for example by providing the bi signal corresponding to its first binary state.

[0125] In other words, in this embodiment, the BOOST circuit controls the high or low power consumption mode of each of the COMPi comparators with i ranging from 2 to N, solely from the state of the outl signal of channel CH1.

[0126] Put another way, for each comparator COMPi with i ranging from 2 to N, the comparator COMPi is in low power mode (bi in its first binary state) if the outl signal is inactive, and is in high power mode (bi in its second binary state) if the outl signal is active.

[0127] Thus, in this embodiment, the BOOST circuit receives the outl signal, but does not receive the outi signals from the CHi channels with index i strictly greater than 2.

[0128] In this example, the COMPI comparator operates only in high-power mode and therefore receives no bl signal from the BOOST circuit. Furthermore, the BOOST circuit does not receive the out2 signal.

[0129] However, in another example not shown, the COMPI comparator is configured to operate selectively in high-power or low-power mode, and the BOOST circuit is configured to drive the COMPI comparator in high-power mode if the out2 signal is inactive, and in low-power mode otherwise. For example, the BOOST circuit then provides a binary signal bl to the COMPI comparator, a first binary state of the signal bl driving the COMPI comparator into low-power mode, and a second The binary state of the signal bl controls the comparator COMP1 in high-power mode. Furthermore, the BOOST circuit then receives, for example, the signal out2.

[0130] Figure 6 illustrates, using timing diagrams, an example of the operation of the detector DET2 of Figure 5. More specifically, Figure 6 represents the evolution of the voltage outFE as a function of time t, the thresholds Thi, the evolution of the signals outi as a function of time t, and the evolution of the signals bi as a function of time t in a case where the DET circuit comprises N=4 channels CHi. The thresholds Thi (Thl, Th2, Th3, Th4 in Figure 6) increase with the index i. In this example, the inactive state of the signals outi is the low state, and the active (pulse) state of the signals outi is the high state. In this example, each signal bi controls the comparator COMPi in low-power mode when it is low, and in high-power mode when it is high. In the example of [Fig.6], the outFE voltage presents a single PL pulse.

[0131] At time t0 before the start of the PI pulse, the outFE voltage is below the threshold Thl, so all the outi signals are in the inactive state (low state in [Fig. 6]). Furthermore, since all the outi signals are in the inactive state, all the bi signals for i from 2 to N are in their first binary states (the low state in [Fig. 6]). As a result, the COMPi comparators for i from 2 to N are all controlled in low-power mode.

[0132] The PI pulse begins after time t0, and, at a time t1 later than time t0, the outFE voltage becomes greater than the threshold Thl. As a result, the outi signal switches to the active state (high state in [Fig. 6]). In particular, in this example where the COMPI comparator is always operating in high-power mode, this switching of the outi signal occurs while the COMPI comparator is in high-power mode.

[0133] Switching the outi signal to the active state causes the COMPi comparators to be switched by the BOOST circuit ([Fig.5]), for i from 2 to N=4, into high consumption mode, or, in other words, switching the bi signals, for i from 2 to N=4, to the second binary state (high state in [Fig.6]).

[0134] After time t1, the voltage outFE increases and successively exceeds the thresholds Th2, Th3, and Th4 before reaching a maximum value (peak of the PI pulse), resulting in the signals out2, out3, and out4 switching successively to the active state. These switching events of the out2, out3, and out4 signals occur while the corresponding comparators COMP2, COMP3, and COMP4 are controlled in high-power mode.

[0135] Then the outFE voltage decreases and falls successively below the thresholds Th4, Th3, and Th2, resulting in the out4, out3, and out2 signals switching successively to the inactive state. These switching of the out4, out3, and out2 signals occurs while the corresponding comparators C0MP4, C0MP3 and C0MP2 are controlled in high power consumption mode.

[0136] The outf voltage continues to decrease until it falls below the threshold Thl at time t2. As a result, the outl signal switches to the inactive state, while comparator COMP1 is in high-power mode. The switching of the outl signal to the inactive state causes the comparators COMPi, for i ranging from 2 to N=4, to switch to low-power mode by the BOOST circuit ([Fig. 5]), or, in other words, the bi signals, for i ranging from 2 to N=4, to switch to the first binary state (low state in [Fig. 6]).

[0137] Although an example has been described here in the case where the comparator COMPI is always in high-power mode, a person skilled in the art can adapt the description of this example to the case where the comparator COMPI is controlled in high-power mode when the out2 signal is inactive, and in low-power mode otherwise. Referring back to the example in [Fig. 6], the comparator COMPI would then be in high-power mode until the out2 signal switches to the active state on the rising edge of the PI pulse, in low-power mode as long as the out2 signal remains active, and in high-power mode after the out2 signal switches to the inactive state on the falling edge of the PL pulse

[0138] Figure 7 schematically represents, in block form, another embodiment of a particle-counting DET2 detector. In Figure 7, only the NUM2 circuit of the DET2 detector is shown; the rest of the DET2 detector in Figure 7 is identical to that in Figure 3. Furthermore, the NUM2 circuit in Figure 7 is similar to that in Figure 3, and only the differences between these two circuits are highlighted here.

[0139] In this embodiment, the BOOST circuit is more specifically configured to: - for i ranging from 2 to N-1 and N strictly greater than 2, control each comparator COMPi in high-power mode if the outi-1 signal of channel CHi-1 is active while the outi+1 signal of channel CHi+1 is inactive, and in low-power mode otherwise; and - control the COMPN comparator in high power mode if the outN-1 signal of the CHN-1 channel is active, and in low power mode otherwise.

[0140] Put another way, in this embodiment, the BOOST circuit controls the high or low consumption mode of each of the COMPi comparators with i ranging from 2 to Nl, only from the state of the outi-1 and outi+1 signals of the channels with indices immediately lower and immediately higher with respect to the CHi channel of the COMPi comparator.

[0141] Put another way, for each comparator COMPi with i ranging from 2 to Nl, the COMPi comparator is in high power mode (bi in its second binary state) if the outi-1 signal is active while the out+1 signal is inactive, and is in low power mode (bi in its first binary state) otherwise.

[0142] Put another way, for each comparator COMPi with i ranging from 2 to Nl: - During a rising edge of the outFE voltage, switching the outi-1 signal of the immediately lower index channel to the active state causes the COMPi comparator to switch to high-power mode, then switching the outi+1 signal of the immediately higher index channel to the active state causes the COMPi comparator to switch to low-power mode; and - during a falling edge of the outFE voltage, switching the outi+1 signal of the immediately higher index channel to the inactive state causes the COMPi comparator to switch to high power mode, then switching the outi-1 signal of the immediately lower index channel to the inactive state causes the COMPi comparator to switch to low power mode.

[0143] Thus, in this embodiment, the BOOST circuit receives the signals outi for i from 1 to N. In addition, the BOOST circuit provides the signals bi, at least for i from 2 to N.

[0144] In this example, the COMPI comparator is configured to operate selectively in high-power or low-power mode, and the BOOST circuit is configured to drive the COMPI comparator in high-power mode if the out2 signal is inactive, and in low-power mode otherwise. As an example, the BOOST circuit then provides the binary signal bl to the COMPI comparator.

[0145] In another example not shown, the COMPI comparator operates only in high power mode and therefore does not receive any bl signal from the BOOST circuit.

[0146] Figure 8 illustrates, by means of timing diagrams, an example of the operation of the DET2 detector of Figure 7. More specifically, Figure 8 represents the evolution of the outFE voltage as a function of time t, the thresholds Thi, the evolution of the outi signals as a function of time t, and the evolution of the bi signals as a function of time t in a case where the DET circuit comprises N=4 CHi channels. The thresholds Thi (Thl, Th2, Th3, Th4 in Figure 4) increase with the index i, with the Thl threshold being the lowest of the Thi thresholds. In this example, the inactive state of the outi signals is the low state, and the active (pulse) state of the outi signals is the high state. In this example, each bi signal drives the comparator COMPi in low-power mode when it is low, and in high-power mode when it is high. In the example in [Fig.8], the voltage outFE exhibits a single pulse PL

[0147] At time t0 before the start of the PI pulse, the outFE voltage is below the threshold Thl, so all the outi signals are in the inactive state (low state in [Fig. 8]). Furthermore, since all the outi signals are in the inactive state, all the bi signals for i from 2 to N are in their first binary states (the low state in [Fig. 8]), and the bl signal is in its second binary state (the high state in [Fig. 8]) because the out2 signal is in the inactive state. It follows that the COMPi comparators for i from 2 to N are all controlled in low-power mode, and that the COMPI comparator is controlled in high-power mode.

[0148] The PI pulse begins after time t0, and, at a time t1 later than time t0, the outFE voltage becomes greater than the threshold Thl. As a result, the outi signal switches to the active state while the comparator COMP1 operates in high-power mode. Furthermore, the switching of the outi signal to the active state causes the comparator COMP2 to switch to high-power mode by the BOOST circuit, or, in other words, the b2 signal to switch to its second binary state.

[0149] At a time t2 after time t1, the voltage outFE becomes greater than the threshold Th2 and the signal out2 switches to the active state while the comparator COMP2 is controlled in high-power mode. The switching of the signal out2 to the active state causes the comparator COMP3 to switch, by the BOOST circuit, to high-power mode (switching the signal b3 to its second binary state) and the comparator COMPI to low-power mode (switching the signal bl to its first binary state).

[0150] At a time t3 after time t2, the voltage outFE becomes greater than the threshold Th3 and the signal out3 switches to the active state while the comparator COMP3 is controlled in high-power mode. The switching of the signal out3 to the active state causes the comparator COMP4 to switch, by the BOOST circuit, to high-power mode (switching the signal b4 to its second binary state) and the comparator COMP2 to low-power mode (switching the signal b2 to its first binary state).

[0151] At a time t4 after time t3, the voltage outFE becomes greater than the threshold Th4 and the signal out4 switches to the active state while the comparator COMP4 is controlled in high-power mode. The switching of the signal out4 to the active state causes the comparator COMP3 to switch, by the BOOST circuit, to low-power mode (switching the signal b3 to its first binary state).

[0152] At a time t5 after time t4, during the falling edge of the pulse outFE, the voltage outFE falls below the threshold Th4 and the signal out4 switches to the inactive state while the comparator COMP4 is still driven in high-power mode. Furthermore, the switching of the signal out4 to the inactive state causes the com mutation, by the BOOST circuit, of the comparator C0MP3 in high power consumption mode (switching of the b3 signal to its second binary state)

[0153] At a time t6 after time t5, during the falling edge of the outFE pulse, the outFE voltage falls below the threshold Th3 and the out3 signal switches to the inactive state while the comparator COMP3 is still controlled in high-power mode. The switching of the out3 signal to the inactive state causes the BOOST circuit to switch the comparator COMP4 to low-power mode (switching the b4 signal to its first binary state) and the comparator COMP2 to high-power mode (switching the b2 signal to its second binary state).

[0154] At a time t7 after time t6, during the falling edge of the pulse outFE, the voltage outFE falls below the threshold Th2 and the signal out2 switches to the inactive state while the comparator COMP2 is still controlled in high-power mode. The switching of the signal out2 to the inactive state causes the comparator COMP3 to switch, by the BOOST circuit, to low-power mode (switching the signal b3 to its first binary state) and to high-power mode (switching the signal bl to its second binary state).

[0155] At a time t8 after time t7, during the falling edge of the outFE pulse, the outFE voltage falls below the threshold Thl and the outl signal switches to the inactive state while the comparator COMP1 is controlled in high-power mode. The switching of the outl signal to the inactive state causes the comparator COMP2 to switch to low-power mode via the BOOST circuit (switching the b2 signal to its first binary state).

[0156] After time t8, the situation is the same as at time t0.

[0157] Although an example has been described here in the case where comparator COMP1 is controlled in high power mode when signal out2 is in the inactive state, and in low power mode otherwise, a person skilled in the art can adapt the description of this example to the case where comparator COMP1 is always in high power mode.

[0158] Several embodiments and variants have been described with reference to Figures 3 to 8. A person skilled in the art will be able to combine aspects of these embodiments and variants. For example, a person skilled in the art will be able to provide, in an N-channel NUM2 device, that comparators of the higher index channels are selectively controlled in high-power or low-power mode as described with reference to Figures 3 and 4, that is, for each of these comparators, solely from the output signal of the comparator with the immediately lower index, and that the other comparators, other than that of the index channel, are selectively controlled in high-power or low-power mode as described with reference to Figures 7 and 8. More generally, in a NUM2 circuit with N channels, a person skilled in the art is able to foresee that, for i going from 2 to N, a part of the comparators COMPi are selectively in high or low consumption mode according to one of the ways described in relation to figures 3 to 8, and that another part of these comparators COMPi are controlled according to another of the ways described in relation to figures 3 to 8.

[0159] A first aspect of a NUM2 circuit has been described above, which reduces power consumption compared to the NUM circuit while maintaining the same switching speed of the COMPi comparators. In addition, the first aspect of the NUM2 circuit increases the switching speed of the COMPi comparators during switching compared to the NUM circuit, while maintaining the same average power consumption.

[0160] Referring again to the DET detector in [Fig. 1], [Fig. 9] illustrates, by means of timing diagrams, an example of the operation of this DET detector. More specifically, [Fig. 9] represents the evolution of the outFE voltage as a function of time t, the thresholds Thi, and the evolution of the outi signals as a function of time t in a case where the DET circuit comprises N=4 CHi channels. The thresholds Thi (Th1, Th2, Th3, Th4 in [Fig. 2]) increase with the index i. In this example, the inactive state of the outi signals is the low state, and the active (pulse) state of the outi signals is the high state.

[0161] In the example in [Fig.9], the voltage outFE has two successive pulses PI and P2. However, compared to [Fig.2], in the example in [Fig.9], the two X photons corresponding to the two pulses PI and P2 are received one after the other with a duration between the reception of the first X photon and that of the second X photon such that the two corresponding pulses of the current Idet overlap and, between the two pulses PI and P2, the voltage outFE does not fall below the threshold Thl, and more particularly the thresholds Thl and Th2 in this example.

[0162] More particularly, in [Fig.9], during the PI pulse, the voltage outFE increases from its resting value ref up to a maximum value, and successively crosses the thresholds Thl, Th2, Th3 and Th4, which causes the switching to the active state of the signals outi, out2, out3 and out4 successively.

[0163] Then, the outFE voltage decreases from the maximum value of the PI pulse to a minimum value reached at the beginning of the following P2 pulse and between the thresholds Th2 and Th3. During this decrease, the outFE voltage successively crosses the thresholds Th4 and Th3 but does not fall back below the thresholds Th2 and Thl, from which it follows that the out4 and out3 signals successively switch to the inactive state while the out2 and outi signals remain in the active state.

[0164] Then, during pulse P2, the outFE voltage increases from the previously reached minimum value to a maximum value. During this increase, the outFE voltage successively crosses the Th4 and Th3 thresholds, which causes the com Signals out3 and out4 are successively switched to the active state, while the other signals out2 and out3 remain active. Then, the outFE voltage decreases from the maximum value of the P2 pulse. During this decrease, the outFE voltage successively crosses the thresholds Th4, Th3, Th2, and Thl, which causes signals out4, out3, out2, and outl to switch to the inactive state successively.

[0165] The signals outl to out4 obtained in the example of [Fig.9] do not allow for a proper evaluation of the number and energy of the X photons received.

[0166] By way of example, using the histogram reconstruction example given in relation to [Fig.2], the corresponding signals c1 to c4 would indicate that: 2 X-ray photons with an energy greater than E4 were received; 0 X-ray photons with an energy between E4 and E3 were received; -1 X-ray photon with an energy between E2 and E3 was received; and 0 X-ray photons with an energy between El and E2 were received.

[0167] It would be desirable to have a particle counting detector which makes it possible to correctly evaluate the number and energy of the particles it receives when the probability of receiving two particles close together in time increases, so as to avoid the errors and / or counting inconsistencies illustrated in relation to [Fig.9].

[0168] A second aspect provides for an EVAL-NUM1 circuit similar to the EVAL-NUM circuit, but which makes it possible to achieve this objective.

[0169] Second aspect

[0170] Fig. 10 schematically represents, in block form, an embodiment of a particle counting detector DET1.

[0171] The DET1 detector shares many features with the DET detector of [Fig. 1], and only the differences between these two detectors, DET and DET1, are highlighted here. In other words, unless otherwise stated, everything described for the DET detector of [Fig. 1] applies to the DET1 detector of [Fig. 10].

[0172] Thus, the detector DET1 includes the photodetector PD supplying the current Idet, and the FRONT-END circuit receiving the current Idet and supplying the voltage outFE.

[0173] The DET1 detector includes an EVAL-NUM1 device or circuit similar to the EVAL-NUM circuit of the DET detector in [Fig. 1] in that it includes the NUM circuit and the EVAL circuit. However, the EVAL-NUM1 circuit differs from the NUM-EVAL circuit in that it further includes a PULSE-RESET device or circuit.

[0174] The EVAL-NUM 1 circuit is, like the EVAL-NUM circuit, configured to receive the outFE voltage and to evaluate the number and energy of the X photons received by the PD photodetector from the outFE voltage, or at least to provide signals enabling the evaluation of the number and energy of the X photons received.

[0175] In the EVAL-NUM1 device, as in [Fig. 1], the NUM circuit is a circuit of The analog-to-digital converter is configured to evaluate the amplitude of each voltage pulse of the received outFE voltage. The NUM circuit provides several digital signals outi, for example, several binary signals, representing, for each pulse of the outFE voltage, the amplitude of that pulse. In the example in [Fig. 10], the NUM circuit includes N=4 digitization channels CHi, and the thresholds Thi are increasing with the index i.

[0176] Compared to the EVAL-NUM device, in the EVAL-NUM1 device, the output signals are not directly supplied to the EVAL circuit. In fact, in the EVAL-NUM1 circuit, the PULSE-RESET circuit, which is a digital pulse reset circuit, is configured to receive the output signals and to supply corresponding output signals. These output signals are then supplied to the EVAL circuit.

[0177] More specifically, for each CHi channel, the PULSE-RESET circuit is configured to receive the outi signal from that channel, and to generate the corresponding outci signal so that the outci signal is in the active state when the outi signal is in the active state and is in the inactive state when the outi signal is in the inactive state.

[0178] Furthermore, the PULSE-RESET circuit is configured to provide a digital pulse reset signal rst. More specifically, the rst signal is configured to force, each time the outci signal is switched to the active state, the switching of the outci signals to the inactive state at the end of a time period tmpl that begins when the outci signal is switched to the active state. Thus, although the rst signal is shown in [Fig. 10] as an output of the PULSE-RESET circuit, in practice, in the embodiment of [Fig. 10] where the rst signal resets the digital pulses of the outci signals, this rst signal is an internal signal of the PULSE-RESET circuit.

[0179] According to one embodiment, the value of the period tmpl is fixed, or, in other words, constant. By way of example, the duration tmpl is determined empirically, by tests or simulations, and depends on (or is determined by) the FRONT-END circuit and the average energy of the detected particles.

[0180] Preferably, the PULSE-RESET circuit is configured so that the rst signal maintains the inactive state of the outci signals for a constant duration tmp2 each time the rst signal switches these outci signals to the inactive state at the end of a corresponding tmpl period. For example, the duration tmp2 is constant. For example, the duration tmp2 is determined empirically, by trials or simulations. For example, the duration tmp2 is chosen to be as short as possible but large enough to be taken into account by the EVAL circuit, for example by the COUNTi counters of the EVAL circuit (see [Fig. 1]). For example, the duration tmp2 is at least ten times shorter than the average width of the voltage pulses of the outFE voltage, the width of an outFE voltage pulse being, for example, the time between the instant when the pulse crosses the lowest threshold Thi and the instant when the pulse falls below this threshold Thi. As an example, for a given FRONT-END circuit and for particles corresponding to X photons, the average width of the pulses outFE is about 20 ns, and, for example, the duration tmp2 is then about 2 ns.

[0181] The outci signals (outcl, ..., outci, ..., outc4 in [Fig. 10]) are supplied to the EVAL circuit of detector DET1, instead of the outi signals that were supplied to the EVAL circuit of detector DET in [Fig. 1]. Thus, the EVAL circuit here is configured to count, for each channel CHi, the number of pulses of the outci signal, that is, the number of times this outci signal switches to the active state. For example, the EVAL circuit provides, for each channel CHi, a digital output signal ci (cl, ..., ci, ..., c4 in [Fig. 10]) incremented by one with each received pulse of the outci signal.

[0182] By way of example, as illustrated in [Fig. 10] for the COMP4 circuit of the NUM circuit, each comparator COMPi of the NUM circuit comprises an open-loop OTA amplifier, the amplifier receiving the outFE voltage on a first input, and the corresponding single Thi on a second input, and providing the corresponding outi signal. By way of example, this outi signal can be directly supplied to the output of the NUM circuit. By way of alternative example, as illustrated in [Fig. 10], the outi signal from the amplifier output is shaped before being transmitted to the corresponding output of the NUM circuit, for example by a BUFF buffer circuit consisting, for example, of two INV inverters in series. By way of another alternative example, the output of the OTA amplifier can be coupled to the corresponding output of the NUM circuit by a single INV inverter.

[0183] Figure 11 illustrates, by means of timing diagrams, an example of the operation of detector DET1 of Figure 10 according to an embodiment in which the signal rst is a reset signal for the signals (or pulses) outci. More specifically, Figure 5 illustrates: the evolution of the outFE voltage as a function of time t, the thresholds Thi, the evolution of the corresponding signals outi as a function of time t, and the evolution of the corresponding signals outci as a function of time t.

[0184] In this example, N is equal to 4, the thresholds Thi have the same values ​​as in [Fig. 2] and 3, and the outFE voltage has the same shape as the outFE voltage of [Fig. 2] and includes in particular the two successive pulses PI and P2. In this example, it is the high state of the rst signal that forces the outci signals to the inactive state, the other state of the rst signal having no influence on the outci signals.

[0185] During the PI pulse, the outFE voltage increases from its resting value ref to a maximum value. During this increase, the outFE voltage successively crosses the thresholds Thi, Th2, Th3, and Th4, causing the outi, out2, out3, and out4 signals to switch to the active state successively. The PULSE-RESET circuit ( [Fig. 10]) then switches the corresponding signals outcl, outc2, outc3, and outc4 to the active state at the same times (neglecting propagation delays in the PULSE-RESET circuit) as the signals outl, out2, out3, and out4 respectively. Furthermore, switching the outcl signal to the active state marks the beginning of a tmpl period.

[0186] Then, while the period tmpl has not yet expired in this example, the voltage outFE decreases from the maximum value of the PI pulse and successively crosses the thresholds Th4, Th3, Th2, and Thl, causing the signals out4, out3, out2, and outl to switch to the inactive state successively. The PULSE-RESET circuit ([Fig. 10]) then successively switches the corresponding signals outc4, outc3, outc2, and outcl to the inactive state at the same times (neglecting propagation delays in the PULSE-RESET circuit) as the signals out4, out3, out2, and outl, respectively.

[0187] Between the two pulses PI and P2, while the outFE voltage is below the Thl threshold, the tmpl time period expires, causing the rst signal to transition to a state (the high state in this example) that forces the outci signals to the inactive state. Since the outci signals are already in the inactive state, the rst signal has no influence on the operation of the DET1 detector. The rst signal is then switched to its other state (the low state in this example), for example, at the end of the tmp2 time period.

[0188] Then the P2 pulse begins and the outFE voltage increases from a value below the Thl threshold to a maximum value. During this increase, the outFE voltage successively crosses the Thl, Th2, Th3, and Th4 thresholds, causing the outl, out2, out3, and out4 signals to switch to the active state successively, and thus the outl, out2, out3, and out4 signals to switch to the active state successively and at the same times (neglecting propagation delays in the PULSE-RESET circuit) as the outl, out2, out3, and out4 signals respectively. Furthermore, although not illustrated in [Fig. 5], the switching of the outcl signal to the active state during the second P2 pulse marks the beginning of a new tmpl period.

[0189] Next, the outFE voltage decreases from the maximum value of the pulse P2. During this decrease, the outFE voltage successively crosses the thresholds Th4, Th3, Th2 and Thl, which causes the switching to the inactive state of the signals out4, out3, out2 and outl successively, and the switching to the inactive state of the signals outc4, outc3, outc2 and outcl successively and at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals out4, out3, out2 and outl respectively.

[0190] The example in [Fig. 5] shows that, when the time separating the reception of two successive X-ray photons is long enough for the voltage outFE to fall below the threshold Thl between pulses PI and P2, the PULSE-RESET circuit, and in particular the signal rst it generates, does not affect the proper functioning of the detector DET1 in relation to the DET detector, the outci signals are then identical to the outi signals.

[0191] Figure 12 illustrates, by means of timing diagrams, an example of the operation of detector DET1 of Figure 10 according to an embodiment in which the signal rst is a reset signal for the signals (or pulses) outci. More specifically, Figure 12 illustrates: the evolution of the outFE voltage as a function of time t, the thresholds Thi, the evolution of the corresponding signals outi as a function of time t, and the evolution of the corresponding signals outci as a function of time t.

[0192] In this example, N is equal to 4, the thresholds Thi have the same values ​​as in [Fig. 2] and 3, and the voltage outFE has the same shape as the voltage outFE of [Fig. 3] and includes in particular the two successive pulses PI and P2. In this example, it is the high state of the signal rst that forces the signals outci to the inactive state, the other state of the signal rst having no influence on the signals outci.

[0193] During the PI pulse, the outFE voltage increases from its resting value ref to a maximum value. During this increase, the outFE voltage successively crosses the thresholds Thi, Th2, Th3, and Th4, causing the signals outi, out2, out3, and out4 to switch to the active state successively. The PULSE-RESET circuit ([Fig. 10]) then switches the corresponding signals outci, outc2, outc3, and outc4 to the active state at the same instants (neglecting propagation delays in the PULSE-RESET circuit) as the signals outi, out2, out3, and out4, respectively. Furthermore, the switching of the outci signal to the active state marks the beginning of a tmpl period.

[0194] Then, while the period tmpl has not yet expired in this example, the voltage outFE decreases from the maximum value of the PI pulse, and successively crosses the thresholds Th4 and Th3, but does not fall below the thresholds Th2 and Thi. As a result, the signals out4 and out3 switch successively to the inactive state, but the signals out2 and outi remain in the active state. Moreover, the corresponding signals outc4 and outc3 switch successively to the inactive state at the same times (neglecting propagation delays) as the respective signals out4 and out3, the signals outc2 and outci remaining, like the signals out2 and outi, in the active state.

[0195] Between the two pulses PI and P2, while the outFE voltage is at a value between the thresholds Th3 and Th2, the tmpl duration expires, causing the rst signal to transition to a state (the high state in this example) that forces the outci signals to the inactive state. Since the outc4 and outc3 signals are already in the inactive state, the rst signal has no influence on these signals. However, the rst signal forces the outc2 and outci signals to switch to the inactive state, even though the out2 and outi signals are in the active state. The rst signal is then switched to its other state (the state (low in this example), for example at the end of the tmp2 duration. Once the rst signal has returned to its low state, since the out2 and outl signals are still active, the PULSE-RESET circuit switches the corresponding outc2 and outcl signals to the active state. Although not illustrated in [Fig. 12], this switching of the outcl signal to the active state at the end of the high state of the rst signal marks the beginning of a new tmpl period.

[0196] Then the pulse P2 starts and the voltage outFE increases to a maximum value. During this increase, the voltage outFE successively crosses the thresholds Th3 and Th4, which causes the switching to the active state of the signals out3 and out4 successively, and therefore the switching to the active state of the signals outc3 and out4 successively and at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals out3 and out4 respectively.

[0197] Next, the outFE voltage decreases from the maximum value of the pulse P2. During this decrease, the outFE voltage successively crosses the thresholds Th4, Th3, Th2 and Thl, which causes the switching to the inactive state of the signals out4, out3, out2 and outl successively, and the switching to the inactive state of the signals outc4, outc3, outc2 and outcl successively and at the same times (neglecting the propagation delays in the PULSE-RESET circuit) as the signals out4, out3, out2 and outl respectively.

[0198] The example in [Fig. 12] shows that, when the time separating the reception of two successive X photons is too short for the voltage outFE to fall below the threshold Thl between the pulses PI and P2, the PULSE-RESET circuit, and in particular the signal rst that it generates, makes it possible to force the reset of the signals outci that have not returned to the inactive state between the two pulses PI and P2.

[0199] Thus, since it is the outci signals that are supplied to the EVAL circuit, each of the ci signals is indeed incremented twice in this example. It is then possible, from the c1 to c4 signals, to determine that two X-ray photons with an energy greater than a value E4 were received by the PD photodetector of the DET1 detector, the energy value E4 determining, with the FRONT-END circuit, the value of the threshold Th4, whereas this was not the case with the ci signals of the DET detector.

[0200] In particular, in very high flux applications, when the PD photodetector ([Fig. 10]) receives so many X-ray photons that at least some of the outi signals remain permanently active, whereas the DET detector of [Fig. 1] would be paralyzed and would not generate any incrementation of the corresponding ci signals, the DET1 detector is not paralyzed and continues to increment the corresponding ci signals thanks to the resets of the outci signals by the rst signal. In this case, the DET1 detector will have a counting frequency that does not decrease at very high flux but will reach a maximum value equal to l / (tmpl + tmp2).

[0201] Figure 13 schematically represents, in block form, an example of detailed embodiment of the PULSE-RESET circuit of detector DET1 of [Fig.10].

[0202] In this embodiment, the rst signal is configured to reset the outci signals.

[0203] In this example, N is equal to 4.

[0204] The PULSE-RESET circuit includes, for each CHi channel, a GENi circuit (GEN1, ..., GENi, ..., GEN4 in [Fig.7]) configured to receive the outi signal from the CHi channel, receive the rst signal and generate the corresponding outci signal.

[0205] According to one embodiment, as illustrated in [Fig. 13], each GENi circuit comprises an RS flip-flop 700 and a combinational OR logic gate. The OR logic gate is configured to receive the outi signal and the rst signal, and to provide a binary output in the active state, for example, the high state, if the outi signal is in the inactive state or the rst signal is in the active state, and in the inactive state, for example, the low state, otherwise. The RS flip-flop typically comprises an initialization input S, a reset input R, and an output Q. The S input is controlled, for example, receives, the corresponding outi signal, and the R input is controlled, for example, receives, the output signal of the OR gate. The Q output determines, for example, provides, the corresponding outci signal. More specifically, in each GENi circuit, the 700 flip-flop is configured to: - switch the outci signal to the active state when the outi signal (input S) switches to the active state while its input R receives a signal in the inactive state; and - switch the outci signal to the inactive state when its input R receives a signal in the active state.

[0206] The person skilled in the art will be able to foresee other implementations of the GENi circuits.

[0207] For example, a person skilled in the art will be able to implement each GENi circuit using a combinational circuit that takes the outi signal and the rst signal as inputs and provides the corresponding outci signal. For example, in the case where the outi, rst, and outci signals are active high and inactive low, the GENi circuit can be implemented with an AND gate having one input receiving the outi signal, another input receiving a binary signal that is high when the rst signal is low and low when the rst signal is high, and an output providing the corresponding outci signal.

[0208] By way of further example, a person skilled in the art will be able to implement each GENi circuit using a multiplexer that takes the outi signal and a signal at a level corresponding to the inactive state of the outi and outci signals on two respective data inputs, and the rst signal on a control input, and outputs the corresponding outci signal. For example, when the rst signal is active, the multiplexer The tiplexer couples its output to the data input receiving the outi signal when the rst signal is inactive, and couples its output to the other data input when the rst signal is active.

[0209] Furthermore, in the embodiment of [Fig. 13], the PULSE-RESET circuit includes a GEN-RST circuit configured to provide the rst signal, at least from the outcl signal. The GEN-RST circuit is therefore configured to receive the outcl signal and to provide the rst signal from the outcl signal.

[0210] According to one embodiment, the GEN-RST circuit comprises a first monostable circuit M0N01 and a second monostable circuit M0N02. Circuit M0N01 is configured to receive the outcl signal from channel CH1 with the lowest threshold Thl, and to provide a P3 pulse each time the outcl signal switches to the active state. In other words, each switching of the outcl signal to the active state causes circuit M0N01 to provide a P3 pulse. Put another way, each switching of the outcl signal to the active state triggers the monostable circuit M0N01. Circuit M0N02 is configured to receive the P3 pulses, and to provide, for example, at the end of each received P3 pulse, a P4 pulse. The rst signal is determined by the P4 pulses; for example, it is identical to the output signal of circuit M0N02, which includes the P4 pulses.For example, the rst signal is configured to force the outci signals to the inactive state at each P4 pulse, and for the entire duration of that P4 pulse.

[0211] By way of example, the duration of each pulse P3 is equal to the duration tmpl, and the duration of each pulse P4 is equal to the duration tmp2.

[0212] According to one embodiment, the monostable circuits M0N01 and M0N02 each comprise one or more resistive components and one or more capacitive components whose resistance and capacitance values ​​determine the duration of the pulses P3 and P4. Preferably, these resistance and / or capacitance values ​​are adjustable so that the durations tmpl and tmp2 can be adapted according to the application in which the EVAL-NUM1 device is implemented, for example, according to the characteristics of the FRONT-END circuit and / or the detected particles.

[0213] In the embodiments described above in relation to Figures 11, 12, 13 and 14, the rst signal is configured to force the outci signals to the inactive state at the expiry of a time period tmpl beginning with each switching to the active state of the outci signal of the CHi channel with the lowest threshold.

[0214] In embodiments, in addition to forcing the outci signals to the inactive state upon the expiration of a time period tmpl beginning with each switching to the active state of the outci signal of the lowest threshold CHi channel, the rst signal is further configured to force the reset of other circuits, in particular the COMPi comparators. For example, according to one embodiment, the rst signal is configured to force the The outci signals and the outi signals are inactive at the expiration of a time period tmpl, which begins with each switching of the outci signal of the lowest threshold CHi channel to the active state. In such a variant, each comparator COMPi receives the rst signal, for example, on a COMPi comparator reset input. For example, each time the rst signal forces the outci signals to the inactive state, this signal also forces the outi signals to the inactive state. A person skilled in the art will be able to adapt the above description in relation to Figures 11, 12, 13, and 14 to such a variant.

[0215] In other embodiments, rather than forcing the outci signals to the inactive state upon the expiration of a time period tmpl beginning with each switching to the active state of the outci signal of the lowest threshold CHi channel, the rst signal is configured to force the reset of other circuits, in particular the COMPi comparators, upon the expiration of the time period tmpl beginning with each switching to the active state of the outci signal of the lowest threshold CHi channel. For example, according to one embodiment, the rst signal is configured to force only the outi signals to the inactive state upon the expiration of a time period tmpl beginning with each switching to the active state of the outci signal of the lowest threshold CHi channel. In such a variant, each COMPi comparator receives the rst signal, for example, on a COMPi comparator reset input.For example, in such a variant, each GENi circuit is configured to copy the outi signal it receives onto the outci signal it provides. For example, each GENi circuit then includes a simple connection, a buffer circuit, a delay circuit, or an inverter between its input receiving the outi signal and its output providing the corresponding outci signal. A person skilled in the art will be able to adapt the description given above in relation to Figures 11, 12, 13, and 14 to such a variant.

[0216] In the embodiments described above in relation to figures 11, 12, 13 and 14, each time period tmpl has the same constant duration.

[0217] In alternative embodiments, a time period tmpl is triggered, by the PULSE-RESET circuit, at each switching to the active state of the outci signal of the CHi channel with the lowest threshold Thi, but this period tmpl ends: if the signal outi or outci of a given CHi channel, preferably the CHN channel, having a threshold Thi higher than the lowest threshold Thl, switches to the inactive state before the end of a minimum time period tmplmax of fixed duration which begins at the same time as the tmpl period, and at the end of the time period tmplmax otherwise.

[0218] The implementation of such embodiment variants is within the reach of a person skilled in the art from the present description.

[0219] In addition, alternative embodiments such as those described above where the duration tmpl The non-fixed function can be combined with embodiments in which the rst signal is configured to force the reset of only the outi signals, and with embodiments in which the rst signal is configured to force the reset of both the outi and outci signals. Implementing such combinations is within the capabilities of a person skilled in the art, based on this description.

[0220] In the embodiments and variants described above, the PULSE-RESET circuit is configured to switch, for each CHi channel, the outci signal to the active state when the outi signal switches to the active state, to switch the outci signal to the inactive state when the outi signal switches to the inactive state, and to generate the rst signal configured to force the outci and / or outi signals to the inactive state. In cases where the rst signal is configured to force at least the outci signals to the inactive state, in variant embodiments, the PULSE-RESET circuit is configured, for each CHi channel, to switch the outci signal to the active state when the outi signal switches to the active state, and to maintain this outci signal in the active state until the rst signal forces this outci signal to switch to the inactive state. Such a variant is compatible with a fixed duration tmpl and with a variable duration tmpl but bounded by a duration tmpmaxl.As an example of implementing such a variant, using the PUSLE-RESET circuit example from [Fig.7], this amounts, for each GENi circuit, to removing the OR gates so that the R input of the flip-flop is controlled, for example, receives the rst signal. In such an example, the RS flip-flop is then configured to: . - switch the outci signal (output Q) to the active state when the outi signal (input S) switches to the active state while the rst signal is in the inactive state (input R); - switch the outci signal (output Q) to the inactive state when the rst signal (input R) switches to the active state, whether the outci signal is active or not; and - maintain the outci signal (output Q) in the inactive state as long as the rst signal (input R) and the outi signal (input S) are simultaneously in the inactive state.

[0221] The embodiments and variants of the second aspect described above can be combined with the embodiments and variants of the first aspect described previously. In this case, the NUM1 circuit is associated with a PUSLE-RESET circuit, or, in other words, the NUM circuit of the EVAL-NUM1 circuit is replaced by the NUM1 circuit of the first aspect.

[0222] A third aspect provides for taking advantage of the embodiments and variants of the second aspect described above, in cases where the PULSE-RESET circuit forces the reset of the output signals, when these embodiments and variants are combined with the first aspect. In other words, a third aspect provides for a NUM-EVAL3 circuit comprising not only the NUM1 circuit (first aspect), and in particular its BOOST circuit, but also the PUSLE-RESET circuit (second aspect). configured to force the outi signals to the inactive state at the expiration of the tmpl period starting with each switch to the active state of the outcl signal.

[0223] Third aspect

[0224] Fig. 14 schematically represents, in block form, an embodiment of a DET3 particle counting detector.

[0225] The DET3 detector shares many features with the DET1 detector of [Fig. 10], and only the differences between these two detectors, DET3 and DET1, are highlighted here. In other words, unless otherwise stated, everything described for the DET1 detector of [Fig. 10] applies to the DET3 detector of [Fig. 14].

[0226] The DET3 detector differs from the DET1 detector in that the EVAL-NUM1 circuit is replaced by an EVAL-NUM3 circuit. The EVAL-NUM3 circuit is similar to the EVAL-NUM1 circuit and differs from it only in that the NUM circuit is replaced by the NUM2 circuit.

[0227] Furthermore, in this third aspect, the PULSE-RESET circuit is configured to force the reset of the outi signals, and optionally that of the outci signals, at the end of the tmpl period beginning with each switching to the active state of the outcl signal. Thus, the NUM2 circuit receives the rst signal. For example, each COMPi circuit receives the rst signal and is configured to force the outi signal corresponding to the inactive state when it receives the active state of the rst signal.

[0228] According to one embodiment, in a manner similar to that described in relation to Figures 5 and 6, the BOOST circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in high consumption mode if the signal outi is in the active state, and in low consumption mode otherwise.

[0229] According to another embodiment, similarly to what has been described in relation to Figures 3 and 4, the BOOST circuit is configured to control, for i from 2 to N, each comparator COMPi in high consumption mode if the outi-1 signal of channel CHi-1 is in the active state, and in low consumption mode otherwise.

[0230] According to yet another embodiment, similarly to what has been described in relation to Figures 7 and 8, the BOOST circuit is configured to: - for i ranging from 2 to N-1 and N strictly greater than 2, control each comparator COMPi in high-power mode if the outi-1 signal of channel CHi-1 is active while the outi+1 signal of channel CHi+1 is inactive, and in low-power mode otherwise; and - control the COMPN comparator in high power mode if the outN-1 signal of the CHN-1 channel is active, and in low power mode otherwise.

[0231] According to yet another embodiment, the BOOST circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in high mode Power consumption is high if the CHi channel's out signal is inactive while the CHI channel's out signal is active, and low power consumption otherwise. In this case, as shown in [Fig. 14], the BOOST circuit provides the b2 to BN signals only from the out signal.

[0232] According to yet another embodiment, the BOOST circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in high consumption mode if the outi signal of channel CHi is in the inactive state while the outi-1 signal of channel CHi-1 is in the active state, and in low consumption mode otherwise.

[0233] More generally, the person skilled in the art will be able to implement the other embodiments and variants of the BOOST circuit mentioned at the end of the description of the first aspect, in the NUM2 circuit of the EVAL-NUM3 circuit.

[0234] Furthermore, in the NUM2 circuit of the EVAL-NUM3 circuit, according to some embodiments, the comparator COMPI is configured to operate continuously in high-power mode, the BOOST circuit then not providing a bl signal, and, according to other embodiments, the comparator COMPI is configured to operate selectively in high-power mode or in low-power mode, and the BOOST circuit is then configured to control the comparator COMPI in high-power mode, for example by means of the bl signal in its second binary state, if the out2 signal is in the inactive state, and in low-power mode, for example by means of the bl signal in its first binary state, otherwise.

[0235] Figure 15 illustrates, by means of timing diagrams, an example of the operation of the DET3 detector of Figure 14. More specifically, Figure 15 represents the evolution of the outFE voltage as a function of time t, the thresholds Thi, and the evolution of the outi, rst, outcl, and bi signals as a function of time t in a case where the DET3 circuit comprises N=4 CHi channels. The thresholds Thi (Thl, Th2, Th3, Th4 in Figure 15) increase with the index i. In this example, the inactive state of the outi signal and the outc1 signal is the low state, and the active (pulse) state of the outi signal and the outcl signal is the high state. In this example, each signal bi (b2, b3, and b4 in [Fig. 15]) controls the comparator COMPi in low-power mode when it is low, and in high-power mode when it is high. In the example in [Fig. 15], the voltage outFE has a single pulse PL. In the example in [Fig. 15], the comparator COMPi is permanently in high-power mode.

[0236] In the example of [Fig. 15], the timing diagrams take into account the delay introduced by each comparator COMPi between the moment when the voltage outFE crosses the threshold Thi associated with this comparator and the corresponding switching of the output signal outi of the comparator.

[0237] In the embodiment illustrated in [Fig. 15], the BOOST circuit is configured, for i ranging from 2 to N, to drive each comparator COMPi in high mode. Power consumption is high if the outl signal is active, and low power consumption otherwise.

[0238] At a time t0 before the start of the PI pulse, the outFE voltage is below the Thl threshold, so all the outi signals are in the inactive state (low state in [Fig. 15]). Furthermore, since all the outi signals are in the inactive state, all the bi signals for i from 2 to N are in their first binary states (the low state in [Fig. 15]). As a result, the COMPi comparators for i from 2 to N are all controlled in low power consumption mode. Since the outi signal is in the inactive state, the outcl signal is also in the inactive state.

[0239] The PI pulse begins after time t0, and, at a time tl later than time t0, the outFE voltage becomes greater than the threshold Thl. As a result, at a time tl' later than time tl, the outi signal switches to the active state (high state in [Fig. 15]). In this example, where the COMPI comparator is always operating in high-power mode, this switching of the outi signal occurs while the COMPI comparator is in high-power mode.

[0240] Switching the outi signal to the active state causes the COMPi comparators to be switched by the BOOST circuit, for i from 2 to N=4, into high consumption mode, or, in other words, switching the bi signals, for i from 2 to N=4, to the second binary state (high state in [Fig. 15]).

[0241] Switching the outi signal to the active state also causes the outcl signal to switch to the active state (high state in [Fig. 15]) via the PULSE-RESET circuit. This results in the start of a corresponding tmpl duration.

[0242] After time tl, at a time t2 later than time tl' in this example, the voltage outFE increases and exceeds the threshold Th2, from which it follows that, at a time t2' later than time t2, the signal out2 switches to the active state while the corresponding comparator COMP2 is controlled in high consumption mode.

[0243] After time t2, at a time t3 between times t2 and t2' in this example, the voltage outFE increases and exceeds the threshold Th3, from which it follows that, at a time t3' later than times t3 and t2', the signal out3 switches to the active state while the corresponding comparator COMP3 is controlled in high consumption mode.

[0244] After time t3, at a time t4 between times t2' and t3' in this example, the voltage outFE increases and exceeds the threshold Th4, from which it follows that, at a time t4' later than times t4 and t3', the signal out4 switches to the active state while the corresponding comparator COMP4 is controlled in high consumption mode.

[0245] At successive times t5, t6, t7 and t8 after time t4, and after time t4' in this example, the tension outFE becomes lower successively below the thresholds Th4, Th3, Th2 and Thl.

[0246] Dashed lines illustrate in [Fig. 15] the corresponding shape that the corresponding signals out4, out3, out2 and outi should have, and, in particular, that the signals out4, out3, out2 and outl should successively switch to the inactive state at times later than time t8.

[0247] However, approximately at time t8 in this example, the duration tmpl expires and the signal rst switches to the active state. This causes the outputs outi of the COMPi comparators to reset, or, in other words, it forces the outi signals to switch to the inactive state.

[0248] Switching the outi signal to the inactive state causes the COMPi comparators to be switched by the BOOST circuit, for i from 2 to N=4, in low power mode, or, in other words, switching the bi signals, for i from 2 to N=4, to the first binary state (low state in [Fig. 15]).

[0249] Switching the outi signal to the inactive state also causes the outcl signal to switch to the inactive state (low state in [Fig. 15]).

[0250] The PUSLE-RESET circuit therefore makes it possible to help the return of the outi signals to the inactive state, and, more particularly, to switch them to the inactive state in advance of the case where these signals would be switched to the inactive state by the comparators COMPi only on the basis of the comparison made, by each comparator COMPi, between the outFE voltage and the associated threshold Thi.

[0251] It follows that the COMPi comparators for i from 2 to N switch back to low power mode more quickly than in the example of [Fig.6].

[0252] Although an example has been described here in the case where the COMPI comparator is always in high power mode, a person skilled in the art can adapt the description of this example to the case where the COMPI comparator is controlled in high power mode when the out2 signal is inactive, and in low power mode otherwise.

[0253] Figure 16 illustrates, by means of timing diagrams, another example of the operation of the DET3 detector of Figure 14. More specifically, Figure 16 represents the evolution of the outFE voltage as a function of time t, the thresholds Thi, and the evolution of the outi, rst, outcl, and bi signals as a function of time t in a case where the DET3 circuit comprises N=4 CHi channels. The thresholds Thi (Thi, Th2, Th3, Th4 in Figure 15) increase with the index i. In this example, the inactive state of the outi signal and the outc1 signal is the low state, and the active (pulse) state of the outi signal and the outcl signal is the high state. In this example, each signal bi (bl, b2, b3 and b4 in [Fig. 16]) controls the comparator COMPi in low-power mode when it is low, and in high-power mode when it is high. In the example in [Fig. 16], the voltage outFE has a single pulse PL. In the example in [Fig.

[16] , the COMPI comparator is controlled in high power mode if the out2 signal is inactive, and in low power mode otherwise.

[0254] In the example in [Fig. 16], the timing diagrams take into account the delay introduced by each comparator COMPi between the moment when the outFE voltage crosses the threshold Thi associated with that comparator and the corresponding switching of the outi output signal of the comparator.

[0255] In the embodiment illustrated by [Fig.16], the BOOST circuit is configured, for i ranging from 2 to N, to control each comparator COMPi in high consumption mode if the outi signal is in the inactive state while the outl signal is in the active state, and in low consumption mode otherwise.

[0256] In this example, the COMPI comparator is controlled in high power mode when the out2 signal is inactive, and in low power mode otherwise.

[0257] At a time t0 before the start of the PI pulse, the outFE voltage is below the threshold Thl, so all the outi signals are in the inactive state (low state in [Fig. 16]). Furthermore, since all the outi signals are in the inactive state, all the bi signals for i from 2 to N are in their first binary states (the low state in [Fig. 16]), and the bl signal is in the active state (the high state in [Fig. 16]). It follows that the COMPi comparators for i from 2 to N are all controlled in low-power mode, and that the COMPI comparator is controlled in high-power mode. Since the outi signal is in the inactive state, the outc1 signal is also in the inactive state.

[0258] The PI pulse begins after time t0, and, at a time tl later than time t0, the outFE voltage becomes greater than the threshold Thl. As a result, at a time tl' later than time tl, the outi signal switches to the active state (high state in [Fig. 16]) while the COMPI comparator is in high-power mode.

[0259] Switching the outi signal to the active state causes the COMPi comparators to be switched by the BOOST circuit, for i from 2 to N=4, into high consumption mode, or, in other words, switching the bi signals, for i from 2 to N=4, to the second binary state (high state in [Fig. 16]).

[0260] Switching the outi signal to the active state also causes the outcl signal to switch to the active state (high state in [Fig. 16]) via the PULSE-RESET circuit. This results in the start of a corresponding tmpl duration.

[0261] After time t1, at a time t2 subsequent to time t1' in this example, the voltage outFE increases and exceeds the threshold Th2, from which it follows that, at a time t2' subsequent to time t2, the signal out2 switches to the active state while the corresponding comparator COMP2 is controlled in high-power mode. The switching of the signal out2 to the active state causes the comparators COMP1 and COMP2 to switch to low-power mode, that is to say, the switching of the signals b1 and b2 to their first binary states (the low state in [Fig. 16]).

[0262] After time t2, at a time t3 between times t2 and t2' in this example, the voltage outFE increases and exceeds the threshold Th3, from which it follows that, at a time t3' Subsequent to times t3 and t2', the out3 signal switches to the active state while the corresponding comparator C0MP3 is controlled in high-power mode. This switching of the out3 signal to the active state causes the comparator C0MP3 to switch to low-power mode, that is, the switching of the b3 signal to its first binary state (low state in [Fig. 16]).

[0263] After time t3, at a time t4 between times t2' and t3' in this example, the voltage outFE increases and exceeds the threshold Th4, from which it follows that, at a time t4' later than times t4 and t3', the signal out4 switches to the active state while the corresponding comparator COMP4 is controlled in high-power mode. This switching of the signal out4 to the active state causes the comparator COMP4 to switch to low-power mode, that is, the signal b4 to switch to its first binary state (low state in [Fig. 16]).

[0264] At successive times t5, t6, t7 and t8 after time t4, and after time t4' in this example, the tension outFE becomes lower successively below the thresholds Th4, Th3, Th2 and Thl.

[0265] Dotted lines illustrate in [Fig. 16] the shape that the corresponding signals out4, out3, out2 and outl should have, and, in particular, that the signals out4, out3, out2 and outl should switch successively to the inactive state at times later than time t8.

[0266] However, approximately at time t8 in this example, the duration tmpl expires and the signal rst switches to the active state. This causes the outputs outi of the COMPi comparators to reset, or, in other words, it forces the outi signals to switch to the inactive state.

[0267] Switching the outl signal to the inactive state causes the COMPi comparators to be switched by the BOOST circuit, for i from 2 to N=4, into low power mode, or, in other words, switching the bi signals, for i from 2 to N=4, to the first binary state (low state in [Fig. 16]).

[0268] Switching the outl signal to the inactive state also causes the outcl signal to switch to the inactive state (low state in [Fig. 16]).

[0269] Switching the out2 signal to the inactive state causes the COMPI comparator to switch, by the BOOST circuit, to high-consumption mode, or, in other words, switching the bl signal to the second binary state (high state in [Fig. 16])

[0270] The PULSE-RESET circuit thus helps the outi signals return to the inactive state, and, more specifically, switches them to the inactive state earlier than if these signals were switched to the inactive state by the COMPi comparators solely based on the comparison made by each COMPi comparator between the outFE voltage and the associated Thi threshold. This also allows the high-power mode of each COMPi comparator to be conditioned for i ranging from 2 to N. the inactive state of the output signal outi of this comparator. As a result, the COMPi comparators for i ranging from 2 to N switch back to low power mode more quickly than in the example of [Fig. 15].

[0271] Although an example has been described here in the case where the COMPI comparator is controlled in high power mode when the out2 signal is in the inactive state, and in low power mode otherwise, a person skilled in the art can adapt the description of this example to the case where the COMPI comparator is always in high power mode.

[0272] In the example in [Fig. 16], the BOOST circuit is configured, for i ranging from 2 to N, to drive each comparator COMPi in high-power mode if the outi signal is inactive while the outl signal is active, and in low-power mode otherwise. As a result, the switching of these COMPi comparators to high-power mode occurs when the outi signal switches to the active state.

[0273] In another example not shown, to further reduce the time each comparator COMPi, for i ranging from 2 to N, is controlled in high-power mode if the outi signal of channel CHi is inactive while the outi-1 signal of channel CHi-1 is active, and in low-power mode otherwise. Using the example in [Fig. 16], the signals b2, b3, and b4 would then switch to the high state at respective times t1', t2', and t3'.

[0274] Although embodiments and variants of detectors DET1, DET2, and DET3 have been described, comprising devices EVAL-NUM1, EVAL-NUM2, and EVAL-NUM3 respectively, some embodiments provide for the devices EVAL-NUM1, EVAL-NUM2, and EVAL-NUM3 alone, i.e., without the FRONT-END circuit and the PD photodetector. Indeed, it may be desirable for a PD photodetector and FRONT-END circuit to be developed and produced by one entity (legal or natural person), and for the EVAL-NUM1, EVAL-NUM2, and EVAL-NUM3 circuit to be developed and produced by another entity (legal or natural person) and to be compatible with this PD photodetector and FRONT-END circuit, for example, by adjusting the threshold values ​​Thi and / or the durations tmpl (or tmplmax) and / or tmp2 accordingly.

[0275] Similarly, one embodiment provides for the PULSE-RESET circuit alone, that is to say without the NUM and NUM2, EVAL and FRONT-END circuits and without the PD photodetector.

[0276] Furthermore, one embodiment provides a particle-counting scanner, for example X-ray photons, comprising a plurality of photon-counting detectors DET1, DET2, or DET3. In the case where the particles detected by each detector DET1, DET2, DET3 of the scanner are X-ray photons, each photodetector PD comprises, for example, cadmium telluride. For example, according to one embodiment In this particular configuration, all the PD photodetectors of an array of several detectors DET1, DET2, or DET3 are arranged in the first level of a stack, the first level comprising, for example, a cadmium telluride layer or substrate, and all the FRONT-END and EVAL-NUM1, EVAL-NUM2, or EVAL-NUM3 circuits of this array of detectors are arranged in the second level of the stack, the first level comprising, for example, a silicon substrate or silicon layer, for example, of the SOI type. The first level is then mounted on the second level and is electrically connected to it, for example, by conductive beads or pads.

[0277] Of course, the embodiments and variants described above are not limited to implementation in an X-ray photon counting scanner, and, more generally, are not limited to implementation in a particle counting scanner.

[0278] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0279] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Device (EVAL-NUM2, EVAL-NUM3, NUM2) for a particle counting detector (DET2, DET3), wherein: the device comprises N digitizing channels, CHi, with N an integer strictly greater than 1 and i an index from 1 to N; each channel CHi comprises a comparator, COMPi, associated with a threshold, Thi, of the channel and configured to provide a first pulsed digital signal, outi, in an active state if a pulsed analog voltage (outFE) supplied to said channels is greater than the threshold of the channel, and in an inactive state otherwise; the thresholds Thi are increasing with the index i; for i from 2 to N, each comparator COMPi is configured to selectively operate in a low-power mode and a high-power mode;and the device includes a control circuit (BOOST) for the COMPi comparators configured, for i ranging from 2 to N, to control each COMPi comparator in low power mode or in high power mode as a function of at least the first outi signal of at least one of the CHi channels.;

2. Device according to claim 1, wherein the control circuit (BOOST) is configured, on a rising edge of each pulse of said voltage (outFE) and for i ranging from 2 to N, to switch each comparator COMPi into the high-power mode in response to a switching to the active state of the first outi signal of channel CHI or the first outi-1 signal of channel CHi-1.

3. Device according to claim 2, wherein the control circuit (BOOST) is further configured, following the rising edge of the pulse of said voltage and for i ranging from 2 to N, to switch each comparator COMPi into the low power mode at the earliest in response to a switching to the active state of the first outi signal of the CHi channel, and at the latest in response to a switching to the inactive state of the first outi signal of the CHI channel.

4. Device according to any one of claims 1 to 3, wherein the control circuit (BOOST) is configured, for i from 2 to N, to control each comparator COMPi in high power mode if the first outi-1 signal of channel CHi-1 is active, and in low power mode otherwise.

5. Device according to any one of claims 1 to 3, wherein N is strictly greater than 2 and the control circuit (BOOST) is configured, for i from 2 to N-1, to: - control each comparator COMPi in high power mode if the first signal outi-1 of channel CHi-1 is active while the first signal outi+1 of channel CHi+1 is inactive, and in low power mode otherwise; and - control comparator COMPN in high power mode if the first signal outN-1 of channel CHN-1 is active and in low power mode otherwise.

6. Device according to any one of claims 1 to 3, wherein the control circuit is configured, for i from 2 to N, to control each comparator COMPi in high power mode if the first outl signal of the CHI channel is active, and in low power mode otherwise.

7. Device according to any one of claims 4 to 6, wherein: - the COMPI comparator is configured to operate only in high power mode; or - the COMPI comparator is configured to operate selectively in high power mode or in low power mode, and the control circuit (BOOST) is configured to control the COMPI comparator in high power mode if the first out2 signal is inactive, and in low power mode otherwise.

8. Device according to any one of claims 1 to 7, wherein the device (EVAL-NUM2) further comprises a digital counting circuit (EVAL) configured to count, for each CHi channel, a number of active state switchings of the first outi signal of said channel.

9. A device according to any one of claims 1 to 7, wherein: the device (EVAL-NUM3) further comprises a digital pulse reset circuit (PULSE-RESET) configured to: - for each CHi channel, receive the first outi signal of said channel, generate a second digital pulse outci signal, and switch the second outci signal into an active state when the first outi signal is in the active state; and - generate a reset signal (rst) forcing, at each switching to the active state of the second outci signal of the CHi channel, a switching to the inactive state of the first outi signals and / or the second outci signals at the end of a first time period (tmpl) beginning with the switching to the active state of the second outci signal of channel CH1.

10. Device according to claim 9 wherein the reset signal (rst) is configured to force, at each switching to the active state of the second outci signal of channel CH1, at least the switching to the inactive state of the first outi signals at the end of the first time period (tmpl) beginning with the switching to the active state of the second outci signal of channel CH1.

11. Device according to any one of claims 1 to 3, wherein: the device (EVAL-NUM3) further comprises a digital pulse reset circuit (PULSE-RESET) configured to: - for each channel CHi, receive the first outi signal of said channel, generate a second digital pulse outci signal, and switch the second outci signal into an active state when the first outi signal is in the active state;and - generate a reset signal (rst) forcing, at each switching to the active state of the second outci signal of the CHI channel, a switching to the inactive state of the first outi signals at the end of a first time period (tmpl) beginning with the switching to the active state of the second outci signal of the CHI channel, and the control circuit (BOOST) is configured to, for i ranging from 2 to N, to control each comparator COMPi in high power mode if the first outi signal of the CHi channel is in the inactive state while the first outi signal of the CHI channel is in the active state, and in low power mode otherwise.;

12. A device according to any one of claims 1 to 3, wherein: the device (EVAL-NUM3) further comprises a digital pulse reset circuit (PULSE-RESET) configured to: - for each CHi channel, receive the first outi signal of said channel, generate a second digital pulse outci signal, and switch the second outci signal into an active state when the first outi signal is in an active state; and - generate a reset signal (rst) forcing, at each switching to the active state of the second outci signal of the CHi channel, a switching to the inactive state of the first outi signals at the end of a first time period (tmpl) beginning with the switching to the active state of the second outcl signal of channel CH1, and the control circuit (BOOST) is configured to, for i ranging from 2 to N, to control each comparator COMPi in high power mode if the first outi signal of channel CHi is in the inactive state while the first outi-1 signal of channel CHi-1 is in the active state, and in low power mode otherwise.

13. Device according to any one of claims 9 to 12, wherein the device (EVAL-NUM3) further comprises a digital counting circuit (EVAL) configured to count, for each CHi channel, a number of active state switchings of the second outci signal of said channel.

14. Particle counting detector (DET2, DET3) comprising: a photodetector (PD) adapted to receive particles, for example photons from X-rays, and to provide a pulsed analog current (Idet) determined by the received particles; a current-to-voltage conversion circuit (FRONT-END) configured to receive the pulsed analog current (Idet) and to provide a corresponding pulsed analog voltage (outFE); and a device (EVAL-NUM2, EVAL-NUM3, NUM2) according to any one of claims 1 to 13, configured to receive the pulsed analog voltage.

15. Photon counting scanner comprising a plurality of particle counting detectors (DET2, DET3) according to claim 14, wherein the particles are photons of X-ray radiation, and each photodetector (PD) comprises, for example, cadmium telluride.

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