Electronic device

Abstract

Electronic Device This description relates to a device comprising a voltage regulator (18) including: first (88) and second (90) branches comprising first (92, 106), second (94, 108), and third (96, 110) transistors, the control nodes of the first transistors of the first and second branches being connected together, the control node of the third transistor of each first and second branch being connected to the midpoint of the first and second transistors of the same branch; a fourth transistor (118); and a fifth transistor (120), the control nodes of the fourth and second transistors of the first branch being connected together to a setpoint voltage application node, the control nodes of the fifth and second transistors of the second branch being connected together to an output node of the regulator. Figure for the abstract: Fig. 2

Description

Title of the invention: Electronic device Technical field

[0001] The present description relates generally to electronic devices and more particularly to electronic devices comprising voltage regulators. Prior art

[0002] A voltage regulator is an electronic component configured to maintain a substantially constant voltage at its output. Voltage regulators may, for example, be linear regulators, i.e., regulators based on an active component working in its linear region or on a passive component, such as a Zener diode, working in its inverse region.

[0003] One type of linear regulator is the so-called low dropout (LDO) regulator. Regulators of this type are such that the output voltage is very close to the regulator's supply voltage. Summary of the invention

[0004] One embodiment provides a device comprising a voltage regulator, the regulator comprising: first and second branches, each first and second branch comprising first, second and third transistors connected in series, in this order, between a first node for applying a supply voltage and a second node for applying a reference voltage, the control nodes of the first transistors of the first and second branches being connected together, the control node of the third transistor of each first and second branch being connected to the midpoint of the first and second transistors of the same branch; a fourth transistor connected between the midpoint of the second and third transistors of the second branch and a third node;and a fifth transistor connected between the midpoint of the second and third transistors of the first branch and a fourth node, the control nodes of the fourth transistor and of the second transistor of the first branch being connected together to a node for applying a set voltage, the control nodes of the fifth transistor and of the second transistor of the second branch being connected together to an output node of the regulator. ;

[0005] According to one embodiment, the first transistors of the first and second branches are P-channel MOSFET transistors, the second and third transistors of the first and second branches are N-channel MOSFET transistors.

[0006] According to one embodiment, the regulator comprises, connected in this order in series between the first and second nodes, sixth and seventh transistors, a first resistor, and eighth and ninth transistors, the control node of the sixth transistor being connected to the midpoint of the seventh transistor and the resistor, the control node of the sixth transistor being further connected to the control nodes of the first transistors of the first and second branches, the control node of the seventh transistor being connected to the midpoint of the transistor and the resistor.

[0007] According to one embodiment, the regulator comprises, connected in this order in series between the first and second nodes, a current source, a second resistor, and tenth and eleventh transistors, the control node of the tenth transistor being connected to the midpoint of the second resistor and the current source and to the control node of the eighth transistor, the control node of the eleventh transistor being connected to the control node of the ninth transistor.

[0008] According to one embodiment, the regulator comprises twelfth, thirteenth and fourteenth transistors connected, in this order, in series between the first and second nodes, a control node of the fourteenth transistor being connected to the control node of the third transistor of the first branch, a control node of the thirteenth transistor being connected to the control node of the eighth transistor.

[0009] According to one embodiment, the regulator comprises fifteenth, sixteenth and seventeenth transistors connected, in this order, in series between the first and second nodes, a control node of the seventeenth transistor being connected to the control node of the third transistor of the second branch, a control node of the sixteenth transistor being connected to the control node of the eighth transistor, a control node of the fifteenth transistor being connected to the control node of the twelfth transistor.

[0010] According to one embodiment, the regulator comprises an eighteenth transistor connected between the first node and the output node of the regulator.

[0011] According to one embodiment, the regulator comprises a nineteenth transistor, the nineteenth transistor being connected in series between the twelfth and thirteenth transistors, a control node of the nineteenth transistor being connected to the control node of the seventh transistor, a control node of the twelfth transistor being connected to the midpoint of the nineteenth and thirteenth transistors.

[0012] According to one embodiment, the regulator comprises a twentieth transistor, the twentieth transistor being connected in series between the fifteenth and sixteenth transistors, a control node of the twentieth transistor being connected to the control node of the nineteenth transistor.

[0013] According to one embodiment, a control node of the eighteenth transistor is connected to the midpoint of the twentieth and sixteenth transistors.

[0014] According to one embodiment, a control node of the thirteenth transistor is connected at the midpoint of the thirteenth and fourteenth transistors, a control node of the eighteenth transistor being connected to the midpoint of the fifteenth and sixteenth transistors.

[0015] According to one embodiment, the regulator comprises a first Miller capacitor, the first capacitor being connected between the output node of the regulator and the midpoint of the sixteenth and seventeenth transistors.

[0016] According to one embodiment, the regulator comprises a second Miller capacitor, the second capacitor being connected between the output node of the regulator and the control node of the third transistor of the first branch. Brief description of the drawings

[0017] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0018] [Fig.l] represents an example of an electronic device;

[0019] [Fig.2] represents an embodiment of a voltage regulator;

[0020] [Fig.3] shows another embodiment of a voltage regulator; and

[0021] [Fig.4] shows another embodiment of a voltage regulator. Description of the embodiments

[0022] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0023] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0024] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0025] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0026] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0027] [Fig.l] represents an example of an electronic device 10. The device 10 is for example a chip.

[0028] The device 10 comprises, for example, a set 12 of circuits and components configured to enable the implementation of digital functions. The set 12 comprises, for example, one or more microcontrollers. The device 10 comprises, for example, a memory 14.

[0029] The device 10 comprises a power management unit 16. The unit 16 is for example configured to generate a supply voltage Vout. The supply voltage Vout is for example the supply voltage of the assembly 12 and / or of the memory 14.

[0030] The unit 16 comprises for example at least one voltage regulator, or a voltage follower, configured to allow the voltage Vout to be maintained at a desired value during operation of the device 10.

[0031] [Fig.2] shows an embodiment of a voltage regulator 18. The re voltage regulator 18 is for example configured to be included in the power management unit 16 of [Fig.l].

[0032] The voltage regulator 18 is configured to supply a load 20. The load 20 corresponds for example to the memory 14 or to the assembly 12 of [Fig.l]. More precisely, the regulator 18 comprises an output node 22 on which the supply voltage Vout is generated. The load 20 is connected, preferably connected, to the node 22.

[0033] The regulator 18 comprises a transistor 26. The transistor 26 is for example an insulated gate field effect transistor (MOSFET - Metal Oxide Semiconductor Field Effect Transistor). The transistor 26 is preferably a P-channel transistor.

[0034] The node 22 is connected to a node 24 for applying a supply voltage VDD of the device 10, i.e. a supply voltage of the regulator 18, by the transistor 26. In other words, a conduction node of the transistor 26, for example the source, is connected, preferably connected, to the node 24 and another conduction node of the transistor 26, for example the drain, is connected, preferably connected, to the node 22.

[0035] The regulator 18 further comprises transistors 28, 30, 32, 34. The transistors 28, 30, 32, 34 are, for example, insulated gate field effect transistors (MOSFETs). The transistors 28, 30, 32, 34 are preferably P-channel transistors.

[0036] Transistors 28 and 30 are connected in series. Similarly, transistors 32 and 34 are connected in series. Transistors 28 and 30 are connected in cascode. In other words, a conduction node of transistor 28, preferably the source, is connected, preferably connected, to node 24. Another conduction node of transistor 28, for example the drain, is connected, preferably connected, to a node 36. A conduction node of transistor 30, preferably the source, is connected, preferably connected, to node 36. Another conduction node of transistor 30, for example the drain, is connected, preferably connected, to a node 38. The control node of transistor 28, for example example the grid, is connected, preferably connected, to node 38.

[0037] Furthermore, transistors 32 and 34 are connected in current mirror with transistors 28 and 30. In other words, a conduction node of transistor 32, preferably the source, is connected, preferably connected, to node 24. Another conduction node of transistor 32, for example the drain, is connected, preferably connected, to a node 40. A conduction node of transistor 34, preferably the source, is connected, preferably connected, to node 40. Another conduction node of transistor 34, for example the drain, is connected, preferably connected, to a node 41. The control node of transistor 32, for example the gate, is connected, preferably connected, to the control node of transistor 28. Thus, the control node of transistor 32 is connected, preferably connected, to node 38. The control node, for example the gate, of transistor 34 is connected, preferably connected, to the control node of transistor 30.

[0038] The control node of transistor 26, for example the gate, is connected, preferably connected, to node 4L

[0039] The regulator 18 further comprises transistors 42 and 44. The transistors 42 and 44 are, for example, insulated gate field effect transistors (MOSFETs). The transistors 42 and 44 are preferably N-channel transistors.

[0040] Transistors 42 and 44 are connected in series. Transistors 42 and 44 are further connected in series with transistors 32 and 34. In other words, a conduction node of transistor 44, preferably the source, is connected, preferably connected, to a node 46 for applying a reference voltage, for example ground. Another conduction node of transistor 44, for example the drain, is connected, preferably connected, to a node 48. A conduction node of transistor 42, preferably the source, is connected, preferably connected, to node 48. Another conduction node of transistor 42, for example the drain, is connected, preferably connected, to node 4L

[0041] Similarly, the regulator 18 further comprises transistors 50 and 52. The transistors 50 and 52 are, for example, insulated gate field effect transistors (MOSFETs). The transistors 50 and 52 are preferably N-channel transistors.

[0042] Transistors 50 and 52 are connected in series. Transistors 50 and 52 are further connected in series with transistors 28, 30. In other words, a conduction node of transistor 52, preferably the source, is connected, preferably connected, to node 46 for applying a reference voltage, for example ground. Another conduction node of transistor 52, for example the drain, is connected, preferably connected, to a node 54. A conduction node of transistor 50, preferably the source, is connected, preferably connected, to node 54. Another conduction node of transistor 50, for example the drain, is connected, preferably connected, to node 38.

[0043] The regulator 18 further comprises transistors 56, 58, 60, 62. The transistors 56, 58, 60, 62 are for example insulated gate field effect transistors (MOSFET). Transistors 56, 58, 60, 62 are preferably N-channel transistors.

[0044] Transistors 56, 58 are connected in series. Similarly, transistors 60, 62 are connected in series. Transistors 56, 58 are connected in cascode. In other words, a conduction node of transistor 58, preferably the source, is connected, preferably connected, to node 46. Another conduction node of transistor 58, for example the drain, is connected, preferably connected, to a node 64. A conduction node of transistor 56, preferably the source, is connected, preferably connected, to node 64. Another conduction node of transistor 56, for example the drain, is connected, preferably connected, to a node 66.

[0045] Furthermore, transistors 60 and 62 are connected in current mirror with transistors 56, 58. In other words, a conduction node of transistor 62, preferably the source, is connected, preferably connected, to node 46. Another conduction node of transistor 62, for example the drain, is connected, preferably connected, to a node 68. A conduction node of transistor 60, preferably the source, is connected, preferably connected, to node 68. Another conduction node of transistor 60, for example the drain, is connected, preferably connected, to a node 70. The control node of transistor 62, for example the gate, is connected, preferably connected, to the control node, for example the gate, of transistor 58. The control node, for example the gate, of transistor 60 is connected, preferably connected, to the control node, for example the gate, of transistor 56.Furthermore, the control node of the transistor 60 is connected, preferably connected, to the control node of the transistor 50 and to the control node of the transistor 42. In other words, the control nodes of the transistors 42, 50, 56, 60 are connected, preferably connected, to each other.

[0046] The regulator 18 further comprises a resistor 72 and a current source 74. The resistor 72 and the source 74 are connected in series. The resistor 72 and the source 74 are connected in series with the transistors 56 and 58. In other words, one terminal of the resistor 72 is connected, preferably connected, to the node 66 and another terminal of the resistor 72 is connected, preferably connected, to a node 76. The node 76 is further connected, preferably connected, to the control node of the transistor 56. The node 76 is thus connected, preferably connected, to the control node of the transistor 60. The source 74 comprises a terminal connected, preferably connected, to the node 76 and another terminal connected, preferably connected, to the node 24.

[0047] The regulator 18 comprises a resistor 78 and transistors 80 and 82. The transistors 80 and 82 are, for example, insulated gate field effect transistors (MOSFETs). The transistors 80 and 82 are preferably P-channel transistors.

[0048] Transistors 80, 82 and resistor 78 are connected in series. Transistors 80, 82 and resistor 78 are connected in series with transistors 60 and 62. In other words, a terminal of resistor 78 is connected, preferably connected, to node 70 and another terminal of resistor 78 is connected, preferably connected, to a node 84. A conduction node of transistor 80, preferably the source, is connected, preferably connected, to node 24. Another conduction node of transistor 62, for example the drain, is connected, preferably connected, to a node 86. A conduction node of transistor 80, preferably the source, is connected, preferably connected, to node 86. Another conduction node of transistor 82, for example the drain, is connected, preferably connected, to node 84. The control node of transistor 80 is connected, preferably connected, to node 70. Furthermore, the control node of transistor 80 is connected, preferably connected, to the control node of transistor 30 and to the control node of transistor 34. Thus, the control nodes of transistors 30, 34 and 80 are for example connected, preferably connected, together.In addition, the control node of transistor 82 is connected, preferably connected, to node 84.

[0049] The regulator 18 further comprises two branches 88 and 92. The branches 88 and 90 both comprise three transistors connected in series between the nodes 24 and 46.

[0050] Thus, the branch 88 comprises transistors 92, 94, 96. The transistors 92, 94, 96 are, for example, insulated gate field effect transistors (MOSFETs). The transistors 94, 96 are preferably N-channel transistors. The transistor 92 is, for example, a P-channel transistor. The transistor 96 is, for example, a transistor identical to the transistor 52. Alternatively, the surface area of ​​the transistor 96 has, for example, a surface area substantially equal to a multiple of the surface area of ​​the transistor 52.

[0051] Transistors 92, 94, 96 are connected in series between nodes 24 and 46. In other words, transistor 92 comprises a conduction node, for example the source, connected, preferably connected, to node 24. Another conduction node of transistor 92, for example the drain, is connected, preferably connected, to a node 98. Transistor 94 comprises a conduction node, for example the source, connected, preferably connected, to node 98. Another conduction node of transistor 94, for example the drain, is connected, preferably connected, to a node 100. Transistor 96 comprises a conduction node, for example the drain, connected, preferably connected, to node 100. Another conduction node of transistor 96, for example the source, is connected, preferably connected, to node 46.

[0052] The transistor 92 comprises a control node, for example the gate, connected, preferably connected, to a node 102. The node 102 is connected, preferably connected, to the control node of the transistor 82 and is connected, preferably connected, to the node 84. The transistor 94 comprises a control node, for example the gate, connected, preferably connected, to a terminal, for example a positive terminal, of a voltage source 104. The voltage source 104 is configured to generate on the positive terminal, a setpoint voltage Vref. The source 104 further comprises a terminal, for example example a negative terminal, connected, preferably connected, to node 46. Transistor 96 comprises a control node, for example the gate, connected, preferably connected, to node 98, that is to say connected, preferably connected, to the source of transistor 94, that is to say connected, preferably connected, to the midpoint of transistors 92 and 94.

[0053] Similarly, branch 90 comprises transistors 106, 108, 110. Transistors 106, 108, 110 are, for example, insulated gate field effect transistors (MOSFETs). Transistors 108, 110 are preferably N-channel transistors. Transistor 106 is, for example, a P-channel transistor. Transistor 110 is, for example, a transistor identical to transistor 44. Alternatively, the surface area of ​​transistor 110 has, for example, a surface area substantially equal to a multiple of the surface area of ​​transistor 44.

[0054] The transistors 106, 108, 110 are connected in series between the nodes 24 and 46. In other words, the transistor 106 comprises a conduction node, for example the source, connected, preferably connected, to the node 24. Another conduction node of the transistor 106, for example the drain, is connected, preferably connected, to a node 112. The transistor 108 comprises a conduction node, for example the source, connected, preferably connected, to the node 112. Another conduction node of the transistor 108, for example the drain, is connected, preferably connected, to a node 114. The transistor 110 comprises a conduction node, for example the drain, connected, preferably connected, to the node 114. Another conduction node of the transistor 110, for example the source, is connected, preferably connected, to the node 46.

[0055] The transistor 106 comprises a control node, for example the gate, connected, preferably connected, to the node 102. The node 102 is connected, preferably connected, to the control nodes of the transistors 82 and 92 and is connected, preferably connected, to the node 84. The transistor 108 comprises a control node, for example the gate, connected, preferably connected, to the output node 22, on which the voltage Vout is generated. The transistor 110 comprises a control node, for example the gate, connected, preferably connected, to a node 116, that is to say connected, preferably connected, to the source of the transistor 108, that is to say connected, preferably connected, to the midpoint of the transistors 106 and 108. The node 116 is further connected, preferably connected, to the control node of the transistor 44.

[0056] The regulator 18 further comprises a pair of differential transistors 118, 120. The transistors 118, 120 are, for example, insulated gate field effect transistors (MOSFETs). The transistors 118, 120 are preferably N-channel transistors. Preferably, the transistors 118 and 120 are identical transistors. Alternatively, one of the transistors 118, 120 may have an area substantially equal to a multiple of the area of ​​the other transistor among the transistors 118, 120.

[0057] Transistor 118 is connected between node 114, i.e. the middle node of transistors 108 and 110, and node 40, i.e. the middle point of transistors 32 and 34. In other words, a conduction node of transistor 118, for example the source, is connected, preferably connected, to node 114. Another conduction node of transistor 118, for example the drain, is connected, preferably connected, to node 40. A control node, for example the gate, of transistor 118 is connected, preferably connected, to the control node of transistor 94 and to the positive terminal of source 104.

[0058] The transistor 120 is connected between the node 100, that is to say the middle node of the transistors 94 and 96, and the node 36, that is to say the middle point of the transistors 28 and 36. In other words, a conduction node of the transistor 120, for example the source, is connected, preferably connected, to the node 100. Another conduction node of the transistor 120, for example the drain, is connected, preferably connected, to the node 36. A control node, for example the gate, of the transistor 120 is connected, preferably connected, to the control node of the transistor 108 and to the node 22.

[0059] When a current is drawn by the load, the voltage Vout varies. This variation in the voltage Vout causes a variation in the currents flowing through the transistors 32, 34 and a variation in the transistors 42, 44. The variation in the voltage Vout does not only cause a variation in the currents flowing through the transistors 32, 34, as in commonly used regulators. The current at the node 41, i.e. the control current of the transistor 26, thus varies more rapidly in the regulator 18, which causes a faster regulation of the voltage Vout.

[0060] The bias applied to transistors 118 and 120 of the differential pair is thus dynamic.

[0061] [Fig.3] shows another embodiment of a voltage regulator 122.

[0062] The regulator 122 comprises the components of the regulator 18 of [Fig. 2], arranged in an identical manner. These different components, i.e. the transistors 26, 32, 34, 42, 28, 30, 50, 52, 106, 108, 110, 18, 120, 92, 94, 96, 82, 80, 60, 62, 56, 58, the resistors 72 and 78 and the sources 74 and 104, are thus present in the regulator 122 and will not be described again in detail.

[0063] The regulator 122 further comprises capacitors 124 and 126. The capacitors 124 and 126 are Miller capacitors and thus make it possible to compensate for the loop gain and accelerate the response of the regulator.

[0064] The capacitor 124 is connected between the output node 22 and the node 48, that is to say the middle node of the transistors 42 and 44. In other words, one terminal of the capacitor 124 is connected, preferably connected, to the node 22 and another terminal of the capacitor 124 is connected, preferably connected, to the node 48.

[0065] Capacitor 126 is connected between output node 22 and a node 128. Otherwise said, one terminal of capacitor 126 is connected, preferably connected, to node 22 and another terminal of capacitor 126 is connected, preferably connected, to node 128. Node 128 is further connected, preferably connected, to the control nodes of transistors 52 and 96.

[0066] [Fig. 4] shows another embodiment of a voltage regulator 130.

[0067] The regulator 130 comprises the components of the regulator 18 of [Fig. 2], arranged identically, with the exception of the transistors 30 and 34. These different components, i.e. the transistors 26, 32, 42, 28, 50, 52, 106, 108, 110, 18, 120, 92, 94, 96, 82, 80, 60, 62, 56, 58, the resistors 72 and 78 and the sources 74 and 104, are thus present in the regulator 122 and will not be described again in detail. In the absence of transistors 30 and 34, a conduction node of transistor 28, for example the drain, is connected, preferably connected, to node 38 and a conduction node of transistor 32, for example the drain, is connected, preferably connected, to node 4L. Thus, the control node of transistor 28 is connected, preferably connected, to the drain of transistor 28. In addition, the control node of transistor 26 is connected, preferably connected, to the drain of transistor 32..

[0068] Unlike regulator 18, transistor 118 is not connected between node 40 and node 114. Similarly, transistor 120 is not connected between node 36 and node 100. Transistor 118 is connected in series with a transistor 132, different from transistor 32, between nodes 114 and 24. Similarly, transistor 120 is connected in series with a transistor 136, different from transistor 28, between nodes 100 and 24.

[0069] Transistors 132 and 136 are, for example, insulated gate field effect transistors (MOSFETs). Transistors 132 and 136 are preferably P-channel transistors.

[0070] In other words, a conduction node, for example the source, of the transistor 118 is, as in [Fig.2], connected, preferably connected, to the node 114 and another conduction node of the transistor 118 is connected, preferably connected, to a node 134. A conduction node of the transistor 132, for example the source, is connected, preferably connected, to the node 24 and another conduction node of the transistor 132, for example the drain, is connected, preferably connected, to the node 134. The control node of the transistor 132, for example the gate, is connected, preferably connected, to the node 134.

[0071] In addition, a conduction node, for example the source, of the transistor 120 is, as in [Fig.2], connected, preferably connected, to the node 100 and another conduction node of the transistor 120 is connected, preferably connected, to a node 138. A conduction node of the transistor 136, for example the source, is connected, preferably connected, to the node 24 and another conduction node of the transistor 136, for example the drain, is connected, preferably connected, to the node 138. The control node of the transistor 136, for example the gate, is connected, preferably connected, to the node 138.

[0072] The regulator 130 further comprises transistors 140 and 142. The transistors 140 and 142 are, for example, insulated gate field effect transistors (MOSFETs). The transistors 140 and 142 are preferably P-channel transistors.

[0073] The transistor 140 is connected between the node 24 and the node 54. In other words, a conduction node of the transistor 140, for example the source, is connected, preferably connected, to the node 24 and another conduction node of the transistor 140, for example the drain, is connected, preferably connected, to the node 54.

[0074] Similarly, transistor 142 is connected between node 24 and node 48. In other words, a conduction node of transistor 142, for example the source, is connected, preferably connected, to node 24 and another conduction node of transistor 142, for example the drain, is connected, preferably connected, to node 48.

[0075] An advantage of the described embodiments is that they allow a variable bias to be applied to the two conduction terminals of the transistors of the differential pair. Thus, the response of the current regulator is faster in the event of variation on the output node.

[0076] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, Miller capacitors 124 and 126 may be present, arranged in the same locations as in the embodiment of [Fig. 3], in the embodiment of [Fig. 4].

[0077] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A device comprising a voltage regulator (18, 122, 130), the regulator comprising: first (88) and second (90) branches, each first (88) and second (90) branch comprising first (92, 106), second (94, 108) and third (96, 110) transistors connected in series, in this order, between a first node (24) for applying a supply voltage (VDD) and a second node (46) for applying a reference voltage, the control nodes of the first transistors (92, 106) of the first (88) and second (90) branches being connected together, the control node of the third transistor (96, 110) of each first (88) and second (90) branch being connected to the midpoint of the first (92, 106) and second (94, 108) transistors of the same branch; a fourth transistor (118) connected between the midpoint (44) of the second (108) and third (110) transistors of the second branch (90) and a third node (40);and a fifth transistor (120) connected between the midpoint (100) of the second (94) and third (108) transistors of the first branch (88) and a fourth node (36), the control nodes of the fourth transistor (118) and of the second transistor (94) of the first branch (88) being connected together to a node for applying a set voltage (Vref), the control nodes of the fifth transistor (120) and of the second transistor (108) of the second branch (90) being connected together to an output node (22) of the regulator.;

2. The device of claim 1, wherein the first transistors (92, 106) of the first (88) and second (90) branches are P-channel MOSFET transistors, the second (94, 108) and third (96, 110) transistors of the first (88) and second (90) branches are N-channel MOSFET transistors.

3. A device according to claim 1 or 2, wherein the regulator comprises, connected in this order in series between the first (24) and second (46) nodes, sixth (82) and seventh (80) transistors, a first resistor (78), and eighth (60) and ninth (62) transistors, the control node of the sixth transistor (82) being connected to the midpoint of the seventh transistor (62) and the resistor (78), the control node of the sixth transistor (82) being further connected to the control nodes of the first transistors (92, 106) of the first (88) and second (90) branches, the control node of the seventh transistor (80) being connected to the midpoint of the transistor (60) and the resistor (78).

4. A device according to claim 3, wherein the regulator comprises, connected in this order in series between the first (24) and second (46) nodes, a current source (74), a second resistor (72), and tenth (56) and eleventh (58) transistors, the control node of the tenth transistor (56) being connected to the midpoint of the second resistor (72) and the current source (74) and to the control node of the eighth transistor (62), the control node of the eleventh transistor (58) being connected to the control node of the ninth transistor (62).

5. Device according to claim 3 or 4, in which the regulator comprises twelfth (28), thirteenth (50) and fourteenth (52) transistors connected, in this order, in series between the first (24) and second (46) nodes, a control node of the fourteenth transistor (52) being connected to the control node of the third transistor (96) of the first branch (88), a control node of the thirteenth transistor (50) being connected to the control node of the eighth transistor (60).

6. Device according to claim 5, in which the regulator comprises fifteenth (32), sixteenth (42) and seventeenth (44) transistors connected, in this order, in series between the first (24) and second (46) nodes, a control node of the seventeenth transistor (44) being connected to the control node of the third transistor (110) of the second branch (90), a control node of the sixteenth transistor (42) being connected to the control node of the eighth transistor (60), a control node of the fifteenth transistor (32) being connected to the control node of the twelfth transistor (28).

7. A device according to any one of claims 1 to 6, wherein the regulator comprises an eighteenth transistor (26) connected between the first node (24) and the output node (22) of the regulator.

8. A device according to claim 3 and claim 5 or 6, wherein the regulator comprises a nineteenth transistor (30), the nineteenth transistor (30) being connected in series between the twelfth (28) and thirteenth (50) transistors, a control node of the nineteenth transistor (30) being connected to the control node of the seventh transistor (80), a control node of the twelfth transistor (28) being connected to the midpoint of the nineteenth (30) and thirteenth (50) transistors.

9. The device of claim 8, wherein the regulator comprises a twentieth transistor (34), the twentieth transistor (34) being connected in series between the fifteenth (32) and sixteenth (42) transistors, a control node of the twentieth transistor (34) being connected to the control node of the nineteenth transistor (36).

10. A device according to claims 7 and 9 as appended to claim 6, wherein a control node of the eighteenth transistor (26) is connected to the midpoint of the twentieth (34) and sixteenth (42) transistors.

11. A device according to claims 6 and 7, wherein a control node of the thirteenth transistor (28) is connected to the midpoint of the thirteenth (28) and fourteenth (50) transistors, a control node of the eighteenth transistor (26) being connected to the midpoint of the fifteenth (32) and sixteenth (42) transistors.

12. A device according to any one of claims 7 to 11 as appended to claim 6, wherein the regulator comprises a first (124) Miller capacitor, the first capacitor being connected between the output node of the regulator and the midpoint of the sixteenth (42) and seventeenth (44) transistors.

13. A device according to any one of claims 1 to 12, wherein the regulator comprises a second (126) Miller capacitor, the second capacitor being connected between the output node of the regulator and the control node of the third transistor of the first branch.

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