Substrate and its manufacturing process for the realization of a wide bandgap bidirectional switch

Abstract

The invention provides a substrate and its manufacturing method for producing a bidirectional switch. This method comprises: transferring a first seed layer (21) of a wide-bandgap polar semiconductor material onto the front face of a substrate, and transferring a second seed layer (22) of said wide-bandgap polar semiconductor material onto the rear face of the substrate. These transfers are carried out so as to expose a first type surface (F1) of the first seed layer (21) and a first type surface (F1) of the second seed layer (22), a second type surface (F2) of the first seed layer (21), and a second type surface (F2) of the second seed layer (22), being at the interface with the front and rear faces of the substrate, respectively. (See Figure 4 for abbreviations.)

Description

Title of the invention: Substrate and its manufacturing process for the realization of a wide-bandgap bidirectional switch. Technical field

[0001] The field of the invention is that of bidirectional switches made of wide bandgap materials such as gallium nitride (GaN) and silicon carbide (SiC). The invention relates more particularly to a substrate and its manufacturing process for producing a bidirectional switch with vertically connected back-to-back transistors. Previous technique

[0002] In power electronics applications such as electric vehicles, renewable energy production, vehicle-to-vehicle communication, and energy storage, bidirectional switches are particularly useful. These switches allow for efficient control of energy flow in both directions, ensuring reliable and safe operation under various operating conditions.

[0003] In the power device market, currently dominated by silicon devices, devices based on wide bandgap materials such as GaN and SiC are gradually increasing their market share. These latter devices can operate at significantly higher temperatures and voltages while offering higher power levels and lower losses.

[0004] Bidirectional GaN-based switches typically have a lateral structure as shown, for example, in Figure 15(a) of article [1] referenced at the end of the description. The separation between the drain and gate electrodes determines the breakdown voltage of these switches. The greater the separation, the higher the voltage that the switch can block. However, this results in a large on-chip footprint.

[0005] Bidirectional SiC-based switches, such as those shown in Figure 15(b) of the same article [1], typically comprise two transistors sharing a common drain. These switches exhibit two drift regions, one for each polarity of the blocking voltage. This also results in a significant on-chip footprint.

[0006] One solution to this space constraint problem is to connect two MOS transistor cells vertically back-to-back as shown in Figure 15(d) of the same article [1] so that they share a common migration region. This connection can be made in a source configuration Common or common drain. The common-source configuration allows bidirectional blocking and conduction control with a single gate control. The common-drain configuration requires two separate gate controls.

[0007] As reported in article [2] referenced at the end of the description, achieving this back-to-back vertical connection requires the implementation of double-sided lithography processes on a single-crystal SiC substrate forming the shared migration region. The single-crystal SiC shared migration region has a thickness of 250 pm and high resistivity: a differential on-state resistance of 140 mQ.cm² is thus observed.

[0008] Furthermore, the shared migration layer in SiC, by virtue of its polar nature, has the characteristic of having, on one side, a surface composed mainly of silicon atoms (a so-called Si-type surface) and, on the other side, a surface composed mainly of carbon atoms (a so-called C-type surface). The MOS transistor cell fabricated on the Si-type surface therefore exhibits different properties from the MOS transistor cell fabricated on the C-type surface.

[0009] Indeed, the surface state of a layer formed by epitaxial growth differs depending on whether the layer is formed on a Si-type surface or a C-type surface. On the one hand, on a C-type surface, the surface after epitaxy is rather flat without macroscopic steps. On the other hand, on a Si-type surface, the surface after epitaxy exhibits terraces of 200–600 nm with steps of 2–8 nm.

[0010] Furthermore, the oxidation of SiC occurs with kinetics 8 to 15 times faster on the C-type surface than on the Si-type surface. After oxidation, the band gap height is higher on the Si-type surface (2.7-2.8 eV) than on the C-type surface (2.4-2.5 eV).

[0011] As reported in article [2], one consequence of the different properties is a very different threshold voltage between the two surfaces. This threshold voltage is indeed 13.7 V at room temperature on the C-type surface and 7.3 V on the Si-type surface. Furthermore, the difference in trap density at the interface makes the channel of the transistor prepared on the MOS transistor cell fabricated on the C-type surface much more sensitive to temperature variations than the MOS transistor cell fabricated on the Si-type surface. Description of the invention

[0012] The invention aims to provide a solution for the design of a bidirectional switch in which the vertically connected back-to-back MOS transistors have similar properties.

[0013] To this end, the invention proposes a method for manufacturing a substrate for the realization of a bidirectional switch with vertically connected transistors dos- backpack, including: - the supply of a support substrate having a front face and a rear face; - the transfer on the front face of the support substrate of a first seed layer in a polar semiconductor material with a wide band gap, said first seed layer having a surface of a first type and a surface of a second type; - the transfer on the back face of the support substrate of a second seed layer in said polar wide bandgap semiconductor material, said second single-crystal layer having a surface of the first type and a surface of the second type.

[0014] The reports are made so as to expose the surface of the first type of the first germ layer and the surface of the first type of the second germ layer, the surface of the second type of the first germ layer and the surface of the second type of the second germ layer being at the interface with respectively the front face and the back face of the support substrate.

[0015] Some preferred but not limiting aspects of this process are as follows: - the transfer of each of the first and second seed layers onto the front and back faces of the support substrate respectively includes: • the bonding of a second type surface of a donor substrate of said polar wide bandgap semiconductor material onto the front and back faces of the support substrate respectively, the donor substrate having been previously subjected to an implantation of ionic species through its second type surface to form a weakening plane; • the supply of thermal and / or mechanical energy to separate the donor substrate at the level of the embrittlement plane. - it further includes the growth, on each of the first and second seed layers placed on the front and back faces of the support substrate respectively, of a migration layer in a wide bandgap semiconductor material. - the migration layer deposited on each of the first and second germ layers has a thickness between 5 and 100 pm. - the migration layer deposited on each of the first and second germ layers is boosted. - It also includes the implantation of N-type or P-type impurities in the migration layer deposited on each of the first and second seed layers. - It further includes the deposition of a grid oxide layer on the migration layer deposited on each of the first and second seed layers and the formation of a grid electrode on the grid oxide layer. - the supporting substrate is made of a material which has an electrical resistivity of less than 20 mQ.cm. - the support substrate is a substrate of silicon carbide, aluminum nitride, diamond or gallium oxide. - the support substrate has a thickness of between 100 and 500 µm, preferably between 300 and 400 µm. - each of the first and second germ layers has a thickness less than or equal to lOpm. - the surfaces of the first type and the second type of each of the first germ layer and the second germ layer are faces perpendicular, within 15°, to opposite crystalline directions. - each of the first and second seed layers is a SiC layer whose first type surface is a Si type surface. - each of the first and second seed layers is a GaN layer whose first type surface is a Ga type surface.

[0016] The invention also relates to a substrate for the realization of a bidirectional switch with vertically connected back-to-back transistors, comprising: - a support substrate having a front face and a rear face; - a first seed layer attached to the front face of the support substrate, the first seed layer being made of a polar semiconductor material with a wide band gap and having a surface of a first type and a surface of a second type, the surface of the second type of the first seed layer being at the interface with the front face of the support substrate; - a second seed layer attached to the back face of the support substrate, the second seed layer being made of said wide band gap polar semiconductor material and having a surface of the first type and a surface of the second type, the second type surface of the second seed layer being at the interface with the back face of the support substrate.

[0017] The invention also relates to a bidirectional switch with vertically connected back-to-back transistors, incorporating a substrate as shown above. Brief description of the drawings

[0018] Other aspects, objects, advantages and features of the invention will become clearer upon reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the drawings attached to which:

[0019] - [Fig.1] illustrates different manufacturing stages of the substrate according to the invention;

[0020] - [Fig.2] is a schematic view of a substrate according to the invention;

[0021] - [Fig. 3] is another schematic view of a substrate according to the invention after implementation of a step for forming migration layers;

[0022] - [Fig. 4] is a schematic view of a substrate according to the invention following the fabrication of MOS cells in the migration layers.

[0023] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0024] The invention relates to a substrate and its manufacturing process for the realization of a wide bandgap bidirectional switch whose transistors are vertically connected back-to-back.

[0025] With reference to [Fig. 1](A), such a method comprises providing a support substrate 1 having a front face and a back face. This support substrate 1 can be made of a wide bandgap material, for example, silicon carbide (e.g., of the μ3-SiC type), aluminum nitride, diamond, or gallium oxide. By wide bandgap, we typically mean a bandgap wider than that of silicon, typically between 1.5 and 7 eV. The support substrate 1 is preferably a substrate with very low electrical resistivity, i.e., a substrate having an electrical resistivity less than or equal to 20 mΩ·cm. The support substrate is, for example, polycrystalline, particularly if it is made of silicon, diamond, or aluminum nitride.

[0026] The substrate 1 can have a thickness between 100 and 500 µm, preferably between 300 and 400 µm. For a substrate with a diameter of 150 mm (for example, polycrystalline SiC), this thickness corresponds to the industry SEMI standard. For a substrate with a diameter of 200 mm (for example, polycrystalline SiC), this thickness may require adjustment compared to the current standard of 500 µm. In all cases, in addition to the thickness that must be adjusted prior to bonding, it may be advisable to perform surface preparation suitable for bonding on both the front and back faces of the substrate 1.

[0027] As illustrated in [Fig. 2], the process further comprises transferring a first seed layer 21 onto the front face of the support substrate 1 and transferring a second seed layer 22 onto the back face of the support substrate 1. A seed layer is defined as a single-crystal growth seed layer. Each of the first and second seed layers 21, 22 may have a thickness less than or equal to 10 pm, for example, a thickness between 400 and 800 nm.

[0028] The seed layers 21, 22 are made of a polar material with a wide band gap. This material can be SiC (for example, 4H-SiC or 6H-SiC) or GaN. It should be noted that seed layers of SiC or GaN can be transferred onto a polycrystalline SiC support substrate.

[0029] Due to their polar nature, the germ layers 21, 22 have the characteristic of having, on one face, a surface of a first type Fl and, on the other face, a surface of a second type F2.

[0030] The surfaces of the first type Fl and the second type F2 correspond to faces perpendicular, within 15°, to opposite crystal directions. For example, these crystal directions correspond to the positive direction along the c-axis (+c, plane (0001)) and the negative direction along the c-axis (-c, plane (000-1)). Thus, the surface of the first type Fl can be defined as a surface whose crystal disorientation with respect to the (0001) axis of the crystal is less than 15°. Similarly, the surface of the second type F2 can be defined as a surface whose crystal disorientation with respect to the (000-1) axis of a crystal is less than 15°. It should be noted that this disorientation is motivated by the need for step-edge growth to promote the growth of a polytype or to minimize antiphase walls.

[0031] In the case of SiC, the Si face is the face oriented along the (0001) direction, while the C face is the face oriented along the (000-1) direction. The surface of the first type Fl is then a Si-type surface consisting mainly of silicon atoms, while the surface of the second type F2 is then a C-type surface consisting mainly of carbon atoms.

[0032] In the case of GaN, the Ga face is the face oriented along the (0001) direction, while the N face is the face oriented along the (000-1) direction. The surface of the first type Fl is then a Ga-type surface consisting mainly of gallium atoms, while the surface of the second type F2 is then an N-type surface consisting mainly of nitrogen atoms.

[0033] The respective orientations of the first germ layer 21 on the front face of the support substrate and of the second germ layer 22 on the back face of the support substrate are arranged so as to expose the first type Fl surface of the first germ layer 21 and the first type Fl surface of the second germ layer 22. Thus, the second type F2 surface of the first germ layer 21 and the second type F2 surface of the second germ layer 22 are at the interface with the front and back faces of the support substrate, respectively. The first type Fl surface is preferably the Si type surface in the case of SiC and the Ga type surface in the case of GaN. This facilitates the formation of epitaxy of SiC or GaN, respectively, on the first type Fl surfaces of the germ layers 21 and 22.It should be noted in this regard that the surface of the first type Fl of each of the germ layers 21, 22 preferably has an off-cut orientation suitable for crystal growth on it, for example an off-cut between 4 and 8° in the case of SiC.

[0034] In a preferred embodiment, the transfer of each of the first and second seed layers 21, 22 onto the front and back faces of the support substrate respectively is carried out in accordance with the Smart Cut™ process. These transfers then include the bonding (see [Fig. 1](B)) respectively onto the front and back faces of the support substrate 1 of a second-type surface of a donor substrate 2 made of said polar wide-bandgap semiconductor material, the donor substrate having been previously subjected to an implantation of ionic species through its second-type surface to form a weakening plane 3 and to an input of thermal and / or mechanical energy to separate the donor substrate at the level of the weakening plane (see [Fig. 1](C)) and thus effect the transfer of the seed layer from the donor substrate to the support substrate (see Fig. 1(D)).Figures 1(B)-1(D) represent the transfer of the first germ layer 21 onto the front face of the support substrate 1. It is understood that identical steps are implemented to carry out the transfer of the second germ layer 22 onto the back face of the support substrate 1.

[0035] The bonding can be carried out in accordance with the techniques set out in patents FR 3 117 666 B1 and FR 3 112 240 B1. It is also possible to carry out a direct bonding with surface activation (so-called SAB for "Surface Activated Bonding") or a bonding exploiting a conductive or semiconducting bonding layer (for example in Si or W).

[0036] Optionally, after the transfer of the seed layers 21 and 22, a so-called "finishing" annealing can be provided, allowing to strengthen the bonding and / or to reactivate the dopants in the seed layers 21 and 22 (since the implantation of ionic species is likely to damage the crystal lattice of these layers and therefore reduce the rate of active dopants).

[0037] In one possible embodiment, the successive transfer of the germ layers 21 and 22 is preceded by the successive execution of surface preparation and transfer processes on both faces of the support substrate 1. For this, two approaches can be considered.

[0038] The first approach includes the preparation, by transfer of the germ layer 21, of an intermediate substrate combining the support substrate 1 and the germ layer 21, followed, after deposition of a protective layer on the surface of the germ layer 21, by a second transfer sequence of the germ layer 22. Optionally, a migration layer 31 (described below) is deposited on the germ layer 21 before the transfer of the germ layer 22, in which case it is the surface of the migration layer 31 that is covered with a protective layer before and during the transfer of the germ layer 22.

[0039] This first approach involves chaining two sequences of the Smart Cut™ process successively, each time addressing one face of the support substrate 1. It has the advantage of reusing existing state-of-the-art technology. It also allows for the creation of a A new surface preparation sequence for substrate 1 prior to seed layer transfer 22 is required, given that the back face of a substrate is impacted during operations related to the Smart Cut™ process and the growth of the migration layer 31: roughening due to heat treatments, scratching during handling and placement / deposition on support tray (or "chuck") type equipment, and the addition of particles at each manufacturing stage. This new preparation sequence for substrate 1 prior to seed layer transfer 22 may also include a thinning step for substrate 1 if necessary.

[0040] The protection of the surface of the migration layer 31 before engaging in surface preparation and transfer of the seed layer 22 can for example consist of a deposit of a layer (or "capping") of carbon.

[0041] The second approach includes the combined preparation by successive bonding of the donor substrates of the germ layers 21 and 22, before application of a single detachment anneal, leading to the separation of three substrates, one forming the negative that gave the germ layer 21 (in other words, the part of the donor substrate remaining after transfer of the germ layer 21), the other substrate formed by the germ layer 21, the support substrate 1 and the germ layer 22, the third the negative that gave the layer 22 (in other words, the part of the donor substrate remaining after transfer of the germ layer 22).

[0042] This second approach makes it possible to limit the thermal budget required for the production and finishing of the substrates illustrated in [Fig.3], since it is not necessary to repeat the delamination and / or finishing anneals.

[0043] This second approach, however, presents two drawbacks. Firstly, it requires handling the substrates successively from their back side. It may therefore be advisable to apply / remove protective layers (for example, by depositing a carbon resin, potentially annealed) to the back side to be handled, before applying a treatment (for example, polishing or epitaxy) to the opposite side of the substrate. Secondly, without a protective layer, this second approach requires impacting each surface successively during the treatment of an opposite side. This drawback, particularly noticeable during the growth or heat treatment stages, can be mitigated by rigorously aligning the substrates at each stage, impacting a minimum number of chips.

[0044] With reference to [Fig. 3], the process can continue with the growth, on each of the first and second seed layers 21, 22 located respectively on the front and back faces of the support substrate, of a drift layer 31, 32 in a wide bandgap semiconductor material (identical or different from that of the underlying seed layers). This can thus involve single-crystal migration layers, for example SiC layers deposited on SiC seed layers or GaN layers deposited on GaN or SiC seed layers.

[0045] The growth of each of the migration layers 31, 32 can be achieved by epitaxy, for example by chemical vapor deposition (or CVD).

[0046] The migration layer 31, 32 deposited on each of the first and second seed layer 21, 22 can have a thickness between 5 and 100pm depending on the desired blocking tension.

[0047] The migration layer 31, 32 deposited on each of the first and second seed layers 21, 22 is preferably doped, for example with n-type doping, in particular to lower its resistivity. In the case of a SiC migration layer, this may have a doping level between 10¹³ and 10¹⁷ atoms / cm³.

[0048] In a preferred application, the support substrate 1 is made of a material with a resistivity lower than that of the migration layer material, preferably a resistivity less than 20 mΩ·cm. Taking the example of a polycrystalline SiC support substrate, this has a resistivity between 1 and 10 mΩ·cm. Such a resistivity is so low that the two migration layers 31, 32 can be considered as connected by a conducting wire. It follows that the equivalent electrical thickness of the support substrate is reduced by up to 20 times. Considering an optimal configuration for a polycrystalline SiC support substrate (support substrate thickness of 100 pm and a resistivity of 1 mQ.cm), we observe a differential resistance in the forward state as low as 0.01 mQ.cm2, equivalent to that of a monocrystalline SiC substrate of 5 pm thickness and significantly lower than that (140 mQ.cm2) observed in article [2] with a shared migration region in the form of a 250 pm thick single-crystal SiC substrate.

[0049] The process can be continued with the fabrication of all or part of the electronic components on each side of the substrate, i.e., in each of the migration regions 31, 32, notably by means of double-sided lithography steps. In particular, the process can include carrying out steps conventionally implemented in the field to form a MOS transistor from each of the migration layers 31, 32.

[0050] The method can thus include the implantation of N-type or P-type impurities in the migration layer 31, 32 deposited on each of the first and second seed layers. In the embodiment shown in [Fig. 4], this implantation makes it possible to form P-doped wells 33 and, within these, N+-doped bands 34 and P+-doped bands 35. The implantation also makes it possible to form a channel region 36 of a JFET (Junction Field-Effect Transistor) Field Effect Transistor) or a CSEL (for Charge Storage Loyer) load storage layer.

[0051] The process may also include the deposition of a grid oxide layer 37 on the migration layer 31, 32 deposited on each of the first and second seed layers and the formation of a grid electrode 28 on the grid oxide layer 37.

[0052] The invention is not limited to the process described above but also extends to the substrate thus manufactured (at any manufacturing stage) as well as to a bidirectional switch made from such a substrate, for example in a common source or common drain configuration. References

[0053] [1] J. Huber and JW Kolar, “Monolithic Bidirectional Power Transistors,” in IEEE Power Electronics Magazine, vol. 10, no. 1, pp. 28-38, March 2023, doi: 10.1109 / MPEL.2023.3234747

[0054] [2] S. Chowdhury, C. Hitchcock, Z. Stum, RP Dahal, IB Bhat and TP Chow, “Experimental Demonstration of High-Voltage 4H-SiC Bi-Directional IGBTs,” in IEEE Electron Device Letters, vol. 37, no. 8, pp. 1033-1036, Aug. 2016, doi: 10.1109 / LED.2016.2581419

Claims

Demands

1. A method for manufacturing a substrate for a bidirectional switch with vertically connected back-to-back transistors, comprising: - the supply of a support substrate (1) having a front face and a rear face; - the transfer on the front face of the support substrate of a first seed layer (21) in a polar semiconductor material with a wide band gap, said first seed layer having a surface of a first type (F1) and a surface of a second type (F2); - the transfer on the back face of the support substrate of a second seed layer (22) in said polar wide band gap semiconductor material, said second single-crystal layer having a surface of the first type (F1) and a surface of the second type (F2); said reports being made so as to expose the surface of the first type (Fl) of the first germ layer (21) and the surface of the first type (Fl) of the second germ layer (22), the surface of the second type (F2) of the first germ layer (21) and the surface of the second type (F2) of the second germ layer (22) being at the interface with respectively the front face and the back face of the support substrate.

2. The method according to claim 1, wherein the transfer of each of the first and second germ layers (21, 22) onto the front and rear faces of the support substrate respectively comprises: - the bonding respectively on the front face and the rear face of the support substrate (1) of a surface of the second type of a donor substrate (2) made of said polar wide bandgap semiconductor material, the donor substrate having been previously subjected to an implantation of ionic species through its surface of the second type to form a weakening plane (3): - the supply of thermal and / or mechanical energy to separate the donor substrate at the level of the embrittlement plane.

3. A method according to any one of claims 1 and 2, further comprising the growth, on each of the first and second seed layer (21, 22) transferred respectively to the front and back face of the support substrate, of a migration layer (31; 32) in a wide bandgap semiconductor material.

4. Method according to claim 3, wherein the migration layer (31, 32) deposited on each of the first and second seed layer (21, 22) has a thickness between 5 and 100 pm.

5. A method according to any one of claims 3 and 4, wherein the migration layer (31, 32) deposited on each of the first and second seed layers (21, 22) is doped.

6. A method according to any one of claims 3 to 5, further comprising the implantation of N-type or P-type impurities in the migration layer (31, 32) deposited on each of the first and second seed layers.

7. A method according to claim 6, further comprising the deposition of a grid oxide layer (37) on the migration layer (31, 32) deposited on each of the first and second seed layers and the formation of a grid electrode (38) on the grid oxide layer.

8. A method according to any one of claims 3 to 7, wherein the support substrate (1) is made of a material which has an electrical resistivity of less than 20 mQ.cm.

9. A method according to any one of claims 1 to 8, wherein the support substrate (1) is a substrate of silicon carbide, aluminum nitride, diamond or gallium oxide.

10. A method according to any one of claims 1 to 9, wherein the support substrate (1) has a thickness of between 100 and 500 pm, preferably between 300 and 400 pm.

11. A method according to any one of claims 1 to 10, wherein each of the first and second germinal layers (21, 22) has a thickness less than or equal to 1 Opm.

12. A method according to any one of claims 1 to 11, wherein the surfaces of the first type (F1) and of the second type (F2) of each of the first seed layer (21) and of the second seed layer (22) are faces perpendicular, within 15°, to opposite crystal directions.

13. A method according to claim 12, wherein each of the first and of the second germ layer (21, 22) is a SiC layer whose first type surface (Fl) is a Si type surface.

14. Method according to claim 12, wherein each of the first and second seed layer (21, 22) is a GaN layer whose first type surface (Fl) is a Ga type surface.

15. Substrate for the realization of a bidirectional switch with vertically connected back-to-back transistors, comprising: - a support substrate (1) having a front face and a rear face; - a first seed layer (21) attached to the front face of the support substrate, the first seed layer being made of a polar semiconductor material with a wide band gap and having a surface of a first type (F1) and a surface of a second type (F2), the surface of the second type (F2) of the first seed layer being at the interface with the front face of the support substrate;- a second seed layer (22) reported on the rear face of the support substrate, the second seed layer being made of said polar wide bandgap semiconductor material and having a surface of the first type (F1) and a surface of the second type (F2), the surface of the second type (F2) of the second seed layer being at the interface with the rear face of the support substrate.;

16. Bidirectional switch with vertically connected back-to-back transistors, incorporating a substrate according to claim 15.

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