VERTICAL STRUCTURE POWER ELECTRONIC COMPONENT AND MANUFACTURING METHOD

Abstract

VERTICAL STRUCTURE POWER ELECTRONIC COMPONENT AND MANUFACTURING METHOD One aspect of the invention relates to a power electronic component comprising: a substrate (31) made of an electrically conductive material; a stack (32) of semiconductor layers comprising: a first semiconductor layer (321) disposed on the substrate (31) and formed of an n-type doped semiconductor material; and a second semiconductor layer (322) disposed on the first semiconductor layer (321) and formed of a p-type doped semiconductor material; the stack (32) having side walls (W) inclined at an angle (α) strictly greater than 90° with respect to a surface (S) of the substrate (31) covered by the stack (32). Figure to be published with the abstract: Figure 3

Description

Title of the invention: POWER ELECTRONIC COMPONENT WITH VERTICAL STRUCTURE AND METHOD OF MANUFACTURING Technical field

[0001] The technical field of the invention is that of power electronics. The present invention relates to a power electronic component with a vertical structure and a method for manufacturing this component. The component may be a diode or a transistor, for example of the MOSFET type (for "metal-oxide-semiconductor field-effect transistor" in English) trench. STATE OF THE ART

[0002] A high electron mobility transistor (or HEMT) is a field effect transistor that benefits from the conduction properties of a two-dimensional electron gas (or 2DEG). It comprises a vertical stack of IILN semiconductor layers on a substrate, typically made of silicon, silicon carbide or sapphire. The two-dimensional electron gas is formed by a heterojunction between a channel layer, typically made of gallium nitride (GaN), and a barrier layer, typically made of aluminum-gallium nitride (AlGaN).

[0003] This heterojunction transistor is called a lateral structure transistor, because the source electrode, the drain electrode and the gate electrode of the transistor are arranged on the same side of the substrate, the source electrode and the drain electrode being located on either side of the gate electrode.

[0004] The HEMT supports high current densities in the on-state, due to the high density of charge carriers and the high mobility of these carriers in the two-dimensional electron gas. It can also exhibit a high switching speed.

[0005] On the other hand, to obtain good voltage resistance in the blocked state, in other words a high breakdown voltage, a large spacing between the gate electrode and the drain electrode is necessary, which increases the size of the transistor.

[0006] A GaN transistor with a vertical structure can, on the other hand, have a high breakdown voltage without increasing the surface area of ​​the component, by varying the thickness of an active layer called a drift layer. This type of transistor is generally formed from a self-supporting GaN substrate.

[0007] The document [« 1.8 mQ.cm2 vertical GaN-based trench metal-oxide-semiconductor field-effect transistors on a free-standing GaN substrate for 1.2-kV-class operation », Tohru Oka et al., Appl. Phys. Express 8, 054101, 2015] describes an example of a vertical GaN transistor, slotted MOSFET type.

[0008] With reference to [Fig.l], this transistor 10 comprises a substrate 11 made of heavily n-doped GaN (n+-GaN), a drift layer 12 made of lightly n-doped GaN (n-GaN) arranged on a first face 11a of the substrate 11, a channel layer 13 made of p-doped GaN (p-GaN) arranged on the drift layer 12 and a source contact layer 14 made of heavily n-doped GaN (n+-GaN) arranged on the channel layer 13. A source electrode 15 is arranged on the source contact layer 14, while a drain electrode 16 is arranged on a second opposite face 11b of the substrate 11. Finally, a gate dielectric layer 17a and a gate electrode 17b are arranged at the bottom and against the side walls of a trench 18. The trench 18 extends to the drift layer 12 through the channel layer 13 and the source contact layer 14.

[0009] Transistor 10 of [Fig.l] has a high breakdown voltage, of the order of 1.2 kV, and a small footprint. On the other hand, it is expensive to manufacture mainly due to the use of a self-supporting GaN substrate.

[0010] The use of low-cost substrates known as foreign (to the IILN semiconductor family), such as silicon substrates, would make it possible to manufacture high-performance power electronic components on large diameter wafers (200 mm, or even 300 mm) and therefore considerably reduce the manufacturing cost of these components.

[0011] The article [“Gallium nitride vertical power de vices on foreign substrates: a review and outlook”, Yuhao Zhang et al., J. Phys. D: Appl. Phys., Vol. 51, 273001, 2018] describes several power components formed from silicon or sapphire (A12O3) substrates, in particular a GaN diode with a vertical structure and GaN transistors with a quasi-vertical structure, of the trench MOSFET type and of the FinFET type (“fin field-effect transistor” in English).

[0012] [Fig. 2] illustrates the main steps of the manufacturing process of the vertical structure GaN diode 20, described in detail in the article [“High-Performance 500 V Quasi- and Fully-Vertical GaN-on-Si pn Diodes”, Yuhao Zhang et al., IEEE Electron Device Letters, Vol. 38, No. 2, pp. 248-251, 2016]. The manufacturing process includes in particular the following steps: • the growth, from a silicon substrate 21, of a stack successively comprising buffer layers 22, a semi-insulating GaN layer 23, a heavily n-doped GaN layer (n+-GaN) 24, a lightly n-doped GaN layer (n-GaN) 25 and a p-doped GaN layer (p-GaN) 26; • etching the stack down to the substrate 21 to form an island called table ; • the formation of an anode 27 (Ni / Au ohmic contact) on the p-GaN layer 26; • the turning over and bonding of the anode-side stack 27 to a transfer substrate 31 (made of silicon) covered with metal layers 32; and • removing the growth substrate 21, the buffer layers 22 and the semi-insulating GaN layer 23; and • the formation of a cathode 28 (Ti / Al ohmic contact) on the n+ -GaN layer 24.

[0013] This GaN on silicon diode, however, has a much lower breakdown voltage than its equivalent formed from a GaN substrate, of the order of 520 V. Summary of the invention

[0014] There is therefore a need to provide a power electronic component that is inexpensive to manufacture and has better voltage resistance than the components of the prior art.

[0015] According to a first aspect of the invention, this need is tended to be satisfied by providing an electronic power component comprising: • a substrate made of an electrically conductive material; • a stack of semiconductor layers comprising: • a first semiconductor layer disposed on the substrate and formed of an n-type doped semiconductor material; and • a second semiconductor layer arranged on the first semiconductor layer and formed from a p-type doped semiconductor material.

[0016] This power electronic component is remarkable in that the stack has side walls inclined at an angle strictly greater than 90° relative to a surface of the substrate covered by the stack.

[0017] The inclination of the side walls gives the stack a flared shape. This geometry is advantageous for component voltage resistance, because it reduces the electric field at the surface of the side walls and moves the breakdown location of the component inside the stack.

[0018] In a first embodiment, the component further comprises: • a source electrode arranged on the second semiconductor layer; • a gate structure extending to the first semiconductor layer through the second semiconductor layer, the gate structure comprising a gate electrode and a gate dielectric layer; and the substrate forms a drain electrode.

[0019] According to a development of this first embodiment, the stack further comprises a source contact layer arranged between the source electrode and the second semiconductor layer.

[0020] According to another development compatible with the previous one, the stack further comprises a drain contact layer arranged between the substrate and the first semiconductor layer.

[0021] In a second embodiment: • the second semiconductor layer is structured in patterns; • the source electrode comprises several portions, each source electrode portion being arranged on a pattern; and • the grid structure comprises several portions intermingled with the patterns.

[0022] In a third embodiment, the component further comprises patterns of semiconductor material arranged on the first semiconductor layer and in which the second semiconductor layer comprises portions intermingled with the patterns, the component further comprising: • a source electrode comprising several portions, each source electrode portion being arranged on a pattern; • a gate electrode comprising several portions, each gate electrode portion being arranged on a portion of the second semiconductor layer; and wherein the substrate forms a drain electrode.

[0023] In a fourth embodiment, the component comprises an anode arranged on the second semiconductor layer and the substrate forms a cathode.

[0024] In a fifth embodiment, the component comprises an anode extending to the first semiconductor layer through the second semiconductor layer and the substrate forms a cathode, the anode being in Schottky contact with the first semiconductor layer.

[0025] According to a development of the fourth or fifth embodiment, the stack further comprises a layer of heavily doped n-type semiconductor material arranged between the substrate and the first semiconductor layer.

[0026] The component according to the first aspect of the invention may also have one or more of the characteristics below, considered individually or in all technically possible combinations: • the angle of inclination of the side walls is between 110° and 160°. • the first semiconductor layer has a thickness greater than or equal to 3 pm, preferably greater than or equal to 10 pm; • the component further comprises a metal layer arranged between the substrate and the stack; • the substrate is made of metal; and • the component further comprises a passivation layer covering the side walls of the stack.

[0027] A second aspect of the invention relates to a method of manufacturing a power electronic component, comprising the following steps: • forming a stack of semiconductor layers on a growth substrate, by successively growing by selective epitaxy a first semiconductor layer in a p-type doped semiconductor material and a second semiconductor layer in an n-type doped semiconductor material, so that the stack has side walls inclined at an angle strictly less than 90° relative to a surface of the growth substrate covered by the stack; • deposit a metallic layer on the stack; • flipping the stack and bonding the metal layer to a transfer substrate made of a conductive material; and • remove the growth substrate.

[0028] In a preferred embodiment, the method further comprises, between the step of forming the stack and the step of depositing the metal layer, the following steps: • forming a passivation layer on the side walls of the stack; and • coating the stack with a dielectric layer.

[0029] The transfer substrate is preferably made of metal, for example copper.

[0030] The growth substrate is advantageously made of silicon, silicon carbide or sapphire.

[0031] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0032] Other characteristics and advantages of the invention will emerge clearly from the description given below, for information purposes only and in no way limiting, with reference to the following figures:

[0033] [Fig.l], previously described, is a sectional view of a vertically structured field effect transistor according to the prior art;

[0034] [Fig.2], previously described, illustrates the main stages of manufacturing a diode with a vertical structure according to the prior art;

[0035] [Fig.3] is a schematic sectional view of an electronic component of power according to a first embodiment of the invention;

[0036] [Fig.4] is a schematic sectional view of an electronic component of power according to a second embodiment of the invention;

[0037] [Fig.5] is a schematic sectional view of an electronic component of power according to a third embodiment of the invention;

[0038] [Fig.6] is a schematic sectional view of an electronic component of power according to a fourth embodiment of the invention; and

[0039] Figures 7A to 7G represent steps of a method of manufacturing the power electronic component of [Fig.3].

[0040] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION

[0041] Figures 3 to 6 show in schematic sectional view different embodiments of a power electronic component 30. The component 30 can be a transistor (see Figs.3-5) or a diode (see [Fig.6]). It can switch reversibly between a first state called “on state” (or “ON state”) and a second state called “off state” (or “OFF state”). It can be used in many electronic devices, such as a power electronic module to produce an energy conversion circuit (e.g., voltage step-down or step-up converter or direct current - alternating current converter).

[0042] In a manner common to all these embodiments, the component 30 comprises: • a substrate 31 made of an electrically conductive material; • a stack 32 of semiconductor layers comprising at least: • a first semiconductor layer 321 arranged on the substrate 31; • a second semiconductor layer 322 arranged on the first semiconductor layer 321.

[0043] The substrate 31 may be made of metal, for example copper, or a degenerate semiconductor material, for example degenerate silicon. It may also comprise a layer of metal on a layer of degenerate semiconductor material (e.g. titanium on degenerate silicon).

[0044] The first semiconductor layer 321, called the drift layer or voltage withstand layer, is made of an n-type doped semiconductor material, and preferably an n-doped IILN semiconductor material such as n-doped gallium nitride (n-GaN). The concentration of n-type doping impurities in the first semiconductor layer 321 is advantageously between 1014 cm3 and 1017 cm3, for example equal to 1016 cm3.

[0045] The thickness of the first semiconductor layer 321 is advantageously su greater than or equal to 3 pm, preferably greater than or equal to 10 pm, in order to give the component 30 good voltage resistance (drain-source voltage VDS in the case of a transistor), for example of at least 1000 V.

[0046] The second semiconductor layer 322, also called the channel layer in the case of a transistor (i.e. the layer in which the conduction channel of the transistor is formed), is made of a p-type doped semiconductor material, and preferably a p-doped III-N semiconductor material such as p-doped gallium nitride (p-GaN). The thickness of the second semiconductor layer 322 may be between 200 nm and 1000 nm.

[0047] The second semiconductor layer 322 is preferably in direct contact with the first semiconductor layer 321. In other words, the stack 32 comprises a PN junction.

[0048] The semiconductor material of the second semiconductor layer 322 is preferably identical to the semiconductor material of the first semiconductor layer 321. Thus, the PN junction is a homojunction.

[0049] The component 30 comprises at least two electrodes: a first electrode formed by the substrate 31 made of electrically conductive material and a second electrode 33 arranged on the second semiconductor layer 322, opposite the substrate 31. The component 30 thus has a vertical structure, more advantageous in terms of size and / or conductivity in the on state than the horizontal and quasi-vertical structures.

[0050] The second electrode 33 is preferably made of metal, for example TiN or TiN on Ti (bilayer).

[0051] For a component 30 of the PN junction transistor or diode type, the first electrode (substrate 31) is in ohmic contact with the first semiconductor layer 321 (n-type), while the second electrode 33 is in ohmic contact with the second semiconductor layer 322 (p-type)

[0052] The component 30 may also comprise a metal layer 34 arranged between the substrate 31 and the stack 32. This metal layer 34, for example made of titanium (Ti) or formed from a titanium on aluminum bilayer (Ti / Al) improves the quality of the electrical contact between the substrate 31 (first electrode) and the first semiconductor layer 321.

[0053] To obtain a weakly resistive (ohmic) contact with the first electrode (substrate 31) and / or with the second electrode 33, the stack 32 of semiconductor layers may further comprise: • a third semiconductor layer 323 made of a heavily doped n-type semiconductor material and arranged between the substrate 31 and the first semiconductor layer 321, (the third semiconductor layer 323 becoming thus the first layer of the stack 32, starting from the substrate 31; cf. Figs.3-6); and / or • a fourth semiconductor layer 324 made of a heavily doped n-type semiconductor material and arranged between the second electrode 33 and the second semiconductor layer 322 (as the last layer of the stack 32; see Figs. 3-4).

[0054] A heavily doped n-type semiconductor material herein designates a material having a concentration of n-type doping impurities of between 1017 cm3 and 1020 cm3, for example equal to 1018 cm3.

[0055] The third and fourth semiconductor layers 323-324 are preferably made of a heavily n-doped III-N semiconductor material, for example heavily n-doped gallium nitride (n+-GaN).

[0056] The second electrode 33 is then, at least in part, separated from the second semiconductor layer 322 by the fourth semiconductor layer 324. Although this is not shown in the figures, the second electrode 33 can extend in part through the fourth semiconductor layer 324 to the second semiconductor layer 322, in order to be able to polarize the latter (instead of leaving it floating).

[0057] As illustrated in Figures 3 to 6, the stack 32 has side walls (or flanks) W inclined relative to a surface S of the substrate 31 covered by the stack 32. The angle of inclination a of the side walls W, that is to say the angle formed between the surface S of the substrate 31 and each of the side walls W of the stack 32 (measured in the trigonometric direction), is strictly greater than 90°.

[0058] Thus, the stack 32 has a flared shape. Inclined side walls W have the effect of reducing the amplitude of the electric field at the surface of these walls, at the level of the depletion zone (also called space charge zone) of the PN junction. This results in a displacement of the breakdown location of the component, from the surface to the volume of the stack 32, and therefore an increase in the breakdown voltage, as explained in the reference work [“Fundamentals of Power Semi-conductor Devices”, B. Jayant Baliga, Springer 2019, Chap.3. Breakedown Voltage, pp. 139-140],

[0059] The angle of inclination a of the side walls W is preferably strictly greater than 95° and more preferably still between 110° and 160°, in order to significantly reduce the electric field at the walls at the location of the PN junction.

[0060] Furthermore, the component 30 comprises a passivation layer 35 covering the side walls W of the stack 32. The passivation layer 35 reduces the parasitic conduction paths (and therefore the leakage currents) and further improves further the breakdown voltage of the component 30. It can be formed of a dielectric layer, for example in alumina (A12O3), a stack of dielectric sub-layers or a depleted PN junction (therefore a stack comprising an n-doped semiconductor layer and a p-doped semiconductor layer).

[0061] Finally, the component 30 may comprise a dielectric layer 36 arranged on the substrate 31 and which coats the stack 32 and the passivation layer 35, if applicable. The dielectric layer 36 is for example made of silicon dioxide (SiO2).

[0062] In the first embodiment shown in [Fig. 3], the component 30 is a trench MOSFET type transistor. The first electrode, formed by the substrate 31, is a drain electrode and the second electrode 33 is a source electrode. In addition to the drain and source electrodes, the transistor comprises a gate structure 37, of the MOS (Metal-Oxide-Semiconductor) type.

[0063] The gate structure 37 comprises a gate dielectric layer and a gate electrode separated, at least laterally, from the semiconductor layers of the stack 32 by the gate dielectric layer. The gate dielectric layer is, for example, made of silicon dioxide (SiO2), aluminum oxide (Al2O3), aluminum nitride (AIN) or silicon nitride (SiN). It may comprise several sub-layers formed from these dielectric materials. The gate electrode is preferably made of metal, for example titanium nitride (TiN).

[0064] Preferably, the stack successively comprises (starting from the substrate 31) the third semiconductor layer 323 (e.g. n+-GaN), the first semiconductor layer 321 (e.g. n-GaN), the second semiconductor layer 322 (e.g. p-GaN) and the fourth semiconductor layer 324 (e.g. n+-GaN). The third semiconductor layer 323 forms a drain contact layer and the fourth semiconductor layer 324 forms a source contact layer.

[0065] The gate structure 37 is arranged in a trench 38, which extends to the first semiconductor layer 321 through the second semiconductor layer 322 and, here, the source contact layer 324.

[0066] The source electrode 33 and the gate electrode may each comprise several portions. The portions of the same electrode are electrically connected to each other in order to be subjected to the same electrical potential. For the sake of clarity, only one portion of the gate electrode and two portions of the source electrode 31, arranged on either side of the portion of the gate electrode, have been shown in [Fig. 3]. The portions of the source electrode 33 are advantageously intermingled (or nested) with the portions of the gate electrode in order to reduce the resistance of the transistor in the on state. Several arrangements (“layout” in English) are possible for the source electrode and the gate electrode: interdigitated combs, hexagonal cell structures as described in the document [“1.8 mQ.cm2 vertical GaN-based trench metal-oxide-semiconductor field-effect transistors on a free-standing GaN substrate for 1.2-kV-class operation », Tohru Oka et al., Appl. Phys. Express 8, 054101, 2015]...

[0067] In the second embodiment shown in [Fig. 4], the component 30 is also a transistor, but of the FinFET type. The FinFET transistor of [Fig. 4] differs from the trench MOSFET transistor of [Fig. 3] essentially in that the second semiconductor layer 322 (i.e. the channel layer) and the source contact layer 324 are structured in patterns commonly called fins. These patterns can have different shapes in top view, for example a rectangular, hexagonal, circular, annular shape, etc. The source electrode 33 comprises several portions (electrically connected to each other), each source electrode portion being arranged on a fin. The gate structure 37 also comprises several portions (electrically connected to each other) intermingled with the patterns of the second semiconductor layer 322 (depending on the arrangement chosen: interdigitated combs, hexagonal cell structures, etc.).In the sectional view of [Fig.4], each portion of the gate structure 37 is disposed (in a trench 38) between two fins (and comprises a gate electrode portion separated from said fins by a portion of the gate dielectric layer).

[0068] The second p-doped semiconductor layer 322, although optional in a FinFET, gives the transistor a higher threshold voltage VTh.

[0069] In the third embodiment represented by [Fig. 5], the component 30 is a JFET type transistor (junction field-effect transistor). The component 30 comprises patterns 325 made of semiconductor material arranged on the first semiconductor layer 321. Each pattern 325 is advantageously surmounted by a portion 326 of a source contact layer (made of highly n-doped semiconductor material, for example n+-GaN) and by a portion of the source electrode 33. The patterns 325 are advantageously formed in the second semiconductor layer 322 by passivating (locally) the p-type doping impurities, thus giving the semiconductor material an intrinsic behavior.

[0070] The second semiconductor layer 322 comprises several distinct portions. The portions of the second semiconductor layer 322 are intermingled with the patterns 325. In the sectional view of [Fig. 5], the portions of the second semiconductor layer 322 are separated two by two by a pattern 325 and each surmounted by a gate electrode portion 37'.

[0071] In the fourth embodiment shown in [Fig.6], the component 30 is a PN junction diode. The first electrode, formed by the substrate 31, is a cathode and the second electrode 33 is an anode.

[0072] Finally, in a fifth embodiment not shown, the component 30 is a Schottky diode. The first electrode (cathode) is formed by the substrate 31 and the second electrode (the anode) passes through the second semiconductor layer 322 until it reaches the first semiconductor layer 321 (in the manner of the gate structure 37 of [Fig. 3]), rather than being disposed on the second semiconductor layer 322. The second electrode is in Schottky contact with the first semiconductor layer 321 (and not ohmic with the second semiconductor layer 322).

[0073] Preferably, the stack 32 of the PN junction diode ([Fig.6]) or of the Schottky diode successively comprises (starting from the substrate 31) the third semiconductor layer 323 (e.g. n+-GaN), the first semiconductor layer 321 (e.g. n-GaN) and the second semiconductor layer 322 (e.g. p-GaN).

[0074] A preferred embodiment of a method for manufacturing the component 30 will now be described with reference to FIGS. 7A to 7G, taking as an example the trench MOSFET transistor of [Fig. 3]. In this method, it is considered that the component 30 comprises the third and fourth semiconductor layers 323-324 (drain and source contact layers). However, one or both of these layers could be omitted.

[0075] Figures 7A to 7G schematically represent steps S1 to S7 of the manufacturing method.

[0076] Step SI illustrated by [Fig.7A] consists of forming the stack 32 of semiconductor layers on a growth substrate 70. The growth substrate 70 is advantageously a low-cost substrate, for example made of silicon, silicon carbide or sapphire. It is preferably covered with one or more buffer layers 71, making it possible to adapt the mesh mismatch between the growth substrate 70 and the semiconductor layers of the stack 32 and thus minimize the number of growth defects.

[0077] A first particularity of this step SI is that the stack 32 is formed by growing the semiconductor layers by epitaxy in the reverse order to that described with reference to FIGS. 3 to 6 (which is also the conventional growth order). Thus, in this preferred embodiment of the manufacturing method, the fourth highly n-doped semiconductor layer 324 (e.g. n+-GaN), the second p-doped semiconductor layer 322 (e.g. p-GaN), the first n-doped semiconductor layer 321 (e.g. n-GaN) and, finally, the third highly n-doped semiconductor layer 323 (e.g. n+-GaN) are grown successively.

[0078] A second particularity of this step SI is the use of a selective epitaxy technique commonly called SAE (for “selective area epitaxy” in English). This technique may comprise the formation of a mask (not shown) on the surface of the growth substrate 70, before or after the growth of the (or the) buffer layer(s) 71, and the growth of the semiconductor layers of the stack 32 in the recess(es) of this mask. The number of stacks 32 obtained on the growth substrate 70 is equal to the number of recesses of the mask. Thus, it is possible to form several stacks 32 called “islands” simultaneously (these stacks 32 belonging to different components or to the same component). The mask is formed from a material capable of withstanding growth temperatures, generally greater than 1000°C. This is typically a dielectric material, for example an aluminum oxide (A1OX).

[0079] It is also possible, after the growth of the buffer layer(s) 71, to etch (through a mask) the buffer layer 71 down to the growth substrate 70 to form the islands, before resuming the growth of the other semiconductor layers only on these islands. This option releases the stress in the islands, and gives the possibility of making wider islands without cracks.

[0080] A selective epitaxy technique is notably described in the article [“Selective-area growth study of GaN micropillars for quasi-vertical Schottky diodes”, A. Debald et al., Semicond. Sci. Technol., Vol. 36, 034005, 2021] for the fabrication of a Schottky diode with a quasi-vertical structure.

[0081] Epitaxial growth gives each stack 32 or island a truncated cone shape, with inclined side walls W (also called facets). The side walls W are inclined relative to a surface S' of the growth substrate 70 covered by the stack 32 by an angle a' strictly less than 90°, preferably strictly less than 85° and even more preferably between 20° and 70°. The angle a' of inclination of the side walls W of the stack 32 on the growth substrate 70 satisfies the following relationship:

[0082] [Math.l] a = 180 - a

[0083] where a is the angle of inclination of the side walls W of the stack 32 on the substrate 31 made of electrically conductive material (Figs.3-6).

[0084] The formation in island(s) also makes it possible to reduce the stresses of the epitaxial layers induced by growth and then cooling and consequently to increase the thickness of the epitaxial layers compared to conventional epitaxy (“full wafer”). This is particularly interesting for the first semiconductor layer 321, or drift layer, which ensures the voltage resistance of the component. Thus, a drift layer 321 with a thickness greater than 3 μm, preferably greater than or equal to 10 μm, and with low stress can be obtained.

[0085] Finally, the formation in island(s) makes it easier to activate the second semiconductor layer 322 (for example in p-GaN) after the SI growth step, by allowing the hydrogen contained in this layer to escape through the sides.

[0086] Step S2 of [Fig.7B] is an optional step consisting of forming the passivation layer 35 on the side walls W of the stack 32.

[0087] In step S3 of [Fig.7C], the stack 32 is coated with the dielectric layer 36. The coating of the stack 32 may comprise a step of depositing a dielectric material until the stack 32 is completely covered, then a planarization step (for example by chemical-mechanical polishing) so that the dielectric layer 36 forms a flat surface with the upper face of the stack 32. The upper face of the stack 32 is formed by the semi-conductor layer epitaxied last, here the third semi-conductor layer 323.

[0088] Then, in S4 (see [Fig.7D]), the metal layer 34 is formed on the stack 32. The metal layer 34 is here in contact with the third semiconductor layer 323. The metal layer 34 can cover both the stack 32 and the dielectric layer 36 or only the stack 32, as shown in [Fig.7D]

[0089] It is also possible to deposit the metal layer 34 on the passivation layer 35 and the upper face of the stack 32, before the step of coating with the dielectric layer 36. A planarization step is then carried out so that the dielectric layer 36 forms a flat surface with the portion of the metal layer 34 arranged on the upper face of the stack 32.

[0090] With reference to [Fig.7E], the method for manufacturing the component 30 then comprises a step S5 of turning the stack 32 over and bonding it, via the metal layer 34, to the substrate 31 made of conductive material. This substrate 31, called the transfer substrate, is advantageously made of metal, for example copper, in order to improve the heat dissipation of the component 30 and the electrical conductivity of the first electrode (drain electrode in the example of the transistor). The bonding is then of the direct metal-metal type (without adding material).

[0091] Then, in step S6 of [Fig.7F], the growth substrate 70 and the buffer layer 71 are removed so as to expose the stack 32, and more particularly the semi-conductor layer epitaxied first, here the fourth semi-conductor layer 324. The majority of the growth substrate 70 can be removed by grinding, by laser lift-off or by a technique called spalling and described in the document [“Kerf-less removal of Si, Ge, and III-V layers by controlled spalling to enable low-cost PV technologies”, Stephen W. Bedell et al., IEEE Journal of Photovoltaics, Vol. 2, No. 2, pp. 141-147, 2012]. Then, the remaining portion of the growth substrate 70 and the buffer layer 71 are removed by dry etching, to avoid damaging the electrically active layers.

[0092] Step S7 represented by [Fig.7G] relates to the formation of the second electrode 33 (source electrode) on the exposed surface of the stack (here the fourth semiconductor layer 324) and a gate structure 37 in the case of a transistor.

[0093] In the example of the MOSFET transistor, the gate structure 37 is a MOS gate structure comprising a gate dielectric layer and a gate electrode (separated at least laterally from the semiconductor layers by the gate dielectric layer). Its formation preferably comprises the following steps: • the formation of a trench 38 extending to the first semiconductor layer 321, preferably by etching the fourth semiconductor layer 324, the second semiconductor layer 322 and possibly a surface portion of the first semiconductor layer 321'; • the formation of the gate dielectric layer at least against the side walls of the trench 38, the bottom of the trench 38 being able to be covered by a so-called passivation layer made of an electrically insulating material; • filling the trench 38 with an electrically conductive material, preferably a metal, to form the gate electrode.

[0094] To manufacture the FinFET type transistor of [Fig.4], step S7 comprises etching several trenches 38 through the fourth semiconductor layer 324 and the second semiconductor layer 322, so as to structure these layers in the form of fins, then forming the different portions of the source electrode 33 on the fins. The gate dielectric layer and the gate electrode are then formed in the different trenches 38 as described previously.

[0095] The manufacturing method of the JFET type transistor of [Fig. 5] comprises steps S1-S6 of FIGS. 7A-7H, with the difference that the stack 32 of epitaxial layers in step S1 is devoid of the fourth semiconductor layer 324. The manufacturing method then comprises a step of passivating the p-type doping impurities (e.g. magnesium ions) in regions of the second semiconductor layer 322, to form the patterns 325 made of semiconductor material (with intrinsic behavior), and preferably a step of implanting n-type doping impurities to form the portions 326 of the source contact layer located on the patterns 325. The p-type doping impurities are preferably passivated (i.e. made inactive) by implantation of hydrogen ions.The source electrode 33 and gate electrode 37' portions are then formed, respectively on the portions 326 of the source contact layer and on the portions of the second semiconductor layer 322.

[0096] In the case of the PN junction diode (see [Fig.6]), the stack 32 of epitaxial layers in the SI stage is also devoid of the fourth semi- conductive 324 and only the second electrode 33 (anode) is formed on the stack 32 during step S7.

[0097] In the case of the Schottky junction diode, a trench extending to the first semiconductor layer 321 is formed, preferably by etching the second semiconductor layer 322 and possibly a surface portion of the first semiconductor layer 321, then the trench is filled with a metal making it possible to form a Schottky contact with the first semiconductor layer 321.

[0098] Whatever the component, the manufacturing method may also include a step of forming a contact pad on the rear face of the transfer substrate 31, to facilitate the subsequent connection of the component after it has been packaged.

Claims

Claims

1. Power electronic component (30) comprising: - a substrate (31) made of an electrically conductive material; - a stack (32) of semiconductor layers comprising: • a first semiconductor layer (321) arranged on the substrate (31) and formed of an n-type doped semiconductor material; and • a second semiconductor layer (322) arranged on the first semiconductor layer (321) and formed of a p-type doped semiconductor material; characterized in that the stack (32) has side walls (W) inclined at an angle (a) strictly greater than 90° relative to a surface (S) of the substrate (31) covered by the stack (32).

2. Component (30) according to claim 1, wherein the angle (a) of inclination of the side walls (W) is between 110° and 160°.

3. Component (30) according to one of claims 1 and 2, in which the first semiconductor layer (321) has a thickness greater than or equal to 3 pm, preferably greater than or equal to 10 pm.

4. Component (30) according to any one of claims 1 to 3, further comprising a metal layer (34) disposed between the substrate (31) and the stack (32).

5. A component (30) according to any one of claims 1 to 4, wherein the substrate (31) is made of metal.

6. A component (30) according to any one of claims 1 to 5, further comprising: - a source electrode (33) disposed on the second semiconductor layer (322); - a gate structure (37) extending to the first semiconductor layer (321) through the second semiconductor layer (322); and wherein the substrate (31) forms a drain electrode.

7. A component (30) according to claim 6, wherein the stack (32) further comprises a source contact layer (324) disposed between the source electrode (33) and the second semiconductor layer (322).

8. Component (30) according to one of claims 6 and 7, wherein the stack (32) further comprises a drain contact layer (323) disposed between the substrate (31) and the first semiconductor layer (321).

9. Component (30) according to any one of claims 6 to 8, wherein: - the second semiconductor layer (322) is structured in patterns; - the source electrode (33) comprises several portions, each source electrode portion being arranged on a pattern; and - the gate structure (37) comprises several portions intermingled with the patterns.

10. A component (30) according to any one of claims 1 to 5, further comprising patterns (325) of semiconductor material arranged on the first semiconductor layer (321) and wherein the second semiconductor layer (322) comprises portions intermingled with the patterns (325), the component further comprising: - a source electrode (33) comprising several portions, each source electrode portion being arranged on a pattern (325); - a gate electrode (37') comprising several portions, each gate electrode portion being arranged on a portion of the second semiconductor layer (322); and wherein the substrate (31) forms a drain electrode.

11. A component (30) according to any one of claims 1 to 5, further comprising an anode (33) disposed on the second semiconductor layer (322) and wherein the substrate (31) forms a cathode.

12. A component (30) according to any one of claims 1 to 5, further comprising an anode (33) extending to the first semiconductor layer (321) through the second semiconductor layer. conductive (322), the anode being in Schottky contact with the first semiconductor layer (321), and in which the substrate (31) forms a cathode.

13. Component (30) according to one of claims 11 and 12, wherein the stack further comprises a layer of heavily doped n-type semiconductor material (323) disposed between the substrate (31) and the first semiconductor layer (321).

14. A component (30) according to any one of claims 1 to 13, further comprising a passivation layer (35) covering the side walls (W) of the stack (32).

15. Method for manufacturing a power electronic component (30), comprising the following steps: - forming (SI) a stack (32) of semiconductor layers on a growth substrate (70), by successively growing by selective epitaxy a semiconductor layer (322) made of a p-type doped semiconductor material and a semiconductor layer (321) made of an n-type doped semiconductor material, so that the stack (32) has side walls (W) inclined at an angle (a') strictly less than 90° relative to a surface (S') of the growth substrate (70) covered by the stack (32); - depositing (S4) a metal layer (34) on the stack (32); - turning over (S5) the stack (32) and bonding the metal layer (34) to a transfer substrate (31) made of a conductive material; and - removing (S6) the growth substrate (70).

16. Method according to claim 15, further comprising, between the step (S1) of forming the stack (32) and the step (S4) of depositing the metal layer (34), the following steps: - forming (S2) a passivation layer (35) on the side walls (W) of the stack (32); and - coating (S3) the stack (32) with a dielectric layer (36).

17. A method according to either of claims 15 and 16, wherein the substrate of report (31) is made of metal.

18. A method according to any one of claims 15 to 17, wherein the growth substrate (70) is silicon, silicon carbide or sapphire.

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