Two-dimensional matrix quantum device and method for producing the same

Abstract

Title: Two-dimensional matrix quantum device and method for producing same The invention relates to a quantum device comprising: • a plurality of quantum dots (120) arranged in a two-dimensional matrix, • a first level (G1) of grids (200) surmounting the plurality of quantum dots (120), • a second level (G2) of grids (600) surmounting the first level (G1) of grids, • a plurality of charge detectors (4, 4a, 4'a, 4b, 4'b) capacitively coupled to the quantum dots (120), Advantageously, the plurality of charge detectors (4, 4a, 4'a, 4b, 4'b) is integrated in one of the first and second levels (G1, G2) of grids, each charge detector comprising a portion (400, 400a, 400b) located between the grids (200, 600) of the level (G1, G2) of grids considered. The invention also relates to a method for producing such a quantum device. Figure for the abstract: Fig.12

Description

Title of the invention: Two-dimensional matrix quantum device and method of producing same Technical field

[0001] The present invention relates to the field of microelectronics and quantum electronics in particular. It finds a particularly advantageous application in the production of two-dimensional matrices of quantum bit devices (called quantum bits or qubits) integrating a compact charge detection system. STATE OF THE ART

[0002] The technical field is that of quantum information. The bits of information called qubits are here made in quantum boxes which ensure the confinement of elementary charges (electrons or holes). Quantum information is, for example, coded on the spin of these particles.

[0003] To encode and manipulate the information contained in quantum dots, for example to initialize a quantum dot with a single charge, it is generally necessary to know the number of charges present in the quantum dot(s). One solution to know this number of charges is to place a charge detector near the quantum dots.

[0004] The operation of such a charge detector relies on capacitive coupling with the quantum dot. It is therefore advantageous to minimize the distance between the detector and the quantum dot to increase the sensitivity of the detector. The environment of the quantum dot also includes the control elements of the qubits, typically control gates. The size and sensitivity of the detector are therefore important aspects of a quantum bit device.

[0005] Charge detectors based on a conductive element connected to one or more charge reservoirs, such as single electron transistors (SETs) or single reservoir quantum dots (SLQDs), are among the most efficient and sensitive detectors. In particular, they allow an absolute reading of the number of charges in a quantum dot.

[0006] This type of charge detector nevertheless requires one or more polarization grids to operate as well as one or more carrier reservoirs. This considerably increases the size of this type of detector.

[0007] For one-dimensional (1D) arrays of quantum dots, SET-type charge detectors can be integrated in the same plane as the quantum dots, opposite them.

[0008] For two-dimensional (2D) networks of quantum dots, the size of SET type detectors limits the possibilities of integrating these detectors near the quantum dots.

[0009] According to a possibility disclosed for example in the document “Shared control of a 16 semiconductor quantum dot crossbar array, F. Borsoi et al., Condensed Matter, 2022”, the detectors are integrated on the periphery of the quantum dots. This limits the size of the 2D matrices to a few quantum dots per side.

[0010] According to another possibility disclosed in document FR3066297, the SET type detectors are integrated in a first plane located under a second plane comprising the quantum dots. These first and second planes are separated by at least one level comprising the polarization grids of the detectors, and interconnections between the detectors and the quantum dots. The second plane comprising the quantum dots is also surmounted by levels of control grids of the quantum dots. Such an architecture is very complex to produce.

[0011] Furthermore, manufacturing constraints limit the proximity of the detectors to approximately 100 nm or more from the quantum dots to be detected.

[0012] The control and / or bias grids may also partially screen the quantum dots for the detectors, which reduces the intensity of the capacitive coupling and the sensitivity of the detector.

[0013] There is therefore a need for a quantum device with a two-dimensional (2D) matrix of quantum dots comprising less bulky and / or better integrated charge detectors. One objective of the invention is to meet this need, and to at least partially overcome the drawbacks of known solutions.

[0014] In particular, an object of the invention is a quantum device comprising charge detectors having improved compactness. Another object of the invention is a method of producing such a device.

[0015] Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0016] To achieve this objective, according to one embodiment, a quantum device is provided comprising: - a semiconductor layer in which is formed, during operation of the quantum device, a plurality of quantum dots arranged in a two-dimensional matrix, - a plurality of charge detectors capacitively coupled to the quantum dots of the plurality of quantum dots - a first set of grids including box control grids quantum, overlying the semiconductor layer, - a second set of grids comprising grids intended to form at least one charge reservoir for the charge detectors.

[0017] Advantageously, each charge detector comprises a portion located between the grids of the first set of grids. Preferably, the grids of the second set of grids form a single charge reservoir common to each charge detector.

[0018] Thus, unlike the solution disclosed by document FR3066297 in which the charge detectors are arranged on a distinct level and separated from the control gate levels of the quantum dots, the device according to the invention integrates the detectors directly within the control gate levels of the quantum dots. This makes it possible to improve the compactness of the device. The detectors can also be closer to the quantum dots. The device architecture proposed by the present invention is also less complex to produce using standard microelectronics technological processes.

[0019] Another aspect of the invention relates to a method of producing such a quantum device, comprising: - a formation of a semiconductor layer intended to comprise a plurality of quantum dots arranged in a two-dimensional matrix, - a formation of a first set of grids comprising control grids of the quantum dots, surmounting the semiconductor layer, - a formation of a second set of grids comprising grids intended to form at least one charge reservoir for charge detectors (4, 4a, 4'a, 4b, 4'b), - a formation of a plurality of charge detectors capacitively coupled to the quantum dots of the plurality of quantum dots, said formation being configured such that each charge detector comprises a portion located between the gates of the first set of gates. BRIEF DESCRIPTION OF THE FIGURES

[0020] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0021] [Fig. 1 A] [Fig.2A] [Fig.3A] [Fig.4A] [Fig.5A] [Fig.ôA] [Fig.7A] [Fig.8A] [Fig.9A] [Fig. 10 A][Fig. 11 A] The figures nA (n = 1... 11) schematically illustrate in cross-section the manufacturing steps of a quantum device, according to an embodiment of the present invention.

[0022] [Fig.lB][Fig.2B][Fig.3B][Fig.4B][Fig.5B][Fig.6B][Fig.7B][Fig.8B][Fig.9B][Fig.l0 B][Fig.l IB] The figures nB (n = 1.. 11) schematically illustrate in top view the manufacturing steps illustrated in the corresponding figures nA, according to an embodiment of the present invention.

[0023] [Fig.lOC] The [Fig.lOC] illustrates in perspective the manufacturing step of the quantum device illustrated in figures 10A and 10B, according to an embodiment of the present invention.

[0024] [Fig. 12] [Fig. 12] schematically illustrates in cross-section a quantum device, according to a first embodiment of the present invention.

[0025] [Fig. 13] [Fig. 13] schematically illustrates in cross-section a quantum device, according to a second embodiment of the present invention.

[0026] [Fig. 14] [Fig. 14] schematically illustrates in top view a quantum device, according to a first embodiment of the present invention.

[0027] [Fig. 15] [Fig. 15] schematically illustrates in top view a quantum device, according to a second embodiment of the present invention.

[0028] [Fig. 16] [Fig. 16] schematically illustrates in top view a quantum device, according to a third embodiment of the present invention.

[0029] [Fig. 17] [Fig. 17] schematically illustrates in top view a quantum device, according to a fourth embodiment of the present invention.

[0030] [Fig. 18] [Fig. 18] schematically illustrates in cross-section a quantum device, according to a third embodiment of the present invention.

[0031] [Fig. 19] [Fig. 19] schematically illustrates in cross-section a quantum device, according to a fourth embodiment of the present invention.

[0032] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, on the schematic diagrams, the thicknesses and / or the dimensions of the different layers, patterns and reliefs are not representative of reality. For reasons of clarity, not all of the alphanumeric references are systematically repeated from one figure to another. It is understood that the elements already described and referenced, when they are reproduced in another figure, typically bear the same alphanumeric references, even if these are not explicitly mentioned. A person skilled in the art will easily identify the same element reproduced in different figures. DETAILED DESCRIPTION

[0033] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0034] According to one example, each charge detector is located under the grids of the second set of grids. Typically, the grids of the second set of grids are arranged in lines parallel to each other, and the charge detectors are located within these lines. A grid of the second set, in the form of a line, thus typically surmounts several charge detectors.

[0035] According to one example, the device comprises a dielectric layer on the semiconductor layer, and the portion of each charge detector located between the gates of the first set of gates is directly in contact with said dielectric layer. The detectors are thus as close as possible to the quantum dots.

[0036] According to one example, the at least one charge reservoir is a single charge reservoir common to each charge detector, for a given grid of the second set of grids. Typically, when the second grids are arranged in lines parallel to each other, the charge reservoir is common to each charge detector for a given row of second grids. When there are several rows of second grids, said rows being independent of each other, there are typically as many charge reservoirs as there are independent rows.

[0037] According to one example, each charge detector comprises a conductive island and at least one charge reservoir separated from each other by a dielectric barrier. Thus, each detector may be of the single electron transistor SET (acronym for “Single Electron Transistor”) type or of the single reservoir quantum dot SLQD (acronym for “Single Load Quantum Dot”) type.

[0038] According to one example, the portion of each charge detector located between the gates of the first set is a conductive island. The conductive island is sensitive to the electrostatic environment. It is thus advantageously located near the quantum dots located below the level of control gates considered. The sensitivity of charge detection in the quantum dots is thus improved.

[0039] According to one example, each charge detector comprises a single charge reservoir. According to this example, the charge detectors are preferably of the single reservoir quantum dot (SLQD) type.

[0040] According to an alternative example, each charge detector comprises two separate charge reservoirs, of source and drain type. According to this example, the charge detectors are preferably of the single electron transistor SET type.

[0041] According to one example, the portion of each charge detector is located between the control gates of the first set of control gates. The proximity of the charge detector to the quantum dots is optimized. The detection sensitivity is optimized.

[0042] According to one example, each control grid of the first set comprises a first stage and a second stage separated by a dielectric barrier, the device being configured so that all the second stages are independently polarizable, so as to control a chemical potential of the portion of each charge detector. The portion of each charge detector located between the control grids of the first set can thus be polarized according to an extended polarization range. A scan on the polarizations of this polarization range can advantageously be carried out in order to determine a number of charges present in the quantum dot(s) located under said first set.

[0043] According to one example, the first stages of the control gates of the first set are configured to control the quantum dots.

[0044] According to one example, the control grids of the first set and the grids of the second set form a grid, in projection according to a first direction z, and the quantum boxes are located directly above the empty spaces of the grid.

[0045] According to one example, the charge detectors are located directly above tunnel barriers separating the quantum dots from each other.

[0046] According to one example, the two-dimensional matrix of quantum dots is organized according to a first network having a first pitch and the charge detectors are organized according to a second network having a second pitch equal to twice the first pitch.

[0047] According to one example, the plurality of quantum dots comprises more than sixteen quantum dots arranged in a two-dimensional matrix, preferably more than thirty-two quantum dots arranged in a two-dimensional matrix, preferably more than one hundred and twenty-eight quantum dots arranged in a two-dimensional matrix.

[0048] According to one example, the plurality of quantum dots comprises N quantum dots and the plurality of charge detectors comprises N / 2 charge detectors, such that each charge detector is associated with two quantum dots of the two-dimensional matrix. In a known manner, in particular by the prior measurement of stability diagrams, the signals detected by the detectors can be linked to one or the other of the quantum dots. This allows the distinction between the different quantum dots associated with a detector. The association of two quantum dots with a detector finds for example an advantageous application in the context of the implementation of a quantum error correcting code, for example of the “surface code” type.In this case, it is necessary to read only the information stored on one half of the quantum boxes corresponding to "measurement" qubits, read periodically to detect errors, the other half of the quantum boxes corresponding to "data" qubits not measured during a calculation so as not to impact the quantum information that they encode.

[0049] According to an example, for four adjacent control grids of the first set successively called first, second, third and fourth control grids of control, the device comprises a first conductive island of a first charge detector between the first and second control grids, said first conductive island being surmounted by a first portion of dielectric barrier connecting the first and second control grids, and a second conductive island of a second charge detector between the third and fourth control grids, said second conductive island being surmounted by a second portion of dielectric barrier connecting the third and fourth control grids.

[0050] According to one example, the two-dimensional matrix of quantum dots and the charge detectors are respectively organized according to networks having the same pitch.

[0051] According to one example, the plurality of quantum dots comprises N quantum dots and the plurality of charge detectors comprises N charge detectors, such that each charge detector is associated with a quantum dot of the two-dimensional array. Each detector is thus typically associated with a single quantum dot. This makes it possible to globally increase the charge detection signal across the entire array. The detection is thus less noisy and more precise.

[0052] According to one example, the first and second sets of gates are configured to locally confine a particle or a charge. According to one example, the device includes a third set of gates configured to control a chemical potential of the quantum dots. This allows the quantum dots to be filled or emptied. This allows the quantum information to be manipulated.

[0053] According to one example, the plurality of charge detectors is integrated into one of the first, second and third sets of grids. For example, the integration of the charge detectors into the third set of grids and directly above a quantum dot allows for better measurement sensitivity with respect to the latter.

[0054] According to one example, the grids of the second set are configured to drive the charge detectors by reflectometry, preferably by common potential, by being connected to an induction and a capacitance in series. The charge detectors are thus perfectly integrated within the sets of grids, in particular between the control grids of the quantum dots.

[0055] According to one example, forming the plurality of charge detectors comprises forming conductive islands between the control gates of the first set of gates, and forming a dielectric barrier on said conductive islands, prior to forming the second set of gates. The dielectric barrier typically separates the conductive islands from a charge reservoir.

[0056] According to one example, the control grids of the first set are oriented in a second direction x and the grids of the second set are oriented in a third direction y perpendicular to the second direction x.

[0057] According to one example, the formation of the dielectric barrier comprises a struc turation configured to form dielectric barrier portions in the form of strips oriented diagonally with respect to the second and third x, y directions, such that the formed charge detectors are fewer in number than the formed quantum dots, typically half as many. The intersections, in projection along the first z direction, between the strips and the control grids of the first level define the charge detectors. Depending on the width and orientation of the strips, it is thus possible to form a sub-array of detectors among the two-dimensional array of quantum dots.

[0058] According to one example, the method comprises connecting the grids of the second set to an induction and a capacitance in series, and driving the charge detectors by reflectometry.

[0059] Unless incompatibility exists, it is understood that all of the above optional features may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention. The features and advantages of one aspect of the invention, for example the device or the method, may be adapted mutatis mutandis to the other aspect of the invention.

[0060] It is specified that, in the context of the present invention, the terms “on”, "overcomes", "covers", "underlies", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition, assembly or application of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0061] A substrate, a film, a layer, “based” on a material A, is understood to mean a substrate, a film, a layer comprising this material A only or this material A and possibly other materials, for example doping elements or alloying elements.

[0062] In the following, the first, second and / or third sets of gates are also called respectively first, second and / or third levels of gates. A “level” of gates, such as a level of interconnections or metallization, typically corresponds to a layer or a set of layers, structured, of a microelectronic circuit, according to the meaning usually given in the field of microelectronics.

[0063] In operation, the device comprises quantum dots regularly distributed in the semiconductor layer, in the form of a two-dimensional matrix. These quantum dots are not necessarily physically defined when the device does not work. Quantum dots can correspond to confinement zones created in the semiconductor layer when one or more voltages are applied to the different gates of the device. The semiconductor layer is therefore suitable for the formation of quantum dots.

[0064] Several embodiments of the invention implementing successive steps of the manufacturing method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them.

[0065] Furthermore, the term “step” means the carrying out of a part of the method, and can designate a set of sub-steps.

[0066] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term step does not necessarily mean unitary and inseparable actions in time and in the sequence of the phases of the process.

[0067] The term “selective etching with respect to” or “etching exhibiting selectivity with respect to” means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and exhibiting an etching rate of the material A greater than the etching rate of the material B. The selectivity is the ratio between the etching rate of the material A and the etching rate of the material B. It is denoted SA:B. A selectivity SA:b of 10:1 means that the etching rate of the material A is 10 times greater than the etching rate of the material B.

[0068] A preferably orthonormal reference frame, comprising the x, y, z axes, is shown in the attached figures. When a single reference frame is shown on the same sheet of figures, this reference frame applies to all the figures in this sheet.

[0069] In the present patent application, we will preferably speak of thickness for a layer or a film, and of height for a device or a structure. The thickness is taken along a direction normal to the main extension plane of the layer or film. Thus, a surface layer of silicon typically has a thickness along z. A gate pattern formed on such a surface layer has a height along z. The relative terms "on", "overcomes", "under", "underlying" refer to positions taken along the z direction. A "lateral" dimension corresponds to a dimension along a direction of the xy plane. A "lateral" or "laterally" extension is understood to mean an extension along one or more directions of the xy plane.

[0070] An element located “perpendicular to” or “in line with” another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the cross-sectional figures.

[0071] The terms "substantially", "approximately", "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and..." and equivalents mean that the limits are included, unless otherwise stated.

[0072] Figures nA (n=1... 11) schematically illustrate in cross-section steps of manufacturing a quantum device comprising charge detectors, according to a first embodiment. Figures nB (n=1... 11) schematically illustrate in perspective the manufacturing steps illustrated in the corresponding figures nA.

[0073] As illustrated in Figures 1A, 1B, the first steps consist in providing a substrate 1 of the silicon on insulator SOI type, comprising a support layer 10, typically a bulk silicon substrate called "bulk", a buried oxide layer 11 called "BOX", and a surface silicon layer 12 called topSi. The topSi layer 12 typically has a thickness ei2 of the order of 5 nm to 20 nm. This topSi layer 12 is intended to contain the quantum dots. These quantum dots can be formed subsequently, by simple electrostatic confinement within the topSi layer 12. Alternatively, they can be created physically, for example by forming regularly distributed holes in the topSi layer 12 (not illustrated).

[0074] As illustrated in Figures 2A, 2B, a gate stack 2 is formed on the substrate 1. This stack 2 is intended to form, after structuring, the first gate level of the device. This stack 2 typically comprises, along z starting from the substrate 1, a dielectric layer 20, a first conductive layer 21, for example based on metal or doped polycrystalline silicon, a dielectric layer 22, a second conductive layer 23, for example based on metal or doped polycrystalline silicon. The stack 2 is topped by a masking layer 3 typically comprising a silicon oxide layer 30 and / or a silicon nitride layer 31. This masking layer 3 is intended to form, after structuring, a hard mask for etching the stack 2.

[0075] As illustrated in Figures 3A, 3B, the masking layer 3 is first structured by lithography and etching to form a hard mask 300 defining first gate patterns on the stack 2, aligned along x in this example. The stack 2 is then etched, typically by anisotropic dry etching along z, to form gates 200. Reactive ion etching (RIE) or plasma etching based on fluorocarbon species can be used to successively etch the layers 23, 22 and 21 of the stack 2. The etching of the stack 2 is configured to stop on the dielectric layer 20. Each gate 200 thus comprises a first stage 210, a dielectric barrier 220, a second stage 230. The gates 200 form the first gate level G1 of the device. The gates 200 are topped at this stage by the hard mask 300. The gates 200 have a width dimension along y Lg. The first stage 210 of the gates 200 is typically configured to control qubits in the quantum dots. The second stage 230 of the gates 200 is typically configured to control the charge detectors associated with the quantum dots.

[0076] As illustrated in Figures 4A, 4B, a dielectric layer 24, also called liner, is deposited conformally on the exposed parts of the dielectric layer 20, on the sides of the gates 200 and on the hard mask 300. The spaces located between the gates 200 are then filled by deposition of a conductive layer, for example based on polycrystalline silicon called polySi. Planarization, typically by chemical mechanical polishing CMP, is then carried out with a stop on the dielectric layer 24 at the top of the gates surmounted by the hard mask. Conductive islands 400 are thus formed between the gates of the first level of gates of the device. These conductive islands 400 are typically “self-aligned”. They are directly formed between the gates of the first level, and therefore aligned with respect to said gates, without this requiring a lithography step.

[0077] As illustrated in Figures 5A, 5B, a dielectric layer 25 is deposited continuously on all of the conductive islands 400 and on the exposed parts of the dielectric layer 24. The dielectric layer 25 is intended to separate a reservoir of electrical charges, typically located above this layer 25, from the conductive islands 400 located under this layer 25. The dielectric layer 25 is configured to remain permeable to the passage of electrical charges between the charge reservoir and the conductive islands 400.

[0078] As illustrated in Figures 6A, 6B, this dielectric layer 25 is then structured by etching, typically in the form of strips oriented diagonally with respect to the underlying grids, for example at 45° with respect to the axes, x, y ([Fig.6B]). This makes it possible to periodically cover one conductive island 400 out of two in the x and y directions. Thus, as illustrated in [Fig.6A] in transverse section along the section line AA shown in [Fig.6B], for four successive grids 200a, 200b, 200c, 200d, only the conductive islands 400a and 400c located respectively between the grids 200a, 200b and 200c, 200d, are covered by a portion 250 of dielectric barrier. The conductive island 400b located between the grids 200b, 200c is not covered along the section line AA.

[0079] As illustrated in Figures 7A, 7B, a conductive layer 41, typically based on polySi, is then deposited, then planarized by CMP. This conductive layer 41 is intended to form a charge reservoir for the conductive islands 400a, 400c of the charge detectors. The conductive layer 41 is separated from the conductive islands 400a, 400c by the dielectric barrier portions 250.

[0080] As illustrated in FIGS. 8A, 8B, a masking layer 5 typically comprising a silicon nitride layer 50 and / or a silicon oxide layer 51 is deposited on the conductive layer 41.

[0081] As illustrated in Figures 9A, 9B, the masking layer 5 is then structured by lithography and etching to form a hard mask 500 defining second grid patterns, aligned along y in this example.

[0082] As illustrated in Figures 10A, 10B, 10C, an anisotropic dry etching along z is then carried out, to form gates 600. This etching typically makes it possible to remove the parts of the layer 41 and the conductive islands 400 not covered by a hard mask. The etching is typically configured to stop in the hard mask 300, at the SiN layer of the hard mask 300, in the hard mask 500, at the SiN layer of the hard mask 500, and on the dielectric layer 20 between the hard masks 300, 500.

[0083] As illustrated in Figures 1 1A, 1 1B, the exposed parts of the hard masks 300, 500, mainly based on SiN, are selectively removed at the dielectric layer 20 at the bottom of the trenches and cavities bordering the gates 200, 600. The top of the gates 200, 600 based on poly Si is thus exposed. A siliciding of the gates 200, 600 is then carried out, in a conventional manner, to obtain top parts 201, 601 of silicided gates. Seen from above ([Fig. 11B]), the mesh of the gates 200, 600 makes it possible to define a two-dimensional matrix of quantum boxes or quantum dots. The quantum dots 120 are located in the inter-grid spaces, between the grids 200, 600, in projection along z ([Fig.llB]). The quantum dots 120 are confined in the topSi. The charge detectors 4 are integrated in the levels Gl, G2 of the device grids.

[0084] The device illustrated in [Fig. 12] is thus obtained. This device comprises quantum dots 120 in the topSi layer 12, located between the different intersections of grids 200, 600. The device further comprises SLQD type charge detectors 4a, 4c partly formed between the grids 200 under the dielectric barrier portions 250. The charge detectors are located above the tunnel barriers 121 connecting two quantum dots together. In this example, the device comprises half as many charge detectors as quantum dots 120. Operation of the charge detectors 4a, 4c by reflectometry can advantageously be envisaged, by connecting the grids 600 to a reflectometry system comprising a capacitance and an induction in series. This configuration corresponds to detection by common potential reflectometry, insofar as all the detectors 4a, 4c are probed by the same grid 600.

[0085] A polarization of the charge detectors 4a, 4c via the second stages 230 of grids 200 can advantageously be carried out, to probe the presence of charges in the quantum boxes 120. The charge detector 4a and the charge detector 4c can be polarized independently of one another.

[0086] Other embodiments of the device can be envisaged.

[0087] [Fig. 13] illustrates an embodiment of the device in which a detector of charge 4a, 4b, 4c is provided for each quantum box 120. In this embodiment, the dielectric layer 25 forms a continuous barrier above the conductive islands of the charge detectors 4a, 4b, 4c. It is sufficient not to structure this dielectric layer 25, as illustrated in FIGS. 5A, 5B, to obtain the device illustrated in [Fig. 13]. The detectors can operate by common potential reflectometry, as previously. A polarization of the charge detectors 4a, 4b, 4c by means of the second stages 230 of grids 200 can advantageously be carried out, to probe the presence of charges in the quantum boxes 120. The charge detectors 4a, 4b, 4c can be polarized independently.

[0088] [Fig. 14] illustrates in top view a 2D network arrangement of boxes quantum dots 120 located between the intersections of the grids 200 and 600, associated with a sub-array of detectors 4 half as numerous as the quantum dots 120, similarly to the architecture presented in [Fig. 12]. In this example, holes 122 are formed in the topSi layer 12 to add structural confinement helping to define the quantum dots 120. The quantum dots 120 are located between the holes 122. The detectors 4 are located directly above certain tunnel barriers separating the quantum dots 120.

[0089] [Fig. 15] illustrates in top view a 2D network arrangement of boxes quantum dots 120 located between the intersections of the grids 200 and 600, associated with a sub-array of detectors 4 as numerous as the quantum dots 120, similarly to the architecture presented in [Fig.13]. In this example, holes 122 are formed in the topSi layer 12 to add structural confinement helping to define the quantum dots 120. The quantum dots 120 are located between the holes 122. The detectors 4 are located directly above the tunnel barriers separating the quantum dots 120.

[0090] [Fig. 16] illustrates in top view a 2D network arrangement of boxes quantum dots 120 located between the intersections of grids 200 and 600. In this example, grids 600, 600' of the second level have been doubled - the pitch of the network along y has been halved - so as to obtain both control of the tunnel barriers by the grids 600 and control of the chemical potentials of the quantum dots by the grids 600'. In this example, the detector sub-array 4 includes half as many detectors as the quantum dots 120. The quantum dots 120 are located between the holes 122. The detectors 4 are located directly above certain quantum boxes 120. The grids 600, 600' of the second level can be produced simultaneously. Alternatively, the grids 600' can be formed after the grids 600, for example on a third level of grids of the device. Those skilled in the art will know how to adapt the formation of the different levels of grids according to requirements.

[0091] [Fig. 17] illustrates in top view a 2D network arrangement of quantum dots 120 located between the intersections of the grids 200 and 600. In this example, a third level G3 of grids 800 has been added above the first and second levels of grids 200, 600 to control the chemical potentials of the quantum dots 120. The charge detectors 4 can be integrated under the grids 800 of this third level. According to a possibility not illustrated, the charge detectors 4 can be integrated between the grids 800 of this third level, for example directly above certain tunnel barriers.

[0092] The device architecture of the present invention thus makes it possible to envisage a multitude of configurations for the placement of the detectors 4 between the grids of at least one level of grids. Such an architecture is advantageously compact and versatile.

[0093] Figures 18 and 19 illustrate two other embodiments of the device in which the charge detectors are of the SET type, with two charge reservoirs 41s, 41d “source and drain” associated with a conductive island via the dielectric barrier 250, 25. The two charge reservoirs 41s, 41d are typically separated by a dielectric block 251 surmounting the dielectric barrier 250, 25, approximately equidistant from the gates 200.

[0094] [Fig. 18] illustrates a first embodiment in which the device comprises half as many SET type charge detectors 4'a, 4'c as quantum dots 120. The two charge reservoirs 41s, 41d are typically connected to the gate 600 by vias 700. As previously, operation of the charge detectors 4'a, 4'c by reflectometry can advantageously be envisaged, by connecting the gates 600 to a reflectometry system.

[0095] [Fig. 19] illustrates a second embodiment in which the device comprises as many charge detectors 4'a, 4'b, 4'c of SET type as quantum dots 120. The two charge reservoirs 41s, 41d are typically connected to the gate 600 by vias 700. As previously, operation of the charge detectors 4'a, 4'b, 4'c by reflectometry can advantageously be envisaged, by connecting the gates 600 to a reflectometry system.

[0096] In view of the above description, it appears clearly that the proposed device offers a particularly effective and versatile solution for integrating charge detectors into the grid levels associated with a 2D matrix of quantum dots, in improving the compactness and sensitivity of this quantum device.

[0097] The invention is not limited to the embodiments previously described.

Claims

Claims

1. Quantum device comprising: • a semiconductor layer (12) adapted to form a plurality of quantum dots (120) arranged in a two-dimensional matrix of quantum dots; • a plurality of charge detectors (4, 4a, 4'a, 4b, 4'b) capacitively coupled to the quantum dots (120) of the plurality of quantum dots, • a first set (Gl) of gates (200) comprising control gates of the quantum dots (120), surmounting the semiconductor layer (12), • a second set (G2) of gates (600) comprising gates intended to form at least one charge reservoir for the charge detectors (4, 4a, 4'a, 4b, 4'b), the device being characterized in that each charge detector (4, 4a, 4'a, 4b, 4'b) comprises a portion (400, 400a, 400b) located between the gates (200) of the first set (Gl) of gates.

2. Device according to the preceding claim in which the at least one charge reservoir is a single charge reservoir common to each charge detector (4, 4a, 4'a, 4b, 4'b), for a given grid (600) of the second set (G2) of grids (600).

3. Device according to any one of the preceding claims comprising a dielectric layer (20) on the semiconductor layer (12), wherein the portion (400, 400a, 400b) of each charge detector (4, 4a, 4'a, 4b, 4'b) located between the gates (200) of the first set (Gl) of gates is directly in contact with said dielectric layer (20).

4. Device according to any one of the preceding claims in which the portion of each charge detector located between the grids of the first set (Gl) is a conductive island (400, 400a, 400b).

5. Device according to any one of the preceding claims in which each control grid (200) of the first set (Gl) comprises a first stage (210) and a second stage (230) separated by a dielectric barrier (220), the device being configured so that all the second stages (230) are independently polarizable between them, so as to control a chemical potential of the portion (400, 400a, 400b) of each charge detector.

6. Device according to the preceding claim in which the first stages (210) of the control grids of the first set are configured to control the quantum dots (120).

7. Device according to any one of the preceding claims in which the charge detectors (4) are located directly above the quantum dots (120), in a first direction z.

8. A device according to any preceding claim wherein the two-dimensional matrix of quantum dots (120) is arranged in a first array having a first pitch and the charge detectors (4, 4a, 4'a, 4b, 4'b) are arranged in a second array having a second pitch equal to twice the first pitch, and wherein the plurality of quantum dots (120) comprises N quantum dots and the plurality of charge detectors (4, 4a, 4'a) comprises N / 2 charge detectors, such that each charge detector is associated with two quantum dots (120) of the two-dimensional matrix.

9. Device according to the preceding claim in combination with claim 3 wherein, for four adjacent control grids (200a, 200b, 200c, 200d) of the first set (Gl), successively called first, second, third and fourth control grids, the device comprises a first conductive island (400a) of a first charge detector (4a) between the first and second control grids (200a, 200b), said first conductive island (400a) being surmounted by a first portion (250) of dielectric barrier connecting the first and second control grids (200a, 200b), and a second conductive island (400c) of a second charge detector (4c) between the third and fourth control grids (200c, 200d), said second conductive island (400c) being surmounted by a second portion (250) of dielectric barrier connecting the third and fourth control grids (200c, 200d).

10. A device according to any one of claims 1 to 7 wherein the two-dimensional matrix of quantum dots (120) and the charge detectors (4, 4a, 4'a, 4b, 4'b) are respectively organized according to networks having the same pitch, and wherein the plurality of quantum dots (120) comprises N quantum dots and the plurality of charge detectors (4, 4a, 4'a, 4b, 4'b) comprises N charge detectors, such that each charge detector is associated with a quantum dot. quantum (120) of the two-dimensional matrix.

11. Device according to any one of the preceding claims in which the grids (600) of the second set (G2) are configured to drive the charge detectors (4, 4a, 4'a, 4b, 4'b) by reflectometry, preferably by common potential, by being connected to an induction and a capacitance in series.

12. A method of producing a quantum device according to any one of the preceding claims, comprising: • forming a semiconductor layer (12) intended to comprise a plurality of quantum dots (120) arranged in a two-dimensional matrix, • forming a first set (G1) of gates (200) comprising control gates of the quantum dots, overlying the semiconductor layer (12), • forming a second set (G2) of gates (600) comprising gates intended to form at least one charge reservoir for charge detectors (4, 4a, 4'a, 4b, 4'b), • forming a plurality of charge detectors (4, 4a, 4'a, 4b, 4'b) capacitively coupled to the quantum dots (120) of the plurality of quantum dots, said formation being configured so that each charge detector includes a portion (400, 400a,400c) located between the grids of the first set (Gl) of grids.,

13. A method according to the preceding claim wherein the formation of the plurality of charge detectors (4, 4a, 4'a, 4b, 4'b) comprises the formation of conductive islands (400, 400a, 400b, 400c) between the control gates (200) of the first set (G1) of gates, and the formation of a dielectric barrier (250, 25) on said conductive islands, before the formation of the second set (G2) of gates.

14. Method according to the preceding claim in which the control grids (200) of the first set (G1) are oriented in a second direction x and the grids (600) of the second set (G2) are oriented in a third direction y perpendicular to the second direction x, and in which the formation of the dielectric barrier comprises a structuring configured to form portions (250) of dielectric barrier in the form of strips oriented diagonally with respect to the second and third directions x, y, so that the charge detectors (4, 4a, 4c) formed are fewer in number than the quantum dots (120) formed, typically half as many.

15. Method according to any one of claims 12 to 14 comprising a connection of the grids (600) of the second set (G2) to an induction and a capacitance in series, and a control of the charge detectors (4, 4a, 4'a, 4b, 4'b) by reflectometry.

Images